diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b44b6c17169..c0d52fd1b63 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -94,6 +94,13 @@ config ARCH_CHIP_TIVA ---help--- TI Tiva TM4C architectures (ARM Cortex-M4) +config ARCH_CHIP_LPC11XX + bool "NXP LPC11xx" + select ARCH_CORTEXM0 + select ARCH_HAVE_CMNVECTOR + ---help--- + NXP LPC11xx architectures (ARM Cortex-M0) + config ARCH_CHIP_LPC17XX bool "NXP LPC17xx" select ARCH_CORTEXM3 @@ -281,6 +288,7 @@ config ARCH_CHIP default "kinetis" if ARCH_CHIP_KINETIS default "kl" if ARCH_CHIP_KL default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA + default "lpc11xx" if ARCH_CHIP_LPC11XX default "lpc17xx" if ARCH_CHIP_LPC17XX default "lpc214x" if ARCH_CHIP_LPC214X default "lpc2378" if ARCH_CHIP_LPC2378 @@ -386,7 +394,8 @@ config ARMV7M_MPU select ARCH_USE_MPU ---help--- Build in support for the ARM Cortex-M3/4 Memory Protection Unit (MPU). - Check your chip specifications first; not all Cortex-M3/4 chips support the MPU. + Check your chip specifications first; not all Cortex-M3/4 chips + support the MPU. config ARMV7M_MPU_NREGIONS int "Number of MPU regions" @@ -460,6 +469,9 @@ endif if ARCH_CHIP_LM || ARCH_CHIP_TIVA source arch/arm/src/tiva/Kconfig endif +if ARCH_CHIP_LPC11XX +source arch/arm/src/lpc11xx/Kconfig +endif if ARCH_CHIP_LPC17XX source arch/arm/src/lpc17xx/Kconfig endif diff --git a/arch/arm/include/lpc11xx/chip.h b/arch/arm/include/lpc11xx/chip.h new file mode 100644 index 00000000000..92d2a1d9b18 --- /dev/null +++ b/arch/arm/include/lpc11xx/chip.h @@ -0,0 +1,141 @@ +/************************************************************************************ + * arch/arm/include/lpc11xx/chip.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H +#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_LPC1115) +# define LPC111x 1 /* LPC111x family */ +# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */ +# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */ +# define LPC11_CPUSRAM_SIZE (8*1024) +# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */ +# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */ +# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */ +# define LPC11_NUSBHOST 0 /* No USB host controller */ +# define LPC11_NUSBOTG 0 /* No USB OTG controller */ +# define LPC11_NUSBDEV 1 /* One USB device controller */ +# define LPC11_NCAN 1 /* One CAN controller */ +# define LPC11_NI2S 0 /* No I2S modules */ +# define LPC11_NDAC 0 /* No DAC module */ +#else +# error "Unsupported LPC11xx chip" +#endif + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. The processor implements only + * bits[7:3] of each field, bits[2:0] read as zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the irqsave() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */ diff --git a/arch/arm/include/lpc11xx/irq.h b/arch/arm/include/lpc11xx/irq.h new file mode 100644 index 00000000000..20c4def1d34 --- /dev/null +++ b/arch/arm/include/lpc11xx/irq.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/arm/include/lpc11xxx/irq.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +#if defined(CONFIG_ARCH_CHIP_LPC1115) +#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */ +#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */ +#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */ +#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */ +#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */ +#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */ +#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */ +#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */ +#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */ +#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */ +#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */ +#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */ +#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */ +#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */ +#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */ +#define LPC11_IRQ_I2C (31) /* Vector 31: I2C */ +#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */ +#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */ +#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */ +#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */ +#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */ +#define LPC11_IRQ_UART (37) /* Vector 37: UART */ + /* Vector 38: Reserved */ + /* Vector 39: Reserved */ +#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */ +#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */ +#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */ + /* Vector 43: Reserved */ +#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */ +#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */ +#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */ +#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */ +#endif + +#define NR_VECTORS (64) /* 64 vectors */ +#define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */ diff --git a/arch/arm/src/lpc11xx/Kconfig b/arch/arm/src/lpc11xx/Kconfig new file mode 100644 index 00000000000..6524ea48420 --- /dev/null +++ b/arch/arm/src/lpc11xx/Kconfig @@ -0,0 +1,263 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +comment "LPC11xx Configuration Options" + +choice + prompt "NXP LPC11XX Chip Selection" + default ARCH_CHIP_LPC1115 + depends on ARCH_CHIP_LPC11XX + +config ARCH_CHIP_LPC1114 + bool "LPC1114" + select ARCH_FAMILY_LPC111X + +config ARCH_CHIP_LPC1115 + bool "LPC1115" + select ARCH_FAMILY_LPC111X + +endchoice + +config ARCH_FAMILY_LPC111X + bool + +menu "LPC11xx Peripheral Support" + +choice + prompt "System Clock:" + default LPC11_INTRCOSC + +config LPC11_INTRCOSC + bool "Internal RC" + +config LPC11_MAINOSC + bool "External Crystal" + +endchoice + +choice + prompt "SysTick clock source" + default LPC11_SYSTICK_CORECLK + +config LPC11_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config LPC11_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + +config LPC11_PLL + bool "PLL" + default y + +config LPC11_UART0 + bool "UART0" + select ARCH_HAVE_UART0 + default y + +config LPC11_CAN0 + bool "CAN0" + default n + +config LPC11_SPI + bool "SPI" + default n + +config LPC11_SSP0 + bool "SSP0" + default n + +config LPC11_SSP1 + bool "SSP1" + default n + +config LPC11_I2C0 + bool "I2C0" + default n + +config LPC11_TMR0 + bool "Timer 0" + default n + +config LPC11_TMR1 + bool "Timer 1" + default n + +config LPC11_WDT + bool "WDT" + default n + +config LPC11_ADC + bool "ADC" + default n + +config LPC11_FLASH + bool "FLASH" + default n + +endmenu + +menu "Serial driver options" + depends on LPC11_UART0 || LPC11_UART1 || LPC11_UART2 || LPC11_UART3 || LPC11_UART4 + +config SERIAL_TERMIOS + bool "Serial driver TERMIOS supported" + depends on LPC11_UART0 || LPC11_UART1 || LPC11_UART2 || LPC11_UART3 + default n + ---help--- + Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.). + If this is not defined, then the terminal settings (baud, parity, etc). + are not configurable at runtime; serial streams cannot be flushed, etc.. + +endmenu + +menu "ADC driver options" + depends on LPC11_ADC + +config ADC0_AVERAGE + int "ADC0 average" + default 200 + +config ADC0_MASK + int "ADC0 mask" + default 1 + +config ADC0_SPS + int "ADC0 SPS" + default 1000 + +config ADC_CHANLIST + bool "Use ADC channel list" + default n + ---help--- + The errata that states: "A/D Global Data register should not be used + with burst mode or hardware triggering". If this option is selected, + then the ADC driver will grab from the individual channel registers + rather than from the global data register as this is the stated + workaround in the errata. + + The ADC interrupt will trigger on conversion complete on the last + channel listed in the array g_adc_chanlist[] (as opposed to + triggering interrupt from the global DONE flag). + + If this option is enabled, then the platform specific code must do + two things: (1) define ADC_NCHANNELS in the configuration file and + (2) provide an array g_adc_chanlist[] with the channel numbers + matching the ADC0_MASK within the board-specific library. + +config ADC_BURSTMODE + bool "One interrupt at the end of all ADC cconversions" + default n + ---help--- + Select this if you want to generate only one interrupt once all selected channels has been converted by the ADC + +config ADC_NCHANNELS + int "ADC0 number of channels" + depends on ADC_CHANLIST + default 0 + ---help--- + If ADC_CHANLIST is enabled, then the platform specific code + must do two things: (1) define ADC_NCHANNELS in the configuration + file and (2) provide an array g_adc_chanlist[] with the channel + numbers matching the ADC0_MASK within the board-specific library. + +endmenu + +menu "CAN driver options" + depends on LPC11_CAN1 || LPC11_CAN2 + +config CAN_EXTID + bool "CAN extended IDs" + default n + ---help--- + Enables support for the 29-bit extended ID. Default Standard 11-bit IDs. + +config CAN1_BAUD + int "CAN1 BAUD" + depends on LPC11_CAN1 + ---help--- + CAN1 BAUD rate. Required if LPC11_CAN1 is defined. + +config CAN2_BAUD + int "CAN2 BAUD" + depends on LPC11_CAN2 + ---help--- + CAN2 BAUD rate. Required if LPC11_CAN2 is defined. + +config CAN1_DIVISOR + int "CAN1 CCLK divisor" + depends on LPC11_CAN1 + default 4 + ---help--- + CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided + by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. + +config CAN2_DIVISOR + int "CAN2 CCLK divisor" + depends on LPC11_CAN2 + default 4 + ---help--- + CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided + by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4. + +config CAN_TSEG1 + int "TSEG1 quanta" + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config CAN_TSEG2 + int "TSEG2 quanta" + default 4 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config CAN_SAM + bool "CAN sampling" + default n + ---help--- + The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line). + +config CAN_LOOPBACK + bool "CAN looopback mode" + default n + ---help--- + Enable CAN loopback mode + +config CAN_REGDEBUG + bool "Register level debug" + depends on DEBUG + default n + ---help--- + Output detailed register-level CAN debug information. Requires also DEBUG and DEBUG_CAN. + +endmenu + +config GPIO_IRQ + bool "GPIO interrupt support" + default n + ---help--- + Enable support for GPIO interrupts + +menu "I2C driver options" + depends on LPC11_I2C0 || LPC11_I2C1 || LPC11_I2C2 + +config I2C0_FREQ + int "I2C0 frequency" + depends on LPC11_I2C0 + default 100000 + +config I2C1_FREQ + int "I2C1 frequency" + depends on LPC11_I2C1 + default 100000 + +config I2C2_FREQ + int "I2C2 frequency" + depends on LPC11_I2C2 + default 100000 + +endmenu diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs new file mode 100644 index 00000000000..1998d92dc77 --- /dev/null +++ b/arch/arm/src/lpc11xx/Make.defs @@ -0,0 +1,103 @@ +############################################################################ +# arch/arm/src/lpc11xx/Make.defs +# +# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = + +CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S +CMN_ASRCS += up_switchcontext.S vfork.S + +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c +CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c +CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c +CMN_CSRCS += up_puts.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c +CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c +CMN_CSRCS += up_systemreset.c up_unblocktask.c up_usestack.c up_doirq.c +CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_ELF),y) +CMN_CSRCS += up_elf.c +endif + +ifeq ($(CONFIG_DEBUG),y) +CMN_CSRCS += up_dumpnvic.c +endif + +CHIP_ASRCS = +CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c +CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_serial.c lpc11_spi.c +CHIP_CSRCS += lpc11_ssp.c lpc11_start.c + +# Configuration-dependent LPC11xx files + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += lpc11_timerisr.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += lpc11_userspace.c +endif + +ifeq ($(CONFIG_GPIO_IRQ),y) +CHIP_CSRCS += lpc11_gpioint.c +endif + +ifeq ($(CONFIG_ARCH_IRQPRIO),y) +CHIP_CSRCS += lpc11_irqprio.c +endif + +ifeq ($(CONFIG_LPC11_SPI0),y) +CHIP_CSRCS += lpc11_spi.c +else +ifeq ($(CONFIG_LPC11_SPI1),y) +CHIP_CSRCS += lpc11_spi.c +endif +endif + +ifeq ($(CONFIG_PWM),y) +CHIP_CSRCS += lpc11_pwm.c +endif diff --git a/arch/arm/src/lpc11xx/chip.h b/arch/arm/src/lpc11xx/chip.h new file mode 100644 index 00000000000..5057045b71f --- /dev/null +++ b/arch/arm/src/lpc11xx/chip.h @@ -0,0 +1,74 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip.h + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/* Include the memory map file. Other chip hardware files should then include + * this file for the proper setup. + */ + +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_iocon.h b/arch/arm/src/lpc11xx/chip/lpc111x_iocon.h new file mode 100644 index 00000000000..1e22bc1ce75 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc111x_iocon.h @@ -0,0 +1,219 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc111x_iocon.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Rommel Marcelo + * Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define IOCON_NPINS 12 + +/* Register offsets *****************************************************************/ + +/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */ +/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */ + +/* Register addresses ***************************************************************/ + +#define LPC11_IOCON_P0_0 (LPC11_IOCON_BASE + 0x00C) +#define LPC11_IOCON_P0_1 (LPC11_IOCON_BASE + 0x010) +#define LPC11_IOCON_P0_2 (LPC11_IOCON_BASE + 0x01C) +#define LPC11_IOCON_P0_3 (LPC11_IOCON_BASE + 0x02C) +#define LPC11_IOCON_P0_4 (LPC11_IOCON_BASE + 0x030) +#define LPC11_IOCON_P0_5 (LPC11_IOCON_BASE + 0x034) +#define LPC11_IOCON_P0_6 (LPC11_IOCON_BASE + 0x04C) +#define LPC11_IOCON_P0_7 (LPC11_IOCON_BASE + 0x050) +#define LPC11_IOCON_P0_8 (LPC11_IOCON_BASE + 0x060) +#define LPC11_IOCON_P0_9 (LPC11_IOCON_BASE + 0x064) +#define LPC11_IOCON_P0_10 (LPC11_IOCON_BASE + 0x068) +#define LPC11_IOCON_P0_11 (LPC11_IOCON_BASE + 0x074) + +#define LPC11_IOCON_P1_0 (LPC11_IOCON_BASE + 0x078) +#define LPC11_IOCON_P1_1 (LPC11_IOCON_BASE + 0x07c) +#define LPC11_IOCON_P1_2 (LPC11_IOCON_BASE + 0x080) +#define LPC11_IOCON_P1_3 (LPC11_IOCON_BASE + 0x090) +#define LPC11_IOCON_P1_4 (LPC11_IOCON_BASE + 0x094) +#define LPC11_IOCON_P1_5 (LPC11_IOCON_BASE + 0x0a0) +#define LPC11_IOCON_P1_6 (LPC11_IOCON_BASE + 0x0a4) +#define LPC11_IOCON_P1_7 (LPC11_IOCON_BASE + 0x0a8) +#define LPC11_IOCON_P1_8 (LPC11_IOCON_BASE + 0x014) +#define LPC11_IOCON_P1_9 (LPC11_IOCON_BASE + 0x038) +#define LPC11_IOCON_P1_10 (LPC11_IOCON_BASE + 0x06c) +#define LPC11_IOCON_P1_11 (LPC11_IOCON_BASE + 0x098) + +#define LPC11_IOCON_P2_0 (LPC11_IOCON_BASE + 0x008) +#define LPC11_IOCON_P2_1 (LPC11_IOCON_BASE + 0x028) +#define LPC11_IOCON_P2_2 (LPC11_IOCON_BASE + 0x05c) +#define LPC11_IOCON_P2_3 (LPC11_IOCON_BASE + 0x08c) +#define LPC11_IOCON_P2_4 (LPC11_IOCON_BASE + 0x040) +#define LPC11_IOCON_P2_5 (LPC11_IOCON_BASE + 0x044) +#define LPC11_IOCON_P2_6 (LPC11_IOCON_BASE + 0x000) +#define LPC11_IOCON_P2_7 (LPC11_IOCON_BASE + 0x020) +#define LPC11_IOCON_P2_8 (LPC11_IOCON_BASE + 0x024) +#define LPC11_IOCON_P2_9 (LPC11_IOCON_BASE + 0x054) +#define LPC11_IOCON_P2_10 (LPC11_IOCON_BASE + 0x058) +#define LPC11_IOCON_P2_11 (LPC11_IOCON_BASE + 0x070) + +#define LPC11_IOCON_P3_0 (LPC11_IOCON_BASE + 0x084) +#define LPC11_IOCON_P3_1 (LPC11_IOCON_BASE + 0x088) +#define LPC11_IOCON_P3_2 (LPC11_IOCON_BASE + 0x09C) +#define LPC11_IOCON_P3_3 (LPC11_IOCON_BASE + 0x0ac) +#define LPC11_IOCON_P3_4 (LPC11_IOCON_BASE + 0x03c) +#define LPC11_IOCON_P3_5 (LPC11_IOCON_BASE + 0x048) + +#define LPC11_IOCON_SCK_LOC (LPC11_IOCON_BASE + 0x0b0) +#define LPC11_IOCON_DSR_LOC (LPC11_IOCON_BASE + 0x0b4) +#define LPC11_IOCON_DCD_LOC (LPC11_IOCON_BASE + 0x0b8) +#define LPC11_IOCON_RI_LOC (LPC11_IOCON_BASE + 0x0bc) + +/* Register bit definitions *********************************************************/ +/* IOCON pin function select */ + +#define IOCON_FUNC_GPIO (0) +#define IOCON_FUNC_ALT1 (1) +#define IOCON_FUNC_ALT2 (2) +#define IOCON_FUNC_ALT3 (3) +#define IOCON_FUNC_ALT4 (4) +#define IOCON_FUNC_ALT5 (5) +#define IOCON_FUNC_ALT6 (6) +#define IOCON_FUNC_ALT7 (7) + +#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */ +#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT) +#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */ +#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT ) +#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */ +#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT) + /* Bit 6-9: Reserved */ +#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */ +#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) + /* Bit 11-31: Reserved */ + +/* Pin modes */ + +#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ +#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */ +#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */ +#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */ + +/* Pin types */ + +#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */ +#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */ +#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */ +#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */ +#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */ + +/* Analog/Digital mode */ + +#define IOCON_ADMODE_SHIFT (7) +#define IOCON_ADMODE_ANALOG (0 << IOCON_ADMODE_SHIFT) +#define IOCON_ADMODE_DIGITAL (1 << IOCON_ADMODE_SHIFT) + +/* I2C modes */ + +#define IOCON_I2CMODE_SHIFT (8) +#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT) +# define IOCON_I2CMODE_STANDARD (0 << IOCON_I2CMODE_SHIFT) +# define IOCON_I2CMODE_STANDIO (1 << IOCON_I2CMODE_SHIFT) +# define IOCON_I2CMODE_FASTPLUS (2 << IOCON_I2CMODE_SHIFT) + /*(3 << IOCON_I2CMODE_SHIFT) Reserved */ + /* Bits 10-31: Reserved */ + +/* SCK location register */ + +#define IOCON_SCK_LOC_SHIFT (0) +#define IOCON_SCK_LOC_MASK (3 << IOCON_SCK_LOC_SHIFT) +# define IOCON_SCK_LOC_SWCLK (0 << IOCON_SCK_LOC_SHIFT) +# define IOCON_SCK_LOC_PIO2_11 (1 << IOCON_SCK_LOC_SHIFT) +# define IOCON_SCK_LOC_PIO0_6 (2 << IOCON_SCK_LOC_SHIFT) + /*(3 << IOCON_SCK_LOC_SHIFT) Reserved */ + /* Bits 2-31: Reserved */ + +/* DSR location register */ + +#define IOCON_DSR_LOC_SHIFT (0) +#define IOCON_DSR_LOC_MASK (3 << IOCON_DSR_LOC_SHIFT) +# define IOCON_DSR_LOC_PIO2_1 (0 << IOCON_DSR_LOC_SHIFT) +# define IOCON_DSR_LOC_PIO3_1 (1 << IOCON_DSR_LOC_SHIFT) + /*(2 << IOCON_DSR_LOC_SHIFT) Reserved */ + /*(3 << IOCON_DSR_LOC_SHIFT) Reserved */ + /* Bits 2-31: Reserved */ + +/* DCD location register */ + +#define IOCON_DCD_LOC_SHIFT (0) +#define IOCON_DCD_LOC_MASK (3 << IOCON_DCD_LOC_SHIFT) +# define IOCON_DCD_LOC_PIO2_2 (0 << IOCON_DCD_LOC_SHIFT) +# define IOCON_DCD_LOC_PIO3_2 (1 << IOCON_DCD_LOC_SHIFT) + /*(2 << IOCON_DCD_LOC_SHIFT) Reserved */ + /*(3 << IOCON_DCD_LOC_SHIFT) Reserved */ + /* Bits 2-31: Reserved */ + +/* RI location register */ + +#define IOCON_RI_LOC_SHIFT (0) +#define IOCON_RI_LOC_MASK (3 << IOCON_RI_LOC_SHIFT) +# define IOCON_RI_LOC_PIO2_3 (0 << IOCON_RI_LOC_SHIFT) +# define IOCON_RI_LOC_PIO3_3 (1 << IOCON_RI_LOC_SHIFT) + /*(2 << IOCON_RI_LOC_SHIFT) Reserved */ + /*(3 << IOCON_RI_LOC_SHIFT) Reserved */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC118X_IOCON_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h b/arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h new file mode 100644 index 00000000000..21c12d01b03 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h @@ -0,0 +1,107 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc111x_memorymap.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define LPC11_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC11_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=16Kb) */ +#define LPC11_ROM_BASE 0x1fff0000 /* -0x1fffffff: 16Kb Boot ROM with flash services */ +#define LPC11_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ +#define LPC11_GPIO_BASE 0x50000000 /* -0x2009ffff: GPIO at AHB Peripherals */ +#define LPC11_APB_BASE 0x40000000 /* -0x4007ffff: APB Peripherals */ +#define LPC11_AHB_BASE 0x50000000 /* -0x501fffff: AHB Peripherals */ +#define LPC11_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC11_SCS_BASE 0xe000e000 +#define LPC11_DEBUGMCU_BASE 0xe0042000 + +/* APB Peripherals *****************************************************************/ + +#define LPC11_I2C0_BASE 0x40000000 /* -0x40003fff: I2C-bus */ +#define LPC11_WDT_BASE 0x40004000 /* -0x40007fff: Watchdog timer */ +#define LPC11_UART0_BASE 0x40008000 /* -0x4000bfff: UART 0 */ +#define LPC11_TMR0_BASE 0x4000c000 /* -0x4000ffff: Timer 0 */ +#define LPC11_TMR1_BASE 0x40010000 /* -0x40013fff: Timer 1 */ +#define LPC11_TMR2_BASE 0x40014000 /* -0x40017fff: Timer 0 */ +#define LPC11_TMR3_BASE 0x40018000 /* -0x4001bfff: Timer 1 */ +#define LPC11_ADC_BASE 0x4001c000 /* -0x4001ffff: ADC */ + /* -0x40037fff: Reserved */ +#define LPC11_PMU_BASE 0x40038000 /* -0x4003bfff: PMU */ + /* -0x40017fff: Reserved */ +#define LPC11_FLASHC_BASE 0x4003c000 /* -0x4003ffff: Flash Controller */ +#define LPC11_SPI0_BASE 0x40040000 /* -0x40043fff: SPI0 */ +#define LPC11_IOCON_BASE 0x40044000 /* -0x40047fff: IOCONFIG */ +#define LPC11_SYSCON_BASE 0x40048000 /* -0x4004bfff: System Control */ + /* -0x4004ffff: Reserved */ +#define LPC11_CAN0_BASE 0x40050000 /* -0x40053fff: CAN0 */ + /* -0x40057ffff: Reserved */ +#define LPC11_SPI1_BASE 0x40058000 /* -0x4005bffff: SPI1 */ + /* -0x4007fffff: Reserved */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC11_GPIO_PIO0 (LPC11_GPIO_BASE + 0) /* -0x5000ffff: GPIO PIO0 */ +#define LPC11_GPIO_PIO1 (LPC11_GPIO_BASE + 0x10000) /* -0x5001ffff: GPIO PIO1 */ +#define LPC11_GPIO_PIO2 (LPC11_GPIO_BASE + 0x20000) /* -0x5002ffff: GPIO PIO1 */ +#define LPC11_GPIO_PIO3 (LPC11_GPIO_BASE + 0x30000) /* -0x5003ffff: GPIO PIO1 */ + /* -0x501fffff: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC116X_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h b/arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h new file mode 100644 index 00000000000..8bf4e667ab7 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h @@ -0,0 +1,122 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* GPIO pin definitions *************************************************************/ +/* NOTE that functions have a alternate pins that can be selected. These alternates + * are identified with a numeric suffix like _1, _2, or _3. Your board.h file + * should select the correct alternative for your board by including definitions + * such as: + * + * #define GPIO_UART1_RXD GPIO_UART1_RXD_1 + * + * (without the suffix) + */ + +#ifdef CONFIG_ARCH_CHIP_LPC1115 + +#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_CT32B0_MAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_SPI0_SSEL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_CT16B0_CAP0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_I2C_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_I2C_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_SPI0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_UART0_CTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_SPI0_MISO (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_CT16B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SPI0_MOSI (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_CT16B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_JTAG_SWCLK (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_PIO0_10 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_SPI0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_CT16B0_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_PIO0_11 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_AD_inp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_CT32B0_MAT3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_PIO1_0 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_AD_inp1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_CT32B1_CAP0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_PIO1_1 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_AD_inp2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_CT32B1_MAT0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_PIO1_2 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_AD_inp3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_CT32B1_MAT1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_JTAG_SWDIO (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_PIO1_3 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_AD_inp4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_CT32B1_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_AD_inp5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CT32B1_MAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_UART0_RTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CT32B0_CAP0 (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_CT32B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_CT32B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_CT16B1_CAP0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_CT16B1_MAT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_AD_inp6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CT16B1_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_AD_inp7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_UART0_DTR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0) + +#endif /* CONFIG_ARCH_CHIP_LPC1115 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC116X_PINCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_adc.h b/arch/arm/src/lpc11xx/chip/lpc11_adc.h new file mode 100644 index 00000000000..1324bff6c22 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_adc.h @@ -0,0 +1,171 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_adc.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_ADC_CR_OFFSET 0x0000 /* A/D Control Register */ +#define LPC11_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */ +#define LPC11_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */ + +#define LPC11_ADC_DR_OFFSET(n) (0x0010+((n) << 2)) +#define LPC11_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */ +#define LPC11_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */ +#define LPC11_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */ +#define LPC11_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */ +#define LPC11_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */ +#define LPC11_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */ +#define LPC11_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */ +#define LPC11_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */ + +#define LPC11_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */ + +/* Register addresses ***************************************************************/ + +#define LPC11_ADC_CR (LPC11_ADC_BASE+LPC11_ADC_CR_OFFSET) +#define LPC11_ADC_GDR (LPC11_ADC_BASE+LPC11_ADC_GDR_OFFSET) +#define LPC11_ADC_INTEN (LPC11_ADC_BASE+LPC11_ADC_INTEN_OFFSET) + +#define LPC11_ADC_DR(n) (LPC11_ADC_BASE+LPC11_ADC_DR_OFFSET(n)) +#define LPC11_ADC_DR0 (LPC11_ADC_BASE+LPC11_ADC_DR0_OFFSET) +#define LPC11_ADC_DR1 (LPC11_ADC_BASE+LPC11_ADC_DR1_OFFSET) +#define LPC11_ADC_DR2 (LPC11_ADC_BASE+LPC11_ADC_DR2_OFFSET) +#define LPC11_ADC_DR3 (LPC11_ADC_BASE+LPC11_ADC_DR3_OFFSET) +#define LPC11_ADC_DR4 (LPC11_ADC_BASE+LPC11_ADC_DR4_OFFSET) +#define LPC11_ADC_DR5 (LPC11_ADC_BASE+LPC11_ADC_DR5_OFFSET) +#define LPC11_ADC_DR6 (LPC11_ADC_BASE+LPC11_ADC_DR6_OFFSET) +#define LPC11_ADC_DR7 (LPC11_ADC_BASE+LPC11_ADC_DR7_OFFSET) + +#define LPC11_ADC_STAT (LPC11_ADC_BASE+LPC11_ADC_STAT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* A/D Control Register */ + +#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */ +#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK) +#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */ +#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT) +#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */ +#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Clocks used on burst mode conv. */ +#define ADC_CR_CLKS_MASK (3 << ADC_CR_CLKS_SHIFT) + /* Bits 20-23: Reserved */ +#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */ +#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT) +# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */ +# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */ +# define ADC_CR_START_P0p2 (2 << ADC_CR_START_SHIFT) /* Start edge on P0.2/SSEL/CT16B0_CAP0 */ +# define ADC_CR_START_P1p5 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.5/DIR/CT32B0_CAP0 */ +# define ADC_CR_START_CT32B0MAT0 (4 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT0 */ +# define ADC_CR_START_CT32B0MAT1 (5 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT1 */ +# define ADC_CR_START_CT16B0MAT0 (6 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT0 */ +# define ADC_CR_START_CT16B0MAT1 (7 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT1 */ +#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */ + /* Bits 28-31: Reserved */ +/* A/D Global Data Register AND Channel 0-7 Data Register */ + /* Bits 0-5: Reserved */ +#define ADC_DR_RESULT_SHIFT (5) /* Bits 6-15: Result of conversion (DONE==1) */ +#define ADC_DR_RESULT_MASK (0x3ff << ADC_DR_RESULT_SHIFT) + /* Bits 16-23: Reserved */ +#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */ +#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT) + /* Bits 27-29: Reserved */ +#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/ +#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/ + +/* A/D Interrupt Enable Register */ + +#define ADC_INTEN_CHAN(n) (1 << (n)) +#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */ +#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */ +#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */ +#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */ +#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */ +#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */ +#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */ +#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */ +#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */ + /* Bits 9-31: Reserved */ +/* A/D Status Register */ + +#define ADC_STAT_DONE(n) (1 << (n)) +#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */ +#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */ +#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */ +#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */ +#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */ +#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */ +#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */ +#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */ +#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8) +#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */ +#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */ +#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */ +#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */ +#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */ +#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */ +#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */ +#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */ +#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */ + /* Bits 17-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_gpio.h b/arch/arm/src/lpc11xx/chip/lpc11_gpio.h new file mode 100644 index 00000000000..99daa2445f7 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_gpio.h @@ -0,0 +1,146 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_gpio.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* GPIO block register offsets ******************************************************/ + +#define LPC11_GPIO0_OFFSET 0x00000 +#define LPC11_GPIO1_OFFSET 0x10000 +#define LPC11_GPIO2_OFFSET 0x20000 +#define LPC11_GPIO3_OFFSET 0x30000 +#define LPC11_GPIO_OFFSET(n) (0x10000*(n)) + +#define LPC11_GPIO_DATA_OFFSET 0x3FFC +#define LPC11_GPIO_DIR_OFFSET 0x8000 /* GPIO Port Direction control */ +#define LPC11_GPIO_IS_OFFSET 0x8004 /* Interrupt Sense register */ +#define LPC11_GPIO_IBE_OFFSET 0x8008 /* Interrupt Both Edges register */ +#define LPC11_GPIO_IEV_OFFSET 0x800c /* Interrupt Event register */ +#define LPC11_GPIO_IE_OFFSET 0x8010 /* Interrupt Mask register */ +#define LPC11_GPIO_RIS_OFFSET 0x8014 /* Raw interrupt status register */ +#define LPC11_GPIO_MIS_OFFSET 0x8018 /* Masked interrupt status register */ +#define LPC11_GPIO_IC_OFFSET 0x801c /* Interrupt clear register */ + +/* Register addresses ***************************************************************/ +/* GPIO block register addresses ****************************************************/ + +#define LPC11_GPIOn_BASE(n) (LPC11_GPIO_BASE+LPC11_GPIO_OFFSET(n)) +#define LPC11_GPIO0_BASE (LPC11_GPIO_BASE+LPC11_GPIO0_OFFSET) +#define LPC11_GPIO1_BASE (LPC11_GPIO_BASE+LPC11_GPIO1_OFFSET) +#define LPC11_GPIO2_BASE (LPC11_GPIO_BASE+LPC11_GPIO2_OFFSET) +#define LPC11_GPIO3_BASE (LPC11_GPIO_BASE+LPC11_GPIO3_OFFSET) + +#define LPC11_GPIO_DIR(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_DIR_OFFSET) /* GPIO Port Direction register */ +#define LPC11_GPIO_IS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IS_OFFSET) /* GPIO Interrupt Sense register */ +#define LPC11_GPIO_IBE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IBE_OFFSET) /* GPIO Interrupt Both Edges sense register */ +#define LPC11_GPIO_IEV(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IVE_OFFSET) /* GPIO Interrupt Event register */ +#define LPC11_GPIO_IE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IE_OFFSET) /* GPIO Interrupt Mask register */ +#define LPC11_GPIO_RIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_RIS_OFFSET) /* GPIO Raw Interrupt Status register */ +#define LPC11_GPIO_MIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_MIS_OFFSET) /* GPIO Masked Interrupt Status register */ +#define LPC11_GPIO_IC(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IC_OFFSET) /* GPIO Interrupt Clear register */ + +#define LPC11_GPIO0_DATA (LPC11_GPIO0_BASE+LPC11_GPIO_DATA_OFFSET) +#define LPC11_GPIO0_DIR (LPC11_GPIO0_BASE+LPC11_GPIO_DIR_OFFSET) +#define LPC11_GPIO0_IS (LPC11_GPIO0_BASE+LPC11_GPIO_IS_OFFSET) +#define LPC11_GPIO0_IBE (LPC11_GPIO0_BASE+LPC11_GPIO_IBE_OFFSET) +#define LPC11_GPIO0_IEV (LPC11_GPIO0_BASE+LPC11_GPIO_IVE_OFFSET) +#define LPC11_GPIO0_IE (LPC11_GPIO0_BASE+LPC11_GPIO_IE_OFFSET) +#define LPC11_GPIO0_RIS (LPC11_GPIO0_BASE+LPC11_GPIO_RIS_OFFSET) +#define LPC11_GPIO0_MIS (LPC11_GPIO0_BASE+LPC11_GPIO_MIS_OFFSET) +#define LPC11_GPIO0_IC (LPC11_GPIO0_BASE+LPC11_GPIO_IC_OFFSET) + +#define LPC11_GPIO1_DATA (LPC11_GPIO1_BASE+LPC11_GPIO_DATA_OFFSET) +#define LPC11_GPIO1_DIR (LPC11_GPIO1_BASE+LPC11_GPIO_DIR_OFFSET) +#define LPC11_GPIO1_IS (LPC11_GPIO1_BASE+LPC11_GPIO_IS_OFFSET) +#define LPC11_GPIO1_IBE (LPC11_GPIO1_BASE+LPC11_GPIO_IBE_OFFSET) +#define LPC11_GPIO1_IEV (LPC11_GPIO1_BASE+LPC11_GPIO_IVE_OFFSET) +#define LPC11_GPIO1_IE (LPC11_GPIO1_BASE+LPC11_GPIO_IE_OFFSET) +#define LPC11_GPIO1_RIS (LPC11_GPIO1_BASE+LPC11_GPIO_RIS_OFFSET) +#define LPC11_GPIO1_MIS (LPC11_GPIO1_BASE+LPC11_GPIO_MIS_OFFSET) +#define LPC11_GPIO1_IC (LPC11_GPIO1_BASE+LPC11_GPIO_IC_OFFSET) + +#define LPC11_GPIO2_DATA (LPC11_GPIO2_BASE+LPC11_GPIO_DATA_OFFSET) +#define LPC11_GPIO2_DIR (LPC11_GPIO2_BASE+LPC11_GPIO_DIR_OFFSET) +#define LPC11_GPIO2_IS (LPC11_GPIO2_BASE+LPC11_GPIO_IS_OFFSET) +#define LPC11_GPIO2_IBE (LPC11_GPIO2_BASE+LPC11_GPIO_IBE_OFFSET) +#define LPC11_GPIO2_IEV (LPC11_GPIO2_BASE+LPC11_GPIO_IVE_OFFSET) +#define LPC11_GPIO2_IE (LPC11_GPIO2_BASE+LPC11_GPIO_IE_OFFSET) +#define LPC11_GPIO2_RIS (LPC11_GPIO2_BASE+LPC11_GPIO_RIS_OFFSET) +#define LPC11_GPIO2_MIS (LPC11_GPIO2_BASE+LPC11_GPIO_MIS_OFFSET) +#define LPC11_GPIO2_IC (LPC11_GPIO2_BASE+LPC11_GPIO_IC_OFFSET) + +#define LPC11_GPIO3_DATA (LPC11_GPIO3_BASE+LPC11_GPIO_DATA_OFFSET) +#define LPC11_GPIO3_DIR (LPC11_GPIO3_BASE+LPC11_GPIO_DIR_OFFSET) +#define LPC11_GPIO3_IS (LPC11_GPIO3_BASE+LPC11_GPIO_IS_OFFSET) +#define LPC11_GPIO3_IBE (LPC11_GPIO3_BASE+LPC11_GPIO_IBE_OFFSET) +#define LPC11_GPIO3_IEV (LPC11_GPIO3_BASE+LPC11_GPIO_IVE_OFFSET) +#define LPC11_GPIO3_IE (LPC11_GPIO3_BASE+LPC11_GPIO_IE_OFFSET) +#define LPC11_GPIO3_RIS (LPC11_GPIO3_BASE+LPC11_GPIO_RIS_OFFSET) +#define LPC11_GPIO3_MIS (LPC11_GPIO3_BASE+LPC11_GPIO_MIS_OFFSET) +#define LPC11_GPIO3_IC (LPC11_GPIO3_BASE+LPC11_GPIO_IC_OFFSET) + +/* Register bit definitions *********************************************************/ +/* GPIO block register bit definitions **********************************************/ + +#define GPIO(n) (1 << (n)) /* n=0,1,..11 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_i2c.h b/arch/arm/src/lpc11xx/chip/lpc11_i2c.h new file mode 100644 index 00000000000..53c7089c6ee --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_i2c.h @@ -0,0 +1,208 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_i2c.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC11_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC11_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC11_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC11_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC11_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC11_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC11_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC11_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC11_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC11_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC11_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC11_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC11_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC11_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC11_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC11_I2C0_CONSET (LPC11_I2C0_BASE+LPC11_I2C_CONSET_OFFSET) +#define LPC11_I2C0_STAT (LPC11_I2C0_BASE+LPC11_I2C_STAT_OFFSET) +#define LPC11_I2C0_DAT (LPC11_I2C0_BASE+LPC11_I2C_DAT_OFFSET) +#define LPC11_I2C0_ADR0 (LPC11_I2C0_BASE+LPC11_I2C_ADR0_OFFSET) +#define LPC11_I2C0_SCLH (LPC11_I2C0_BASE+LPC11_I2C_SCLH_OFFSET) +#define LPC11_I2C0_SCLL (LPC11_I2C0_BASE+LPC11_I2C_SCLL_OFFSET) +#define LPC11_I2C0_CONCLR (LPC11_I2C0_BASE+LPC11_I2C_CONCLR_OFFSET) +#define LPC11_I2C0_MMCTRL (LPC11_I2C0_BASE+LPC11_I2C_MMCTRL_OFFSET) +#define LPC11_I2C0_ADR1 (LPC11_I2C0_BASE+LPC11_I2C_ADR1_OFFSET) +#define LPC11_I2C0_ADR2 (LPC11_I2C0_BASE+LPC11_I2C_ADR2_OFFSET) +#define LPC11_I2C0_ADR3 (LPC11_I2C0_BASE+LPC11_I2C_ADR3_OFFSET) +#define LPC11_I2C0_BUFR (LPC11_I2C0_BASE+LPC11_I2C_BUFR_OFFSET) +#define LPC11_I2C0_MASK0 (LPC11_I2C0_BASE+LPC11_I2C_MASK0_OFFSET) +#define LPC11_I2C0_MASK1 (LPC11_I2C0_BASE+LPC11_I2C_MASK1_OFFSET) +#define LPC11_I2C0_MASK2 (LPC11_I2C0_BASE+LPC11_I2C_MASK2_OFFSET) +#define LPC11_I2C0_MASK3 (LPC11_I2C0_BASE+LPC11_I2C_MASK3_OFFSET) + +#define LPC11_I2C1_CONSET (LPC11_I2C1_BASE+LPC11_I2C_CONSET_OFFSET) +#define LPC11_I2C1_STAT (LPC11_I2C1_BASE+LPC11_I2C_STAT_OFFSET) +#define LPC11_I2C1_DAT (LPC11_I2C1_BASE+LPC11_I2C_DAT_OFFSET) +#define LPC11_I2C1_ADR0 (LPC11_I2C1_BASE+LPC11_I2C_ADR0_OFFSET) +#define LPC11_I2C1_SCLH (LPC11_I2C1_BASE+LPC11_I2C_SCLH_OFFSET) +#define LPC11_I2C1_SCLL (LPC11_I2C1_BASE+LPC11_I2C_SCLL_OFFSET) +#define LPC11_I2C1_CONCLR (LPC11_I2C1_BASE+LPC11_I2C_CONCLR_OFFSET) +#define LPC11_I2C1_MMCTRL (LPC11_I2C1_BASE+LPC11_I2C_MMCTRL_OFFSET) +#define LPC11_I2C1_ADR1 (LPC11_I2C1_BASE+LPC11_I2C_ADR1_OFFSET) +#define LPC11_I2C1_ADR2 (LPC11_I2C1_BASE+LPC11_I2C_ADR2_OFFSET) +#define LPC11_I2C1_ADR3 (LPC11_I2C1_BASE+LPC11_I2C_ADR3_OFFSET) +#define LPC11_I2C1_BUFR (LPC11_I2C1_BASE+LPC11_I2C_BUFR_OFFSET) +#define LPC11_I2C1_MASK0 (LPC11_I2C1_BASE+LPC11_I2C_MASK0_OFFSET) +#define LPC11_I2C1_MASK1 (LPC11_I2C1_BASE+LPC11_I2C_MASK1_OFFSET) +#define LPC11_I2C1_MASK2 (LPC11_I2C1_BASE+LPC11_I2C_MASK2_OFFSET) +#define LPC11_I2C1_MASK3 (LPC11_I2C1_BASE+LPC11_I2C_MASK3_OFFSET) + +#define LPC11_I2C2_CONSET (LPC11_I2C2_BASE+LPC11_I2C_CONSET_OFFSET) +#define LPC11_I2C2_STAT (LPC11_I2C2_BASE+LPC11_I2C_STAT_OFFSET) +#define LPC11_I2C2_DAT (LPC11_I2C2_BASE+LPC11_I2C_DAT_OFFSET) +#define LPC11_I2C2_ADR0 (LPC11_I2C2_BASE+LPC11_I2C_ADR0_OFFSET) +#define LPC11_I2C2_SCLH (LPC11_I2C2_BASE+LPC11_I2C_SCLH_OFFSET) +#define LPC11_I2C2_SCLL (LPC11_I2C2_BASE+LPC11_I2C_SCLL_OFFSET) +#define LPC11_I2C2_CONCLR (LPC11_I2C2_BASE+LPC11_I2C_CONCLR_OFFSET) +#define LPC11_I2C2_MMCTRL (LPC11_I2C2_BASE+LPC11_I2C_MMCTRL_OFFSET) +#define LPC11_I2C2_ADR1 (LPC11_I2C2_BASE+LPC11_I2C_ADR1_OFFSET) +#define LPC11_I2C2_ADR2 (LPC11_I2C2_BASE+LPC11_I2C_ADR2_OFFSET) +#define LPC11_I2C2_ADR3 (LPC11_I2C2_BASE+LPC11_I2C_ADR3_OFFSET) +#define LPC11_I2C2_BUFR (LPC11_I2C2_BASE+LPC11_I2C_BUFR_OFFSET) +#define LPC11_I2C2_MASK0 (LPC11_I2C2_BASE+LPC11_I2C_MASK0_OFFSET) +#define LPC11_I2C2_MASK1 (LPC11_I2C2_BASE+LPC11_I2C_MASK1_OFFSET) +#define LPC11_I2C2_MASK2 (LPC11_I2C2_BASE+LPC11_I2C_MASK2_OFFSET) +#define LPC11_I2C2_MASK3 (LPC11_I2C2_BASE+LPC11_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 399-402 in the "LPC11xx User Manual" (UM10398), Rev. 01, 4 January + * 2010, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-1 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_memorymap.h b/arch/arm/src/lpc11xx/chip/lpc11_memorymap.h new file mode 100644 index 00000000000..302de1a17e0 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_memorymap.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_memorymap.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* This file is only a thin shell that includes the correct memory map definitions + * for the selected LPC11xx family. + */ + +#include + +#if defined(LPC111x) +# include "chip/lpc111x_memorymap.h" +#else +# error "Unrecognized LPC11xx family" +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h b/arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h new file mode 100644 index 00000000000..cae57481f0e --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* This file is only a thin shell that includes the correct pin configuration + * definitions for the selected LPC11xx family. + */ + +#include + +#if defined(LPC111x) +# include "chip/lpc111x_pinconfig.h" +#else +# error "Unrecognized LPC11xx family" +#endif + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + + #endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_pmu.h b/arch/arm/src/lpc11xx/chip/lpc11_pmu.h new file mode 100644 index 00000000000..6a8b5a6865e --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_pmu.h @@ -0,0 +1,106 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_pmu.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_PMU_PCON_OFFSET 0x0000 /* Power control register */ +#define LPC11_PMU_GPREG0 0x0004 /* General purpose register 0 */ +#define LPC11_PMU_GPREG1 0x0008 /* General purpose register 1 */ +#define LPC11_PMU_GPREG2 0x000C /* General purpose register 2 */ +#define LPC11_PMU_GPREG3 0x0010 /* General purpose register 3 */ +#define LPC11_PMU_GPREG4 0x0014 /* General purpose register 0 */ + +/* Register addresses ***************************************************************/ + +#define LPC11_PMU_PCON (LPC11_PMU_BASE+LPC11_PMU_PCON_OFFSET) +#define LPC11_PMU_GPREG0 (LPC11_PMU_BASE+LPC11_PMU_GPREG0) +#define LPC11_PMU_GPREG1 (LPC11_PMU_BASE+LPC11_PMU_GPREG1) +#define LPC11_PMU_GPREG2 (LPC11_PMU_BASE+LPC11_PMU_GPREG2) +#define LPC11_PMU_GPREG3 (LPC11_PMU_BASE+LPC11_PMU_GPREG3) +#define LPC11_PMU_GPREG4 (LPC11_PMU_BASE+LPC11_PMU_GPREG4) + +/* Register bit definitions *********************************************************/ + +/* Power control register */ + /* Bit 0: Reserved. Do not write 1 to this bit */ +#define PMU_PCON_DPDEN (1 << 1) /* Deep power-down mode enable */ + /* Bits 2-7: Reserved. Do not write ones to this bit */ +#define PMU_PCON_SLEEPFLAG (1 << 8) /* Sleep mode flag */ + /* Bits 9-10: Reserved. Do not write ones to this bit */ +#define PMU_PCON_DPDFLAG (1 << 11) /* Deep power-down flag. */ + /* Bits 12-31: Reserved. Do not write ones to this bit */ + + +/* General Purpose REG */ + +#define PMU_GPREG03_GPDATA_MASK (0xffffffff) /* Bits 0-31: Data retained during Deep power-down mode */ + + +/* General Purpose REG4 Register */ + + /* Bits 0-9: Reserved. Do not write ones to this bit */ +#define PMU_GPREG4_WAKEUPHYS (1 << 10) /* WAKEUP pin hysteresis enable */ +#define PMU_GPREG4_GPDATA_SHIFT 11 /* Data retained during Deep power-down mode. */ +#define PMU_GPREG4_GPDATA_MASK (0x1fffff << PMU_GPREG4_GPDATA_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_ssp.h b/arch/arm/src/lpc11xx/chip/lpc11_ssp.h new file mode 100644 index 00000000000..1c67102c044 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_ssp.h @@ -0,0 +1,182 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_ssp.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */ +#define LPC11_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */ +#define LPC11_SSP_DR_OFFSET 0x0008 /* Data Register */ +#define LPC11_SSP_SR_OFFSET 0x000c /* Status Register */ +#define LPC11_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */ +#define LPC11_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set/Clear Register */ +#define LPC11_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */ +#define LPC11_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */ +#define LPC11_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */ + +/* Register addresses ***************************************************************/ +/* SPI 0 */ +#define LPC11_SSP0_CR0 (LPC11_SPI0_BASE+LPC11_SSP_CR0_OFFSET) +#define LPC11_SSP0_CR1 (LPC11_SPI0_BASE+LPC11_SSP_CR1_OFFSET) +#define LPC11_SSP0_DR (LPC11_SPI0_BASE+LPC11_SSP_DR_OFFSET) +#define LPC11_SSP0_SR (LPC11_SPI0_BASE+LPC11_SSP_SR_OFFSET) +#define LPC11_SSP0_CPSR (LPC11_SPI0_BASE+LPC11_SSP_CPSR_OFFSET) +#define LPC11_SSP0_IMSC (LPC11_SPI0_BASE+LPC11_SSP_IMSC_OFFSET) +#define LPC11_SSP0_RIS (LPC11_SPI0_BASE+LPC11_SSP_RIS_OFFSET) +#define LPC11_SSP0_MIS (LPC11_SPI0_BASE+LPC11_SSP_MIS_OFFSET) +#define LPC11_SSP0_ICR (LPC11_SPI0_BASE+LPC11_SSP_ICR_OFFSET) + +/* SPI 1 */ +#define LPC11_SSP1_CR0 (LPC11_SPI1_BASE+LPC11_SSP_CR0_OFFSET) +#define LPC11_SSP1_CR1 (LPC11_SPI1_BASE+LPC11_SSP_CR1_OFFSET) +#define LPC11_SSP1_DR (LPC11_SPI1_BASE+LPC11_SSP_DR_OFFSET) +#define LPC11_SSP1_SR (LPC11_SPI1_BASE+LPC11_SSP_SR_OFFSET) +#define LPC11_SSP1_CPSR (LPC11_SPI1_BASE+LPC11_SSP_CPSR_OFFSET) +#define LPC11_SSP1_IMSC (LPC11_SPI1_BASE+LPC11_SSP_IMSC_OFFSET) +#define LPC11_SSP1_RIS (LPC11_SPI1_BASE+LPC11_SSP_RIS_OFFSET) +#define LPC11_SSP1_MIS (LPC11_SPI1_BASE+LPC11_SSP_MIS_OFFSET) +#define LPC11_SSP1_ICR (LPC11_SPI1_BASE+LPC11_SSP_ICR_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* SPI/SSP Control Register 0 */ + +#define SSP_CR0_DSS_SHIFT (0) /* Data Size Select */ +#define SSP_CR0_DSS_MASK (15 << SSP_CR0_SHIFT) +# define SSP_CR0_DSS_4BITS (3 << SSP_CR0_DSS_SHIFT) /* 4 bits per transfer */ +# define SSP_CR0_DSS_5BITS (4 << SSP_CR0_DSS_SHIFT) /* 5 bits per transfer */ +# define SSP_CR0_DSS_6BITS (5 << SSP_CR0_DSS_SHIFT) /* 6 bits per transfer */ +# define SSP_CR0_DSS_7BITS (6 << SSP_CR0_DSS_SHIFT) /* 7 bits per transfer */ +# define SSP_CR0_DSS_8BITS (7 << SSP_CR0_DSS_SHIFT) /* 8 bits per transfer */ +# define SSP_CR0_DSS_9BITS (8 << SSP_CR0_DSS_SHIFT) /* 9 bits per transfer */ +# define SSP_CR0_DSS_10BITS (9 << SSP_CR0_DSS_SHIFT) /* 10 bits per transfer */ +# define SSP_CR0_DSS_11BITS (10 << SSP_CR0_DSS_SHIFT) /* 11 bits per transfer */ +# define SSP_CR0_DSS_12BITS (11 << SSP_CR0_DSS_SHIFT) /* 12 bits per transfer */ +# define SSP_CR0_DSS_13BITS (12 << SSP_CR0_DSS_SHIFT) /* 13 bits per transfer */ +# define SSP_CR0_DSS_14BITS (13 << SSP_CR0_DSS_SHIFT) /* 14 bits per transfer */ +# define SSP_CR0_DSS_15BITS (14 << SSP_CR0_DSS_SHIFT) /* 15 bits per transfer */ +# define SSP_CR0_DSS_16BITS (15 << SSP_CR0_DSS_SHIFT) /* 16 bits per transfer */ +#define SSP_CR0_FRF_SHIFT (4) /* Frame Format */ +#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT) +# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) /* SPI Frame Format */ +# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) /* TI Frame Format */ +# define SSP_CR0_FRF_MWIRE (2 << SSP_CR0_FRF_SHIFT) /* Microwire Frame Format */ + /* (3 << SSP_CR0_FRF_SHIFT) format is not supported */ +#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock polarity control */ +#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock phase control */ +#define SSP_CR0_SCR_SHIFT (8) /* Bit 8-15: Serial Clock Rate. PCLK/(CPSDVSR x [SCR + 1] */ +#define SSP_CR0_SCR_MASK (255 << SSP_CR0_SCR_SHIFT) + +/* SPI/SSP Control Register 1 */ + +#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */ +#define SSP_CR1_SSE (1 << 1) /* Bit 1: SPI Enable */ +#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */ +#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */ + /* Bits 4-31: Reserved */ + +/* SPI/SSP Data Register */ + +#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */ + /* Bits 16-31: Reserved */ +/* SPI/SSP Status Register */ + +#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */ +#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */ +#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */ +#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */ +#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */ + /* Bits 5-31: Reserved */ +/* SPI/SSP Clock Prescale Register */ + +#define SSP_CPSR_DVSR_MASK (0xff) /* Even values between 2 and 254 */ + +/* SPI/SSP Interrupt Mask Set/Clear Register */ + +#define SSP_IMSC_RORIM (1 << 0) /* Bit 0: Enable Receive Overrun Interrupt */ +#define SSP_IMSC_RTIM (1 << 1) /* Bit 1: Enable Receive Timeout Interrupt */ +#define SSP_IMSC_RXIM (1 << 2) /* Bit 2: Enable Rx FIFO half full Interrupt */ +#define SSP_IMSC_TXIM (1 << 3) /* Bit 3: Enable Tx FIFO halt empty */ + /* Bits 4-31: Reserved */ + +/* SPI/SSP Raw Interrupt Status */ + +#define SSP_RIS_RORIS (1 << 0) /* Bit 0: An Overrun event occurred */ +#define SSP_RIS_RTRIS (1 << 1) /* Bit 1: Rx FIFO has data and MCU didn't read it */ +#define SSP_RIS_RXRIS (1 << 2) /* Bit 2: The Rx FIFO is at least half full */ +#define SSP_RIS_TXRIS (1 << 3) /* Bit 3: Tx FIFO is at least halt empty */ + /* Bits 4-31: Reserved */ + +/* SPI/SSP Masked Interrupt Status Register */ + +#define SSP_MIS_RORMIS (1 << 0) /* Bit 0: An Overrun occurred and this interrupt is enabled */ +#define SSP_MIS_RTMIS (1 << 1) /* Bit 1: An Rx FIFO timeout happened and this int is enabled */ +#define SSP_MIS_RXMIS (1 << 2) /* Bit 2: Rx FIFO is at least half empty and this int is enabled */ +#define SSP_MIS_TXMIS (1 << 3) /* Bit 3: Tx FIFO is at least halt full and this int is enabled */ + /* Bits 4-31: Reserved */ +/* SPI/SSP Interrupt Clear Register */ + +#define SSP_ICR_RORIC (1 << 0) /* Bit 0: Clear Rx FIFO Overrun Interrupt */ +#define SSP_ICR_RTIC (1 << 1) /* Bit 1: Clear Rx FIFO read timeout Interrupt */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SPI_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_syscon.h b/arch/arm/src/lpc11xx/chip/lpc11_syscon.h new file mode 100644 index 00000000000..3709135feb6 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_syscon.h @@ -0,0 +1,449 @@ +/******************************************************************************************** + * arch/arm/src/lpc11xx/chip/lpc11_syscon.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ + +#define LPC11_SYSCON_SYSMEMREMAP_OFFSET 0x0000 /* System memory remap */ +#define LPC11_SYSCON_PRESETCTRL_OFFSET 0x0004 /* Pefipheral reset control */ +#define LPC11_SYSCON_SYSPLLCTRL_OFFSET 0x0008 /* System PLL control */ +#define LPC11_SYSCON_SYSPLLSTAT_OFFSET 0x000C /* System PLL status */ + /* 0x010 - 0x01c: Reserved */ + +#define LPC11_SYSCON_SYSOSCCTRL_OFFSET 0x0020 /* System oscillator control */ +#define LPC11_SYSCON_WDTOSCCTRL_OFFSET 0x0024 /* Watchdog oscillator control */ +#define LPC11_SYSCON_IRCCTRL_OFFSET 0x0028 /* IRC control */ + /* 0x02c: Reserved */ + +#define LPC11_SYSCON_SYSRSTSTAT_OFFSET 0x0030 /* System reset status register */ + /* 0x034 - 0x03c: Reserved */ + +#define LPC11_SYSCON_SYSPLLCLKSEL_OFFSET 0x0040 /* System PLL clock source select */ +#define LPC11_SYSCON_SYSPLLCLKUEN_OFFSET 0x0044 /* System PLL clock source update enable */ + /* 0x048 - 0x06c: Reserved */ + +#define LPC11_SYSCON_MAINCLKSEL_OFFSET 0x0070 /* Main clock source select */ +#define LPC11_SYSCON_MAINCLKUEN_OFFSET 0x0074 /* Main clock source update enable */ +#define LPC11_SYSCON_SYSAHBCLKDIV_OFFSET 0x0078 /* System AHB clock divider */ + /* 0x07c: Reserved */ + +#define LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET 0x0080 /* System AHB clock control */ + /* 0x084 - 0x090: Reserved */ + +#define LPC11_SYSCON_SSP0CLKDIV_OFFSET 0x0094 /* SPI0 clock divider */ +#define LPC11_SYSCON_UARTCLKDIV_OFFSET 0x0098 /* UART clock divider */ +#define LPC11_SYSCON_SSP1CLKDIV_OFFSET 0x009c /* SPI1 clock divider */ + /* 0x0a0 - 0x0cc: Reserved */ + +#define LPC11_SYSCON_WDTCLKSEL_OFFSET 0x00d0 /* WDT clock source select */ +#define LPC11_SYSCON_WDTCLKUEN_OFFSET 0x00d4 /* WDT clock source update enable */ +#define LPC11_SYSCON_WDTCLKDIV_OFFSET 0x00d8 /* WDT clock divider */ + /* 0x0dc: Reserved */ + +#define LPC11_SYSCON_CLKOUTCLKSEL_OFFSET 0x00e0 /* CLKOUT clock source select */ +#define LPC11_SYSCON_CLKOUTUEN_OFFSET 0x00e4 /* CLKOUT clock source update enable */ +#define LPC11_SYSCON_CLKOUTCLKDIV_OFFSET 0x00e8 /* CLKOUT clock divider */ + /* 0x0ec - 0x0fc: Reserved */ + +#define LPC11_SYSCON_PIOPORCAP0_OFFSET 0x0100 /* POR captured PIO status 0 */ +#define LPC11_SYSCON_PIOPORCAP1_OFFSET 0x0104 /* POR captured PIO status 1 */ + /* 0x108 - 0x14c: Reserved */ + +#define LPC11_SYSCON_BODCTRL_OFFSET 0x0150 /* BOD control */ +#define LPC11_SYSCON_SYSTCKCAL_OFFSET 0x0154 /* System tick counter calibration */ + /* 0x158 - 0x16c: Reserved */ + +#define LPC11_SYSCON_IRQLATENCY_OFFSET 0x0170 /* IRQ delay */ +#define LPC11_SYSCON_NMISRC_OFFSET 0x0174 /* NMI source selection */ + /* 0x178 - 0x1fc: Reserved */ + +#define LPC11_SYSCON_STARTAPRP0_OFFSET 0x0200 /* Start logic edge control register 0 */ +#define LPC11_SYSCON_STARTERP0_OFFSET 0x0204 /* Start logic signal enable register 0 */ +#define LPC11_SYSCON_STARTRSRP0CLR_OFFSET 0x0208 /* Start logic reset register 0 */ +#define LPC11_SYSCON_STARTSRP0_OFFSET 0x020c /* Start logic status register 0 */ + /* 0x210 - 0x22c: Reserved */ + +#define LPC11_SYSCON_PDSLEEPCFG_OFFSET 0x0230 /* Power-down states in Deep-sleep mode */ +#define LPC11_SYSCON_PDAWAKECFG_OFFSET 0x0234 /* Power-down states after wake-up from Deep-sleep mode */ +#define LPC11_SYSCON_PDRUNCFG_OFFSET 0x0238 /* Power-down configuration register */ + /* 0x023c - 0x3f0: Reserved */ +#define LPC11_SYSCON_DEVICE_ID_OFFSET 0x03f4 /* Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L */ + + +/* Register addresses ***********************************************************************/ + +#define LPC11_SYSCON_SYSMEMREMAP (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSMEMREMAP_OFFSET) + +#define LPC11_SYSCON_PRESETCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_PRESETCTRL_OFFSET) +#define LPC11_SYSCON_SYSPLLCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCTRL_OFFSET) +#define LPC11_SYSCON_SYSPLLSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLSTAT_OFFSET) + +#define LPC11_SYSCON_SYSOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSOSCCTRL_OFFSET) +#define LPC11_SYSCON_WDTOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTOSCCTRL_OFFSET) +#define LPC11_SYSCON_IRCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_IRCCTRL_OFFSET) + +#define LPC11_SYSCON_SYSRSTSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSRSTSTAT_OFFSET) + +#define LPC11_SYSCON_SYSPLLCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKSEL_OFFSET) +#define LPC11_SYSCON_SYSPLLCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKUEN_OFFSET) + +#define LPC11_SYSCON_MAINCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKSEL_OFFSET) +#define LPC11_SYSCON_MAINCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKUEN_OFFSET) + +#define LPC11_SYSCON_SYSAHBCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKDIV_OFFSET) +#define LPC11_SYSCON_SYSAHBCLKCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET) + +#define LPC11_SYSCON_SSP0CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP0CLKDIV_OFFSET) +#define LPC11_SYSCON_UARTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_UARTCLKDIV_OFFSET) +#define LPC11_SYSCON_SSP1CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP1CLKDIV_OFFSET) + +#define LPC11_SYSCON_WDTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKSEL_OFFSET) +#define LPC11_SYSCON_WDTCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKUEN_OFFSET) +#define LPC11_SYSCON_WDTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKDIV_OFFSET) + +#define LPC11_SYSCON_CLKOUTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKSEL_OFFSET) +#define LPC11_SYSCON_CLKOUTUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTUEN_OFFSET_OFFSET) +#define LPC11_SYSCON_CLKOUTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKDIV_OFFSET) + +#define LPC11_SYSCON_PIOPORCAP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP0_OFFSET) +#define LPC11_SYSCON_PIOPORCAP1 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP1_OFFSET) + +#define LPC11_SYSCON_BODCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_BODCTRL_OFFSET) +#define LPC11_SYSCON_SYSTCKCAL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSTCKCAL_OFFSET) + +#define LPC11_SYSCON_IRQLATENCY (LPC11_SYSCON_BASE + LPC11_SYSCON_IRQLATENCY_OFFSET) +#define LPC11_SYSCON_NMISRC (LPC11_SYSCON_BASE + LPC11_SYSCON_NMISRC_OFFSET) + +#define LPC11_SYSCON_STARTAPRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTAPRP0_OFFSET) +#define LPC11_SYSCON_STARTERP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTERP0_OFFSET) +#define LPC11_SYSCON_STARTRSRP0CLR (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTRSRP0CLR_OFFSET) +#define LPC11_SYSCON_STARTSRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTSRP0_OFFSET) + +#define LPC11_SYSCON_PDSLEEPCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDSLEEPCFG_OFFSET) +#define LPC11_SYSCON_PDAWAKECFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDAWAKECFG_OFFSET) +#define LPC11_SYSCON_PDRUNCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDRUNCFG_OFFSET) + +#define LPC11_SYSCON_DEVICE_ID (LPC11_SYSCON_BASE + LPC11_SYSCON_DEVICE_ID_OFFSET) + +/* Register bit definitions *****************************************************************/ + +#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0) /* Bits 0-1: System memory remap register */ +#define SYSCON_SYSMEMREMAP_MAP_MASK (3 << SYSCON_SYSMEMREMAP_MAP_SHIFT) +# define SYSCON_SYSMEMREMAP_MAP_BOOTLOADER (0 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Boot ROM */ +# define SYSCON_SYSMEMREMAP_MAP_RAM (1 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Static RAM */ +# define SYSCON_SYSMEMREMAP_MAP_FLASH (2 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are keeped in flash */ + /* Bits 2-31: Reserved */ + +#define SYSCON_PRESETCTRL_SSP0_RST_N (1 << 0) /* SPI0 reset control */ +#define SYSCON_PRESETCTRL_I2C_RST_N (1 << 1) /* I2C reset control */ +#define SYSCON_PRESETCTRL_SSP1_RST_N (1 << 2) /* SPI1 reset control */ +#define SYSCON_PRESETCTRL_CAN_RST_N (1 << 3) /* C_CAN reset control */ + /* Bits 4-31: Reserved */ + +#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0) /* Bits 0-4: Feedback divider value. */ +#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1f << SYSCON_SYSPLLCTRL_MSEL_SHIFT) +# define SYSCON_SYSPLLCTRL_MSEL_DIV(n) ((n-1) << SYSCON_SYSPLLCTRL_MSEL_SHIFT) /* n=1,2,3,..32 */ +#define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5) /* Bits 5-6: Post divider ratio P. The division ratio is 2 x P */ +#define SYSCON_SYSPLLCTRL_PSEL_MASK (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) +# define SYSCON_SYSPLLCTRL_PSEL_DIV1 (0 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) +# define SYSCON_SYSPLLCTRL_PSEL_DIV2 (1 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) +# define SYSCON_SYSPLLCTRL_PSEL_DIV4 (2 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) +# define SYSCON_SYSPLLCTRL_PSEL_DIV8 (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT) + /* Bits 7-31: Reserved */ + +#define SYSCON_SYSPLLSTAT_LOCK (1 << 0) /* PLL lock status. 0 = PLL not locked, 1 = PLL locked */ + /* Bits 1-31: Reserved */ + +#define SYSCON_SYSOSCCTRL_BYPASS (1 << 0) /* Bypass system oscillator */ +#define SYSCON_SYSOSCCTRL_FREQRANGE (1 << 1) /* Determines freq. range for low-power oscillator */ + /* Bits 2-31: Reserved */ +#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0) /* Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana/(2x(1+DIVSEL)) */ +#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1f << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) +# define SYSCON_WDTOSCCTRL_DIVSEL(n) (((n-2)/2) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) /* n = 2,4,8,..64 */ +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5) /* Bits 5-8: Select watchdog oscillator analog output frequency */ +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) +# define SYSCON_WDTOSCCTRL_FREQSEL_0p6Mhz (1 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 0.6 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p05Mhz (2 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.05 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p4Mhz (3 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p75Mhz (4 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.75 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p1Mhz (5 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.1 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p4Mhz (6 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p7Mhz (7 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.7 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3Mhz (8 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.0 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3p25Mhz (9 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.25 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3p5Mhz (10 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.5 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3p75Mhz (11 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.75 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_4Mhz (12 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_4p2Mhz (13 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.2 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_4p4Mhz (14 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_4p6Mhz (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.6 MHz */ + /* Bits 9-31: Reserved */ + +#define SYSCON_IRCCTRL_TRIM_MASK (0xff) /* Bits 0-7: Trim value used to adjust on-chip 12 MHz oscillator */ + /* Bits 8-31: Reserved */ + +#define SYSCON_SYSRSTSTAT_POR (1 << 0) /* POR reset status */ +#define SYSCON_SYSRSTSTAT_EXTRST (1 << 1) /* Status of the external /RESET pin */ +#define SYSCON_SYSRSTSTAT_WDT (1 << 2) /* Status of the Watchdog reset */ +#define SYSCON_SYSRSTSTAT_BOD (1 << 3) /* Status of Brown-out detect reset */ +#define SYSCON_SYSRSTSTAT_SYSRST (1 << 4) /* Status of the software system reset */ + /* Bits 5-31: Reserved */ + +#define SYSCON_SYSPLLCLKSEL_SHIFT (0) /* Bits 0-1: System PLL clock source */ +#define SYSCON_SYSPLLCLKSEL_MASK (3 << SYSCON_SYSPLLCLKSEL_SHIFT) +# define SYSCON_SYSPLLCLKSEL_IRCOSC (0 << SYSCON_SYSPLLCLKSEL_SHIFT) +# define SYSCON_SYSPLLCLKSEL_SYSOSC (1 << SYSCON_SYSPLLCLKSEL_SHIFT) + /* Bits 2-31: Reserved */ + +#define SYSCON_SYSPLLCLKUEN_ENA (1 << 0) /* Bit 0: Enable system PLL clock source update */ + /* Bits 1-31: Reserved */ + +#define SYSCON_MAINCLKSEL_SHIFT (0) /* Bits 0-1: Clock source for main clock */ +#define SYSCON_MAINCLKSEL_MASK (3 << SYSCON_MAINCLKSEL_SHIFT) +# define SYSCON_MAINCLKSEL_IRCOSC (0 << SYSCON_MAINCLKSEL_SHIFT) /* IRC oscillator */ +# define SYSCON_MAINCLKSEL_PLLOSC (1 << SYSCON_MAINCLKSEL_SHIFT) /* Input clock to system PLL */ +# define SYSCON_MAINCLKSEL_WDTOSC (2 << SYSCON_MAINCLKSEL_SHIFT) /* WDT oscillator */ +# define SYSCON_MAINCLKSEL_SYSPLLCLKOUT (3 << SYSCON_MAINCLKSEL_SHIFT) /* System PLL clock out */ + /* Bits 2-31: Reserved */ + +#define SYSCON_MAINCLKUEN_ENA (1 << 0) /* Bit 0: Enable main clock source update */ + /* Bits 1-31: Reserved */ + +#define SYSCON_SYSAHBCLKDIV_SHIFT (0) /* Bits 0-7: 0=System clock disabled, 1=Divide by 1 ... 255 = Divide by 255 */ +#define SYSCON_SYSAHBCLKDIV_MASK (0xff << SYSCON_SYSAHBCLKDIV_SHIFT) + /* Bits 8-31: Reserved */ +//# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */ + +#define SYSCON_SYSAHBCLKCTRL_SYS (1 << 0) /* Bit 0: Enables clock for AHB to APB bridge */ +#define SYSCON_SYSAHBCLKCTRL_ROM (1 << 1) /* Bit 1: Enables clock for ROM */ +#define SYSCON_SYSAHBCLKCTRL_RAM (1 << 2) /* Bit 2: Enables clock for RAM */ +#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3) /* Bit 3: Enables clock for flash register interface */ +#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1 << 4) /* Bit 4: Enables clock for flash array access */ +#define SYSCON_SYSAHBCLKCTRL_I2C (1 << 5) /* Bit 5: Enables clock for I2C */ +#define SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6) /* Bit 6: Enables clock for GPIO */ +#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1 << 7) /* Bit 7: Enables clock for 16-bit counter/timer 0 */ +#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1 << 8) /* Bit 8: Enables clock for 16-bit counter/timer 1 */ +#define SYSCON_SYSAHBCLKCTRL_CT32B0 (1 << 9) /* Bit 9: Enables clock for 32-bit counter/timer 0 */ +#define SYSCON_SYSAHBCLKCTRL_CT32B1 (1 << 10) /* Bit 10: Enables clock for 32-bit counter/timer 1 */ +#define SYSCON_SYSAHBCLKCTRL_SSP0 (1 << 11) /* Bit 11: Enables clock for SPI0 */ +#define SYSCON_SYSAHBCLKCTRL_UART (1 << 12) /* Bit 12: Enables clock for UART */ +#define SYSCON_SYSAHBCLKCTRL_ADC (1 << 13) /* Bit 13: Enables clock for ADC */ + /* Bit 14: Reserved */ +#define SYSCON_SYSAHBCLKCTRL_WDT (1 << 15) /* Bit 15: Enables clock for WDT */ +#define SYSCON_SYSAHBCLKCTRL_IOCON (1 << 16) /* Bit 16: Enables clock for I/O configuration block */ +#define SYSCON_SYSAHBCLKCTRL_CAN (1 << 17) /* Bit 17: Enables clock for C_CAN */ +#define SYSCON_SYSAHBCLKCTRL_SSP1 (1 << 18) /* Bit 18: Enables clock for SPI1 */ + /* Bits 19-31: Reserved */ + +#define SYSCON_SSP0CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI0_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ + /* Bits 8-31: Reserved */ + +#define SYSCON_UARTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable UART_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ + /* Bits 8-31: Reserved */ + +#define SYSCON_SSP1CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI1_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */ + /* Bits 8-31: Reserved */ + +#define SYSCON_WDTCLKSEL_SHIFT (0) /* Bits 0-1: WDT clock source */ +#define SYSCON_WDTCLKSEL_MASK (3 << SYSCON_WDTCLKSEL_SHIFT) +# define SYSCON_WDTCLKSEL_IRCOSC (0 << SYSCON_WDTCLKSEL_SHIFT) /* IRC oscillator */ +# define SYSCON_WDTCLKSEL_MAINCLK (1 << SYSCON_WDTCLKSEL_SHIFT) /* Main clock */ +# define SYSCON_WDTCLKSEL_WDTOSC (2 << SYSCON_WDTCLKSEL_SHIFT) /* Watchdog oscillator */ + /* Bits 2-31: reserved */ + +#define SYSCON_WDTCLKUEN_ENA (1 << 0) /* Bit 0: Enable WDT clock source update */ + /* Bits 1-31: Reserved */ + +#define SYSCON_WDTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable WDCLK, 1=Divide by 1 ... 255 = Divide by 255 */ + /* Bits 8-31: Reserved */ + +#define SYSCON_CLKOUTCLKSEL_SHIFT (0) /* Bits 0-1: CLKOUT clock source */ +#define SYSCON_CLKOUTCLKSEL_MASK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) +# define SYSCON_CLKOUTCLKSEL_IRCOSC (0 << SYSCON_CLKOUTCLKSEL_SHIFT) /* IRC oscillator */ +# define SYSCON_CLKOUTCLKSEL_SYSOSC (1 << SYSCON_CLKOUTCLKSEL_SHIFT) /* System oscillator */ +# define SYSCON_CLKOUTCLKSEL_WDTOSC (2 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Watchdog oscillator */ +# define SYSCON_CLKOUTCLKSEL_MAINCLK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Main clock */ + /* Bits 2-31: Reserved */ + +#define SYSCON_CLKOUTUEN_ENA (1 << 0) /* Bit 0: Enable CLKOUT clock source update */ + /* Bits 1-31: Reserved */ + +#define SYSCON_CLKOUTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable CLKOUT, 1=Divide by 1 ... 255 = Divide by 255 */ + /* Bits 1-31: Reserved */ + +#define SYSCON_PIOPORCAP0_CAPPIO0_SHIFT (0) /* Bits 0-11: Raw reset stats input PIO0_n: PIO0_11 to PIO0_0 */ +#define SYSCON_PIOPORCAP0_CAPPIO0_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) +# define SYSCON_PIOPORCAP0_CAPPIO0_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) /* n = 0 to 11 */ + +#define SYSCON_PIOPORCAP0_CAPPIO1_SHIFT (12) /* Bits 12-23: Raw reset stats input PIO0_n: PIO1_11 to PIO1_0 */ +#define SYSCON_PIOPORCAP0_CAPPIO1_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) +# define SYSCON_PIOPORCAP0_CAPPIO1_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) /* n = 0 to 11 */ + +#define SYSCON_PIOPORCAP0_CAPPIO2_SHIFT (24) /* Bits 24-31: Raw reset stats input PIO0_n: PIO2_11 to PIO2_0 */ +#define SYSCON_PIOPORCAP0_CAPPIO2_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) +# define SYSCON_PIOPORCAP0_CAPPIO2_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) /* n = 0 to 11 */ + + +#define SYSCON_PIOPORCAP1_CAPPIO2_8 (1 << 0) /* Bit 0: Raw reset status input PIO2_8 */ +#define SYSCON_PIOPORCAP1_CAPPIO2_9 (1 << 1) /* Bit 1: Raw reset status input PIO2_9 */ +#define SYSCON_PIOPORCAP1_CAPPIO2_10 (1 << 2) /* Bit 2: Raw reset status input PIO2_10 */ +#define SYSCON_PIOPORCAP1_CAPPIO2_11 (1 << 3) /* Bit 3: Raw reset status input PIO2_11 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_0 (1 << 4) /* Bit 4: Raw reset status input PIO3_0 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_1 (1 << 5) /* Bit 5: Raw reset status input PIO3_1 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_2 (1 << 6) /* Bit 6: Raw reset status input PIO3_2 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_3 (1 << 7) /* Bit 7: Raw reset status input PIO3_3 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_4 (1 << 8) /* Bit 8: Raw reset status input PIO3_4 */ +#define SYSCON_PIOPORCAP1_CAPPIO3_5 (1 << 9) /* Bit 9: Raw reset status input PIO3_5 */ + /* Bits 10-31: Reserved */ + +#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0) /* Bits 0-1: BOD reset level */ +#define SYSCON_BODCTRL_BODRSTLEV_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) +# define SYSCON_BODCTRL_BODRSTLEV_LEVEL0 (0 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 0: assert 1.46V, de-assert 1.63V */ +# define SYSCON_BODCTRL_BODRSTLEV_LEVEL1 (1 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 1: assert 2.06V, de-assert 2.15V */ +# define SYSCON_BODCTRL_BODRSTLEV_LEVEL2 (2 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 2: assert 2.35V, de-assert 2.43V */ +# define SYSCON_BODCTRL_BODRSTLEV_LEVEL3 (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 3: assert 2.63V, de-assert 2.71V */ +#define SYSCON_BODCTRL_BODINTVAL_SHIFT (2) /* Bits 2-3: BOD interrupt level */ +#define SYSCON_BODCTRL_BODINTVAL_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_BODINTVAL_SHIFT) +# define SYSCON_BODCTRL_BODINTVAL_LEVEL0 (0 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 0: Reserved */ +# define SYSCON_BODCTRL_BODINTVAL_LEVEL1 (1 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 1: int. assert 2.22V,de-a. 2.35V */ +# define SYSCON_BODCTRL_BODINTVAL_LEVEL2 (2 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 2: int. assert 2.52V,de-a. 2.66V */ +# define SYSCON_BODCTRL_BODINTVAL_LEVEL3 (3 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 3: int. assert 2.80V,de-a. 2.90V */ +#define SYSCON_BODCTRL_BODRSTENA (1 << 4) /* BOD reset enable */ + /* Bits 5-31: Reserved */ + +#define SYSCON_SYSTCKCAL_CAL 0x3ffffff /* Bits 0-25: System tick timer calibration value */ + /* Bits 26-31: Reserved */ + +#define SYSCON_IRQLATENCY_LATENCY_MASK (0xff) /* Bits 0-7: 8-bit latency value */ + /* Bits 8-31: Reserved */ + +#define SYSCON_NMISRC_IRQNO_SHIFT (0) /* Bits 0-4: The IRQ number of interrupt that acts as NMI if bit 31 is 1 */ +#define SYSCON_NMISRC_IRQNO_MASK (31 << SYSCON_NMISRC_IRQNO_SHIFT) + /* Bits 5-30: Reserved */ +#define SYSCON_NMISRC_NMIEN (1 << 31) /* Write 1 to this bit to enable NMI source selected by bits 4:0 */ + +#define SYSCON_STARTAPRP0_APRPIO0_SHIFT (0) /* Bits 0-11: Edge select for start logic input PIO0_[0-11], 0=fall/1=rise */ +#define SYSCON_STARTAPRP0_APRPIO0_MASK (0xfff << SYSCON_STARTAPRP0_APRPIO0_SHIFT) +# define SYSCON_STARTAPRP0_APRPIO0_BIT(n) ((1 << n) << SYSCON_STARTAPRP0_APRPIO0_SHIFT) /* n = 0 to 11 */ +#define SYSCON_STARTAPRP0_APRPIO1_0 (1 << 12) /* Bit 12: Edge select start logic input PIO1_0, 0=falling/1=rising */ + /* Bits 13-31: Reserved */ + +#define SYSCON_STARTERP0_ERPIO0_SHIFT (0) /* Bits 0-11: Enable start signal for start logic input PIO0[0-11] */ +#define SYSCON_STARTERP0_ERPIO0_MASK (0xfff << SYSCON_STARTERP0_ERPIO0_SHIFT) +# define SYSCON_STARTERP0_ERPIO0_BIT(n) ((1 << n) << SYSCON_STARTERP0_ERPIO0_SHIFT) /* n = 0 to 11 */ +#define SYSCON_STARTERP0_ERPIO1_0 (1 << 12) /* Bit 12: Enable start signal for start logic input PIO1_0 */ + /* Bits 13-31: Reserved */ + +#define SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT (0) /* Bits 0-11: Start logic reset register 0 */ +#define SYSCON_STARTRSRP0CLR_RSRPIO0_MASK (0xfff << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) +# define SYSCON_STARTRSRP0CLR_RSRPIO0_BIT(n) ((1 << n) << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) /* n = 0 to 11 */ +#define SYSCON_STARTRSRP0CLR_RSRPIO1_0 (1 << 12) /* Bit 12: Start signal reset for start logic input PIO1_0 */ + /* Bits 13-31: Reserved */ + +#define SYSCON_STARTSRP0_SRPIO0_SHIFT (0) /* Bits 0-11: Start logic status register 0 */ +#define SYSCON_STARTSRP0_SRPIO0_MASK (0xfff << SYSCON_STARTSRP0_SRPIO0_SHIFT) +# define SYSCON_STARTSRP0_SRPIO0_BIT(n) ((1 << n) << SYSCON_STARTSRP0_SRPIO0_SHIFT) /* n = 0 to 11 */ +#define SYSCON_STARTSRP0_SRPIO1_0 (1 << 12) /* Bit 12: Start signal status for start logic input PIO1_0 */ + /* Bits 13-31: Reserved */ + + /* Bits 0-2: Reserved. NOTE: Always write these bits as 111 */ +#define SYSCON_PDSLEEPCFG_BOD_PD (1 << 3) /* BOD power-down control in Deep-sleep mode */ + /* Bits 4-5: Reserved. NOTE: Always write these bits as 11 */ +#define SYSCON_PDSLEEPCFG_WDTOSC_PD (1 << 6) /* Watchdog oscillator power control in Deep-sleep mode */ + /* Bit 7: Reserved. NOTE: Always write this bit as 1 */ + /* Bits 8-10: Reserved NOTE: Always write these bits as 000 */ + /* Bits 11-12: Reserved. NOTE: Always write these bits as 11 */ + /* Bits 13-31: Reserved */ + +#define SYSCON_PDAWAKECFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output wake-up configuration */ +#define SYSCON_PDAWAKECFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator wake-up configuration */ +#define SYSCON_PDAWAKECFG_FLASH_PD (1 << 2) /* Bit 2: Flash wake-up configuration */ +#define SYSCON_PDAWAKECFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection wake-up configuration */ +#define SYSCON_PDAWAKECFG_ADC_PD (1 << 4) /* Bit 4: ADC wake-up configuration */ +#define SYSCON_PDAWAKECFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator wake-up configuration */ +#define SYSCON_PDAWAKECFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator wake-up configuration */ +#define SYSCON_PDAWAKECFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL wake-up configuration */ + /* Bit 8: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 9: Reserved. NOTE: Always write this bit as 0 */ + /* Bit 10: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 11: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 12: Reserved. NOTE: Always write this bit as 0 */ + /* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */ + /* Bits 16-31: Reserved */ + +#define SYSCON_PDRUNCFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output power-down */ +#define SYSCON_PDRUNCFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator power-down */ +#define SYSCON_PDRUNCFG_FLASH_PD (1 << 2) /* Bit 2: Flash power-down */ +#define SYSCON_PDRUNCFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection power-down */ +#define SYSCON_PDRUNCFG_ADC_PD (1 << 4) /* Bit 4: ADC power-down */ +#define SYSCON_PDRUNCFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator power-down */ +#define SYSCON_PDRUNCFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator power-down */ +#define SYSCON_PDRUNCFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL power-down */ + /* Bit 8: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 9: Reserved. NOTE: Always write this bit as 0 */ + /* Bit 10: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 11: Reserved. NOTE: Always write this bit as 1 */ + /* Bit 12: Reserved. NOTE: Always write this bit as 0 */ + /* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */ + /* Bits 16-31: Reserved */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_timer.h b/arch/arm/src/lpc11xx/chip/lpc11_timer.h new file mode 100644 index 00000000000..28e1122323b --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_timer.h @@ -0,0 +1,271 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_timer.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC11_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC11_TMR_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC11_TMR_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC11_TMR_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC11_TMR_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC11_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC11_TMR_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC11_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC11_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC11_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC11_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC11_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC11_TMR_EMR_OFFSET 0x003c /* External Match Register */ +#define LPC11_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */ +#define LPC11_TMR_PWMC_OFFSET 0x0074 /* PWM Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC11_TMR16B0IR (LPC11_TMR16B0_BASE+LPC11_TMR_IR_OFFSET) +#define LPC11_TMR16B0TCR (LPC11_TMR16B0_BASE+LPC11_TMR_TCR_OFFSET) +#define LPC11_TMR16B0TC (LPC11_TMR16B0_BASE+LPC11_TMR_TC_OFFSET) +#define LPC11_TMR16B0PR (LPC11_TMR16B0_BASE+LPC11_TMR_PR_OFFSET) +#define LPC11_TMR16B0PC (LPC11_TMR16B0_BASE+LPC11_TMR_PC_OFFSET) +#define LPC11_TMR16B0MCR (LPC11_TMR16B0_BASE+LPC11_TMR_MCR_OFFSET) +#define LPC11_TMR16B0MR0 (LPC11_TMR16B0_BASE+LPC11_TMR_MR0_OFFSET) +#define LPC11_TMR16B0MR1 (LPC11_TMR16B0_BASE+LPC11_TMR_MR1_OFFSET) +#define LPC11_TMR16B0MR2 (LPC11_TMR16B0_BASE+LPC11_TMR_MR2_OFFSET) +#define LPC11_TMR16B0MR3 (LPC11_TMR16B0_BASE+LPC11_TMR_MR3_OFFSET) +#define LPC11_TMR16B0CCR (LPC11_TMR16B0_BASE+LPC11_TMR_CCR_OFFSET) +#define LPC11_TMR16B0CR0 (LPC11_TMR16B0_BASE+LPC11_TMR_CR0_OFFSET) +#define LPC11_TMR16B0CR1 (LPC11_TMR16B0_BASE+LPC11_TMR_CR1_OFFSET) +#define LPC11_TMR16B0EMR (LPC11_TMR16B0_BASE+LPC11_TMR_EMR_OFFSET) +#define LPC11_TMR16B0CTCR (LPC11_TMR16B0_BASE+LPC11_TMR_CTCR_OFFSET) +#define LPC11_TMR16B0PWMC (LPC11_TMR16B0_BASE+LPC11_TMR_PWMC_OFFSET) + +#define LPC11_TMR16B1IR (LPC11_TMR16B1_BASE+LPC11_TMR_IR_OFFSET) +#define LPC11_TMR16B1TCR (LPC11_TMR16B1_BASE+LPC11_TMR_TCR_OFFSET) +#define LPC11_TMR16B1TC (LPC11_TMR16B1_BASE+LPC11_TMR_TC_OFFSET) +#define LPC11_TMR16B1PR (LPC11_TMR16B1_BASE+LPC11_TMR_PR_OFFSET) +#define LPC11_TMR16B1PC (LPC11_TMR16B1_BASE+LPC11_TMR_PC_OFFSET) +#define LPC11_TMR16B1MCR (LPC11_TMR16B1_BASE+LPC11_TMR_MCR_OFFSET) +#define LPC11_TMR16B1MR0 (LPC11_TMR16B1_BASE+LPC11_TMR_MR0_OFFSET) +#define LPC11_TMR16B1MR1 (LPC11_TMR16B1_BASE+LPC11_TMR_MR1_OFFSET) +#define LPC11_TMR16B1MR2 (LPC11_TMR16B1_BASE+LPC11_TMR_MR2_OFFSET) +#define LPC11_TMR16B1MR3 (LPC11_TMR16B1_BASE+LPC11_TMR_MR3_OFFSET) +#define LPC11_TMR16B1CCR (LPC11_TMR16B1_BASE+LPC11_TMR_CCR_OFFSET) +#define LPC11_TMR16B1CR0 (LPC11_TMR16B1_BASE+LPC11_TMR_CR0_OFFSET) +#define LPC11_TMR16B1CR1 (LPC11_TMR16B1_BASE+LPC11_TMR_CR1_OFFSET) +#define LPC11_TMR16B1EMR (LPC11_TMR16B1_BASE+LPC11_TMR_EMR_OFFSET) +#define LPC11_TMR16B1CTCR (LPC11_TMR16B1_BASE+LPC11_TMR_CTCR_OFFSET) +#define LPC11_TMR16B1PWMC (LPC11_TMR16B1_BASE+LPC11_TMR_PWMC_OFFSET) + +#define LPC11_TMR32B0IR (LPC11_TMR32B0_BASE+LPC11_TMR_IR_OFFSET) +#define LPC11_TMR32B0TCR (LPC11_TMR32B0_BASE+LPC11_TMR_TCR_OFFSET) +#define LPC11_TMR32B0TC (LPC11_TMR32B0_BASE+LPC11_TMR_TC_OFFSET) +#define LPC11_TMR32B0PR (LPC11_TMR32B0_BASE+LPC11_TMR_PR_OFFSET) +#define LPC11_TMR32B0PC (LPC11_TMR32B0_BASE+LPC11_TMR_PC_OFFSET) +#define LPC11_TMR32B0MCR (LPC11_TMR32B0_BASE+LPC11_TMR_MCR_OFFSET) +#define LPC11_TMR32B0MR0 (LPC11_TMR32B0_BASE+LPC11_TMR_MR0_OFFSET) +#define LPC11_TMR32B0MR1 (LPC11_TMR32B0_BASE+LPC11_TMR_MR1_OFFSET) +#define LPC11_TMR32B0MR2 (LPC11_TMR32B0_BASE+LPC11_TMR_MR2_OFFSET) +#define LPC11_TMR32B0MR3 (LPC11_TMR32B0_BASE+LPC11_TMR_MR3_OFFSET) +#define LPC11_TMR32B0CCR (LPC11_TMR32B0_BASE+LPC11_TMR_CCR_OFFSET) +#define LPC11_TMR32B0CR0 (LPC11_TMR32B0_BASE+LPC11_TMR_CR0_OFFSET) +#define LPC11_TMR32B0CR1 (LPC11_TMR32B0_BASE+LPC11_TMR_CR1_OFFSET) +#define LPC11_TMR32B0EMR (LPC11_TMR32B0_BASE+LPC11_TMR_EMR_OFFSET) +#define LPC11_TMR32B0CTCR (LPC11_TMR32B0_BASE+LPC11_TMR_CTCR_OFFSET) +#define LPC11_TMR32B0PWMC (LPC11_TMR32B0_BASE+LPC11_TMR_PWMC_OFFSET) + +#define LPC11_TMR32B1IR (LPC11_TMR32B1_BASE+LPC11_TMR_IR_OFFSET) +#define LPC11_TMR32B1TCR (LPC11_TMR32B1_BASE+LPC11_TMR_TCR_OFFSET) +#define LPC11_TMR32B1TC (LPC11_TMR32B1_BASE+LPC11_TMR_TC_OFFSET) +#define LPC11_TMR32B1PR (LPC11_TMR32B1_BASE+LPC11_TMR_PR_OFFSET) +#define LPC11_TMR32B1PC (LPC11_TMR32B1_BASE+LPC11_TMR_PC_OFFSET) +#define LPC11_TMR32B1MCR (LPC11_TMR32B1_BASE+LPC11_TMR_MCR_OFFSET) +#define LPC11_TMR32B1MR0 (LPC11_TMR32B1_BASE+LPC11_TMR_MR0_OFFSET) +#define LPC11_TMR32B1MR1 (LPC11_TMR32B1_BASE+LPC11_TMR_MR1_OFFSET) +#define LPC11_TMR32B1MR2 (LPC11_TMR32B1_BASE+LPC11_TMR_MR2_OFFSET) +#define LPC11_TMR32B1MR3 (LPC11_TMR32B1_BASE+LPC11_TMR_MR3_OFFSET) +#define LPC11_TMR32B1CCR (LPC11_TMR32B1_BASE+LPC11_TMR_CCR_OFFSET) +#define LPC11_TMR32B1CR0 (LPC11_TMR32B1_BASE+LPC11_TMR_CR0_OFFSET) +#define LPC11_TMR32B1CR1 (LPC11_TMR32B1_BASE+LPC11_TMR_CR1_OFFSET) +#define LPC11_TMR32B1EMR (LPC11_TMR32B1_BASE+LPC11_TMR_EMR_OFFSET) +#define LPC11_TMR32B1CTCR (LPC11_TMR32B1_BASE+LPC11_TMR_CTCR_OFFSET) +#define LPC11_TMR32B1PWMC (LPC11_TMR32B1_BASE+LPC11_TMR_PWMC_OFFSET) + + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + */ + +/* Interrupt Register */ + +#define TMR_MR0INT (1 << 0) /* Bit 0: Match channel 0 interrupt */ +#define TMR_MR1INT (1 << 1) /* Bit 1: Match channel 1 interrupt */ +#define TMR_MR2INT (1 << 2) /* Bit 2: Match channel 2 interrupt */ +#define TMR_MR3INT (1 << 3) /* Bit 3: Match channel 3 interrupt */ +#define TMR_CR0INT (1 << 4) /* Bit 4: Capture channel 0 interrupt */ +#define TMR_CR1INT (1 << 5) /* Bit 5: Capture channel 1 interrupt */ + /* Bits 6-31: Reserved */ +/* Timer Control Register */ + +#define TMR_TCR_CEN (1 << 0) /* Bit 0: Counter Enable */ +#define TMR_TCR_CRST (1 << 1) /* Bit 1: Counter Reset */ + /* Bits 2-31: Reserved */ +/* Match Control Register */ + +#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ + /* Bits 12-31: Reserved */ +/* Capture Control Register */ + +#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */ +#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */ +#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* External Match Register */ + +#define TMR_EMR_NOTHING (0) /* Do Nothing */ +#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */ +#define TMR_EMR_SET (2) /* Set external match bit MATn.m */ +#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */ + +#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */ +#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */ +#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */ +#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */ +#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */ +#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy) +# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT) +# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT) +#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */ +#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT) +# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT) +#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */ +#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT) +# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT) +#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */ +#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT) +# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT) + /* Bits 12-31: Reserved */ +/* Count Control Register */ + +#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT) +# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */ +# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT) +# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */ +#define TMR_CTCR_ENCC (1 << 4) /* Enable Clear Timer/Prescale when capture event happens */ +#define TMR_CTCR_SELCC_SHIFT (5) /* Bits 5-7: Selects which capture event will clear Timer/Prescale */ +#define TMR_CTCR_SELCC_MASK (3 << TMR_CTCR_SELCC_SHIFT) +# define TMR_CTCR_SELCC_RECAP0 (0 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP0 clears timer (if bit 4 is set) */ +# define TMR_CTCR_SELCC_FECAP0 (1 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP0 clears timer (if bit 4 is set) */ +# define TMR_CTCR_SELCC_RECAP1 (2 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP1 clears timer (if bit 4 is set) */ +# define TMR_CTCR_SELCC_FECAP1 (3 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP1 clears timer (if bit 4 is set) */ + /* Bits 8-31: Reserved */ + +/* PWM Control register */ + +#define TMR_PWMC_PWMEN0 (1 << 0) /* PWM channel0 enable */ +#define TMR_PWMC_PWMEN1 (1 << 1) /* PWM channel1 enable */ +#define TMR_PWMC_PWMEN2 (1 << 2) /* PWM channel2 enable */ +#define TMR_PWMC_PWMEN3 (1 << 3) /* PWM channel3 enable */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_uart.h b/arch/arm/src/lpc11xx/chip/lpc11_uart.h new file mode 100644 index 00000000000..7d3dffd3b24 --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_uart.h @@ -0,0 +1,261 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_uart.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H +#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */ +#define LPC11_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */ +#define LPC11_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */ +#define LPC11_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */ +#define LPC11_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */ +#define LPC11_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */ +#define LPC11_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */ +#define LPC11_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */ +#define LPC11_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */ +#define LPC11_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */ +#define LPC11_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */ +#define LPC11_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */ +#define LPC11_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */ +#define LPC11_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */ +#define LPC11_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */ +#define LPC11_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */ +#define LPC11_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */ +#define LPC11_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */ + +/* Register addresses ***************************************************************/ + +#define LPC11_UART0_RBR (LPC11_UART0_BASE+LPC11_UART_RBR_OFFSET) +#define LPC11_UART0_THR (LPC11_UART0_BASE+LPC11_UART_THR_OFFSET) +#define LPC11_UART0_DLL (LPC11_UART0_BASE+LPC11_UART_DLL_OFFSET) +#define LPC11_UART0_DLM (LPC11_UART0_BASE+LPC11_UART_DLM_OFFSET) +#define LPC11_UART0_IER (LPC11_UART0_BASE+LPC11_UART_IER_OFFSET) +#define LPC11_UART0_IIR (LPC11_UART0_BASE+LPC11_UART_IIR_OFFSET) +#define LPC11_UART0_FCR (LPC11_UART0_BASE+LPC11_UART_FCR_OFFSET) +#define LPC11_UART0_LCR (LPC11_UART0_BASE+LPC11_UART_LCR_OFFSET) +#define LPC11_UART0_MCR (LPC11_UART0_BASE+LPC11_UART_MCR_OFFSET) +#define LPC11_UART0_LSR (LPC11_UART0_BASE+LPC11_UART_LSR_OFFSET) +#define LPC11_UART0_SCR (LPC11_UART0_BASE+LPC11_UART_SCR_OFFSET) +#define LPC11_UART0_ACR (LPC11_UART0_BASE+LPC11_UART_ACR_OFFSET) +#define LPC11_UART0_ICR (LPC11_UART0_BASE+LPC11_UART_ICR_OFFSET) +#define LPC11_UART0_FDR (LPC11_UART0_BASE+LPC11_UART_FDR_OFFSET) +#define LPC11_UART0_TER (LPC11_UART0_BASE+LPC11_UART_TER_OFFSET) +#define LPC11_UART0_RS485CTRL (LPC11_UART0_BASE+LPC11_UART_RS485CTRL_OFFSET) +#define LPC11_UART0_ADRMATCH (LPC11_UART0_BASE+LPC11_UART_ADRMATCH_OFFSET) +#define LPC11_UART0_RS485DLY (LPC11_UART0_BASE+LPC11_UART_RS485DLY_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* RBR (DLAB =0) Receiver Buffer Register (all) */ + +#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */ + /* Bits 8-31: Reserved */ + +/* THR (DLAB =0) Transmit Holding Register (all) */ + +#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */ + /* Bits 8-31: Reserved */ + +/* DLL (DLAB =1) Divisor Latch LSB (all) */ + +#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */ + /* Bits 8-31: Reserved */ + +/* DLM (DLAB =1) Divisor Latch MSB (all) */ + +#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */ + /* Bits 8-31: Reserved */ + +/* IER (DLAB =0) Interrupt Enable Register (all) */ + +#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */ +#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */ +#define UART_IER_RXLIE (1 << 2) /* Bit 2: RX Line Interrupt Enable */ + /* Bits 3-7: Reserved */ +#define UART_IER_ABEOINTEN (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOINTEN (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +#define UART_IER_ALLIE (0x038f) + +/* IIR Interrupt ID Register (all) */ + +#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */ +#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */ +#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT) +# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Interrupt */ +# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */ +# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */ +# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */ +# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */ + /* Bits 4-5: Reserved */ +#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */ +#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT) +#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */ +#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */ + /* Bits 10-31: Reserved */ +/* FCR FIFO Control Register (all) */ + +#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */ +#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */ +#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */ + /* Bits 3-5: Reserved */ +#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */ +#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT) +# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */ +# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */ +# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */ +# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */ + /* Bits 8-31: Reserved */ +/* LCR Line Control Register (all) */ + +#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */ +#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT) +#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */ +#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */ +#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */ +#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT) +# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */ +# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */ +# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */ +# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */ +#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */ +#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */ + /* Bits 8-31: Reserved */ +/* MCR Modem Control Register (UART1 only) */ + +#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */ +#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */ + /* Bits 2-3: Reserved */ +#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */ + /* Bit 5: Reserved */ +#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */ +#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */ + /* Bits 8-31: Reserved */ +/* LSR Line Status Register (all) */ + +#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */ +#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */ +#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ +#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ +#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ +#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ +#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ +#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ + /* Bits 8-31: Reserved */ +/* MSR Modem Status Register (UART1 only) */ + +#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */ +#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */ +#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */ +#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */ +#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */ +#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */ +#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */ +#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */ + /* Bits 8-31: Reserved */ +/* SCR Scratch Pad Register (all) */ + +#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */ + /* Bits 8-31: Reserved */ +/* ACR Auto-baud Control Register (all) */ + +#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/ +#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/ +#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/ + /* Bits 3-7: Reserved */ +#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ +#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ + /* Bits 10-31: Reserved */ + +/* FDR Fractional Divider Register (all) */ + +#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */ +#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT) +#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT) + /* Bits 8-31: Reserved */ +/* TER Transmit Enable Register (all) */ + /* Bits 0-6: Reserved */ +#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 Control */ + +#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */ +#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */ +#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */ +#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */ +#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */ +#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */ + /* Bits 6-31: Reserved */ +/* RS-485/EIA-485 address match */ + +#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */ + /* Bits 8-31: Reserved */ +/* RS-485/EIA-485 direction control delay (UART1 only) */ + +#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */ + /* Bits 8-31: Reserved */ +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H */ diff --git a/arch/arm/src/lpc11xx/chip/lpc11_wdt.h b/arch/arm/src/lpc11xx/chip/lpc11_wdt.h new file mode 100644 index 00000000000..e17eb48048d --- /dev/null +++ b/arch/arm/src/lpc11xx/chip/lpc11_wdt.h @@ -0,0 +1,102 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/chip/lpc11_wdt.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc11_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC11_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC11_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC11_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC11_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */ + +/* Register addresses ***************************************************************/ + +#define LPC11_WDT_MOD (LPC11_WDT_BASE+LPC11_WDT_MOD_OFFSET) +#define LPC11_WDT_TC (LPC11_WDT_BASE+LPC11_WDT_TC_OFFSET) +#define LPC11_WDT_FEED (LPC11_WDT_BASE+LPC11_WDT_FEED_OFFSET) +#define LPC11_WDT_TV (LPC11_WDT_BASE+LPC11_WDT_TV_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ + /* Bits 4-31: Reserved */ +/* Watchdog timer constant register */ + +#define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */ + /* Bits 24-31: Reserved */ + +/* Watchdog feed sequence register */ + +#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa + * followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register */ + +#define WDT_TV (0x00ffffff) /* Bits 0-23: Watchdog timer value */ + /* Bits 24-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */ diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.c b/arch/arm/src/lpc11xx/lpc111x_gpio.c new file mode 100644 index 00000000000..adbae8e5eb4 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc111x_gpio.c @@ -0,0 +1,730 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc111x_gpio.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "chip/lpc111x_iocon.h" +#include "lpc11_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default input pin configuration */ + +#define DEFAULT_INPUT (GPIO_INPUT|GPIO_PULLUP) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ +/* These tables have global scope because they are also used in + * lpc11_gpiodbg.c + */ + +/* We have to remember the configured interrupt setting.. PINs are not + * actually set up to interrupt until the interrupt is enabled. + */ + +#ifdef CONFIG_GPIO_IRQ +uint64_t g_intedge0; +uint64_t g_intedge2; +#endif + +/* GPIO register base addresses */ + +const uint32_t g_gpiobase[GPIO_NPORTS] = +{ + LPC11_GPIO0_BASE, + LPC11_GPIO1_BASE, + LPC11_GPIO2_BASE, + LPC11_GPIO3_BASE +}; + +/* Port 0 and Port 2 can provide a single interrupt for any combination of + * port pins + */ + +const uint32_t g_intbase[GPIO_NPORTS] = +{ +}; + +/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */ +/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */ + +const uint32_t iocon_port0[IOCON_NPINS] = +{ + LPC11_IOCON_P0_0, + LPC11_IOCON_P0_1, + LPC11_IOCON_P0_2, + LPC11_IOCON_P0_3, + LPC11_IOCON_P0_4, + LPC11_IOCON_P0_5, + LPC11_IOCON_P0_6, + LPC11_IOCON_P0_7, + LPC11_IOCON_P0_8, + LPC11_IOCON_P0_9, + LPC11_IOCON_P0_10, + LPC11_IOCON_P0_11 +}; + +const uint32_t iocon_port1[IOCON_NPINS] = +{ + LPC11_IOCON_P1_0, + LPC11_IOCON_P1_1, + LPC11_IOCON_P1_2, + LPC11_IOCON_P1_3, + LPC11_IOCON_P1_4, + LPC11_IOCON_P1_5, + LPC11_IOCON_P1_6, + LPC11_IOCON_P1_7, + LPC11_IOCON_P1_8, + LPC11_IOCON_P1_9, + LPC11_IOCON_P1_10, + LPC11_IOCON_P1_11 +}; + +const uint32_t iocon_port2[IOCON_NPINS] = +{ + LPC11_IOCON_P2_0, + LPC11_IOCON_P2_1, + LPC11_IOCON_P2_2, + LPC11_IOCON_P2_3, + LPC11_IOCON_P2_4, + LPC11_IOCON_P2_5, + LPC11_IOCON_P2_6, + LPC11_IOCON_P2_7, + LPC11_IOCON_P2_8, + LPC11_IOCON_P2_9, + LPC11_IOCON_P2_10, + LPC11_IOCON_P2_11 +}; + +const uint32_t iocon_port3[IOCON_NPINS] = +{ + LPC11_IOCON_P3_0, + LPC11_IOCON_P3_1, + LPC11_IOCON_P3_2, + LPC11_IOCON_P3_3, + LPC11_IOCON_P3_4, + LPC11_IOCON_P3_5, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_pinfunc + * + * Description: + * Set the PIN function in the IOCON register. + * + ****************************************************************************/ + +static int lpc11_pinfunc(unsigned int port, unsigned int pin, + unsigned int value) +{ + const uint32_t *table = NULL; + uint32_t regaddr; + uint32_t regval; + + switch (port) + { + case 0: + table = iocon_port0; + break; + case 1: + table = iocon_port1; + break; + case 2: + table = iocon_port2; + break; + case 3: + table = iocon_port3; + break; + } + + regaddr = table[pin]; + if (regaddr != 0) + { + /* Set the requested value in the IOCON register */ + + regval = getreg32(regaddr); + regval &= ~(IOCON_FUNC_MASK); + regval |= (value << IOCON_FUNC_SHIFT); + putreg32(regval, regaddr); + return OK; + + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc11_pullup + * + * Description: + * Get the address of the PINMODE register corresponding to this port and + * pin number. + * + ****************************************************************************/ + +static int lpc11_pullup(lpc11_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + const uint32_t *table = NULL; + uint32_t regaddr; + uint32_t regval; + uint32_t value; + + switch (cfgset & GPIO_PUMODE_MASK) + { + default: + case GPIO_PULLUP: /* Pull-up resistor enabled */ + value = IOCON_MODE_PU; + break; + + case GPIO_REPEATER: /* Repeater mode enabled */ + value = IOCON_MODE_RM; + break; + + case GPIO_FLOAT: /* Neither pull-up nor -down */ + value = IOCON_MODE_FLOAT; + break; + + case GPIO_PULLDN: /* Pull-down resistor enabled */ + value = IOCON_MODE_PD; + break; + } + + switch (port) + { + case 0: + table = iocon_port0; + break; + case 1: + table = iocon_port1; + break; + case 2: + table = iocon_port2; + break; + case 3: + table = iocon_port3; + break; + } + + + /* Fetch the IOCON register address for this port/pin combination */ + + regaddr = table[pin]; + if (regaddr != 0) + { + /* Set the requested value in the IOCON register */ + + regval = getreg32(regaddr); + regval &= ~(IOCON_MODE_MASK); + regval |= (value << IOCON_MODE_SHIFT); + putreg32(regval, regaddr); + return OK; + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc11_setintedge + * + * Description: + * Remember the configured interrupt edge. We can't actually enable the + * the edge interrupts until the called calls IRQ enabled function. + * + ****************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +static void lpc11_setintedge(unsigned int port, unsigned int pin, + unsigned int value) +{ + uint64_t *intedge; + unsigned int shift; + + /* Which word to we use? */ + + if (port == 0) + { + intedge = &g_intedge0; + } + else if (port == 2) + { + intedge = &g_intedge2; + } + else + { + return; + } + + /* Set the requested value in the IOCON register */ + + shift = pin << 1; + *intedge &= ~((uint64_t)3 << shift); + *intedge |= ((uint64_t)value << shift); +} +#endif /* CONFIG_GPIO_IRQ */ + +/**************************************************************************** + * Name: lpc11_setopendrain + * + * Description: + * Set the ODMODE register for open drain mode + * + ****************************************************************************/ + +static void lpc11_setopendrain(unsigned int port, unsigned int pin) +{ + const uint32_t *table = NULL; + uint32_t regaddr; + uint32_t regval; + + switch (port) + { + case 0: + table = iocon_port0; + break; + case 1: + table = iocon_port1; + break; + case 2: + table = iocon_port2; + break; + case 3: + table = iocon_port3; + break; + } + + regaddr = table[pin]; + if (regaddr != 0) + { + /* Set the requested value in the IOCON register */ + + regval = getreg32(regaddr); + regval &= ~(IOCON_OD_MASK); + regval |= (1 << IOCON_OD_SHIFT); + putreg32(regval, regaddr); + } +} + +/**************************************************************************** + * Name: lpc11_clropendrain + * + * Description: + * Reset the ODMODE register to disable open drain mode + * + ****************************************************************************/ + +static void lpc11_clropendrain(unsigned int port, unsigned int pin) +{ + const uint32_t *table = NULL; + uint32_t regaddr; + uint32_t regval; + + switch (port) + { + case 0: + table = iocon_port0; + break; + case 1: + table = iocon_port1; + break; + case 2: + table = iocon_port2; + break; + case 3: + table = iocon_port3; + break; + } + + regaddr = table[pin]; + if (regaddr != 0) + { + /* Set the requested value in the IOCON register */ + + regval = getreg32(regaddr); + regval &= ~(1 << IOCON_OD_SHIFT); + putreg32(regval, regaddr); + } +} + +/**************************************************************************** + * Name: lpc11_configinput + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int lpc11_configinput(lpc11_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + uint32_t regval; + uint32_t gpiobase; + uint32_t intbase; + uint32_t pinmask = (1 << pin); + + /* Set up GPIO registers */ + + gpiobase = g_gpiobase[port]; + + /* Set as input */ + + regval = getreg32(gpiobase + LPC11_GPIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, gpiobase + LPC11_GPIO_DIR_OFFSET); + + /* Set up interrupt registers */ + + intbase = g_intbase[port]; + if (intbase != 0) + { + /* Disable any rising edge interrupts */ + + regval = getreg32(intbase + LPC11_GPIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, intbase + LPC11_GPIO_DIR_OFFSET); + + /* Disable any falling edge interrupts */ + + regval = getreg32(intbase + LPC11_GPIO_DIR_OFFSET); + regval &= ~pinmask; + putreg32(regval, intbase + LPC11_GPIO_DIR_OFFSET); + + /* Forget about any falling/rising edge interrupt enabled */ + +#ifdef CONFIG_GPIO_IRQ + lpc11_setintedge(port, pin, 0); +#endif + } + + /* Set up IOCON registers */ + /* Configure as GPIO */ + + lpc11_pinfunc(port, pin, IOCON_FUNC_GPIO); + + /* Set pull-up mode */ + + lpc11_pullup(cfgset, port, pin); + + /* Open drain only applies to outputs */ + + lpc11_clropendrain(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: lpc11_configinterrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the + * pin. + * + ****************************************************************************/ + +static inline int lpc11_configinterrupt(lpc11_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + /* First, configure the port as a generic input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc11_configinput(cfgset, port, pin); + + /* Then just remember the rising/falling edge interrupt enabled */ + + DEBUGASSERT(port == 0 || port == 2); +#ifdef CONFIG_GPIO_IRQ + lpc11_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT); +#endif + return OK; +} + +/**************************************************************************** + * Name: lpc11_configoutput + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline int lpc11_configoutput(lpc11_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + uint32_t gpiobase; + uint32_t regval; + + /* First, configure the port as a generic input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc11_configinput(DEFAULT_INPUT, port, pin); + + /* Now, reconfigure the pin as an output */ + + gpiobase = g_gpiobase[port]; + regval = getreg32(gpiobase + LPC11_GPIO_DIR_OFFSET); + regval |= (1 << pin); + putreg32(regval, gpiobase + LPC11_GPIO_DIR_OFFSET); + + /* Check for open drain output */ + + if ((cfgset & GPIO_OPEN_DRAIN) != 0) + { + /* Set pull-up mode. This normally only applies to input pins, but does have + * meaning if the port is an open drain output. + */ + + lpc11_pullup(cfgset, port, pin); + + /* Select open drain output */ + + lpc11_setopendrain(port, pin); + } + + /* Set the initial value of the output */ + + lpc11_gpiowrite(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + + return OK; +} + +/**************************************************************************** + * Name: lpc11_configalternate + * + * Description: + * Configure a GPIO alternate function pin based on bit-encoded description + * of the pin. + * + ****************************************************************************/ + +static int lpc11_configalternate(lpc11_pinset_t cfgset, unsigned int port, + unsigned int pin, uint32_t alt) +{ + /* First, configure the port as an input so that we have a known + * starting point and consistent behavior during the re-configuration. + */ + + (void)lpc11_configinput(DEFAULT_INPUT, port, pin); + + /* Set up IOCON registers */ + /* Configure as GPIO */ + + lpc11_pinfunc(port, pin, alt); + + /* Set pull-up mode */ + + lpc11_pullup(cfgset, port, pin); + + /* Check for open drain output */ + + if ((cfgset & GPIO_OPEN_DRAIN) != 0) + { + /* Select open drain output */ + + lpc11_setopendrain(port, pin); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lpc11_configgpio(lpc11_pinset_t cfgset) +{ + unsigned int port; + unsigned int pin; + int ret = -EINVAL; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + ret = lpc11_configinput(cfgset, port, pin); + break; + + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + ret = lpc11_configinterrupt(cfgset, port, pin); + break; + + case GPIO_OUTPUT: /* GPIO outpout pin */ + ret = lpc11_configoutput(cfgset, port, pin); + break; + + case GPIO_ALT1: /* Alternate function 1 */ + ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT1); + break; + + case GPIO_ALT2: /* Alternate function 2 */ + ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT2); + break; + + case GPIO_ALT3: /* Alternate function 3 */ + ret = lpc11_configalternate(cfgset, port, pin, IOCON_FUNC_ALT3); + break; + + default: + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: lpc11_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lpc11_gpiowrite(lpc11_pinset_t pinset, bool value) +{ + uint32_t gpiobase; + uint32_t offset; + uint32_t regval; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the port base address */ + + gpiobase = g_gpiobase[port]; + + /* Get the pin number */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Set or clear the output on the pin */ + + offset = LPC11_GPIO_DATA_OFFSET; + + regval = getreg32(gpiobase + offset); + regval &= ~(1 << pin); + regval |= (value << pin); + putreg32(regval, gpiobase + offset); + } +} + +/**************************************************************************** + * Name: lpc11_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lpc11_gpioread(lpc11_pinset_t pinset) +{ + uint32_t gpiobase; + unsigned int port; + unsigned int pin; + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < GPIO_NPORTS) + { + /* Get the port base address */ + + gpiobase = g_gpiobase[port]; + + /* Get the pin number and return the input state of that pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + return ((getreg32(gpiobase + LPC11_GPIO_DATA_OFFSET) & (1 << pin)) != 0); + } + + return false; +} diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.h b/arch/arm/src/lpc11xx/lpc111x_gpio.h new file mode 100644 index 00000000000..aec89ce4f73 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc111x_gpio.h @@ -0,0 +1,178 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc111x_gpio.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H +#define __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Bit-encoded input to lpc11_configgpio() ******************************************/ + +/* Encoding: FFFF xxMM OVPP NNNN + * + * Pin Function: FFF + * Pin Mode bits: MM + * Open drain: O (output pins) + * Initial value: V (output pins) + * Port number: PP (0-3) + * Pin number: NNNN (0-11) + */ + +/* Pin Function bits: FFF + * Only meaningful when the GPIO function is GPIO_PIN + */ + +#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */ +#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */ +# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */ +# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */ +# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO output pin */ +# define GPIO_ALT_GPIO (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function is a GPIO */ +# define GPIO_ALT0 (5 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 0 */ +# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 1 */ +# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 2 */ +# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 3 */ + +#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) + +#define GPIO_INOUT_MASK GPIO_OUTPUT +#define GPIO_FE_MASK GPIO_INTFE +#define GPIO_RE_MASK GPIO_INTRE + +#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) < GPIO_ALT0) +#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) >= GPIO_ALT0) +#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT) +#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT) +#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0) +#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0) +#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps)) +#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0) +#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0) + +/* Pin Mode: MM */ + +#define GPIO_PUMODE_SHIFT (8) /* Bits 8-9: Pin pull-up mode */ +#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT) +# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */ +# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */ + +/* Open drain: O */ + +#define GPIO_OPEN_DRAIN (1 << 7) /* Bit 7: Open drain mode */ + +/* Initial value: V */ + +#define GPIO_VALUE (1 << 6) /* Bit 6: Initial GPIO output value */ +#define GPIO_VALUE_ONE GPIO_VALUE +#define GPIO_VALUE_ZERO (0) + +/* Port number: PP (0-3) */ + +#define GPIO_PORT_SHIFT (4) /* Bit 4-5: Port number */ +#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) + +#define GPIO_NPORTS 4 + +/* Pin number: NNNN (0-11) */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-11 */ +#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +typedef uint16_t lpc11_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* These tables have global scope only because they are shared between lpc11_gpio.c, + * lpc11_gpioint.c, and lpc11_gpiodbg.c + */ + +EXTERN const uint32_t g_lopinsel[GPIO_NPORTS]; +EXTERN const uint32_t g_hipinsel[GPIO_NPORTS]; +EXTERN const uint32_t g_lopinmode[GPIO_NPORTS]; +EXTERN const uint32_t g_hipinmode[GPIO_NPORTS]; +EXTERN const uint32_t g_odmode[GPIO_NPORTS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_clockconfig.c b/arch/arm/src/lpc11xx/lpc11_clockconfig.c new file mode 100644 index 00000000000..804b6d29610 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_clockconfig.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_clockconfig.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "lpc11_clockconfig.h" +#include "chip/lpc11_syscon.h" +#include "chip/lpc111x_iocon.h" +#include "chip/lpc11_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_clockconfig + * + * Description: + * Called to initialize the LPC11xx. This does whatever setup is needed + * to put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void lpc11_clockconfig(void) +{ + int regval; + + /* Enable the main oscillator (or not) and the frequency range of the main + * oscillator. + */ + +#ifdef CONFIG_LPC11_INTRCOSC + regval = SYSCON_SYSPLLCLKSEL_IRCOSC; +#else + regval = SYSCON_SYSPLLCLKSEL_SYSOSC; +#endif + putreg32(regval, LPC11_SYSCON_SYSPLLCLKSEL); + + /* MSEL = 3 , PSEL = 1 */ + + putreg32((SYSCON_SYSPLLCTRL_MSEL_DIV(4) | SYSCON_SYSPLLCTRL_PSEL_DIV2), + LPC11_SYSCON_SYSPLLCTRL); + + /* Power UP the PLL */ + + regval = getreg32(LPC11_SYSCON_PDRUNCFG); + regval &= ~(SYSCON_PDRUNCFG_SYSPLL_PD); + putreg32(regval, LPC11_SYSCON_PDRUNCFG); + + /* Inform the core to use PLL as clock */ + + putreg32(SYSCON_MAINCLKSEL_PLLOSC, LPC11_SYSCON_SYSPLLCLKUEN); + + /* Use PLL as main clock */ + + putreg32(SYSCON_MAINCLKSEL_SYSPLLCLKOUT, LPC11_SYSCON_MAINCLKSEL); + + /* Inform the core of clock update */ + + putreg32(SYSCON_MAINCLKUEN_ENA, LPC11_SYSCON_MAINCLKUEN); +} diff --git a/arch/arm/src/lpc11xx/lpc11_clockconfig.h b/arch/arm/src/lpc11xx/lpc11_clockconfig.h new file mode 100644 index 00000000000..ebec697945a --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_clockconfig.h @@ -0,0 +1,84 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_clockconfig.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_clockconfig + * + * Description: + * Called to initialize the LPC11XX. This does whatever setup is needed to put the + * MCU in a usable state. This includes the initialization of clocking using the + * settings in board.h. + * + ************************************************************************************/ + +void lpc11_clockconfig(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.c b/arch/arm/src/lpc11xx/lpc11_gpio.c new file mode 100644 index 00000000000..932740af883 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_gpio.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_gpio.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* This file is only a thin shell that includes the correct GPIO logic for + * the selected LPC17xx family. The correct file cannot be selected by the + * make system because it needs the intelligence that only exists in chip.h + * that can associate an LPC17xx part number with an LPC17xx family. + */ + +#include + +#if defined(LPC111x) +# include "lpc111x_gpio.c" +#elif defined(LPC11C) +# include "lpc11c_gpio.c" +#else +# error "Unrecognized LPC11xx family" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h new file mode 100644 index 00000000000..4d92c973b08 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_gpio.h @@ -0,0 +1,194 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_gpio.h + * + * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include + +#include "chip/lpc11_gpio.h" +#include "chip/lpc11_pinconfig.h" + +/* Include the GPIO definitions for the selected LPC17xx family. */ + +#if defined(LPC111x) +# include "lpc111x_gpio.h" +#elif defined(LPC11C) +# include "lpc11c_gpio.h" +#else +# error "Unrecognized LPC11xx family" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* These tables have global scope only because they are shared between lpc11_gpio.c, + * lpc11_gpioint.c, and lpc11_gpiodbg.c + */ + +#ifdef CONFIG_GPIO_IRQ +EXTERN uint64_t g_intedge0; +EXTERN uint64_t g_intedge2; +#endif + +EXTERN const uint32_t g_fiobase[GPIO_NPORTS]; +EXTERN const uint32_t g_intbase[GPIO_NPORTS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: lpc11_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for GPIO pins. + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc11_gpioirqinitialize(void); +#else +# define lpc11_gpioirqinitialize() +#endif + +/************************************************************************************ + * Name: lpc11_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int lpc11_configgpio(lpc11_pinset_t cfgset); + +/************************************************************************************ + * Name: lpc11_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void lpc11_gpiowrite(lpc11_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: lpc11_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool lpc11_gpioread(lpc11_pinset_t pinset); + +/************************************************************************************ + * Name: lpc11_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc11_gpioirqenable(int irq); +#else +# define lpc11_gpioirqenable(irq) +#endif + +/************************************************************************************ + * Name: lpc11_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ************************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +void lpc11_gpioirqdisable(int irq); +#else +# define lpc11_gpioirqdisable(irq) +#endif + +/************************************************************************************ + * Function: lpc11_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO +int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg); +#else +# define lpc11_dumpgpio(p,m) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c new file mode 100644 index 00000000000..45e7d311f68 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_gpiodbg.c + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc11_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_GPIO +#endif + +#ifdef CONFIG_DEBUG_GPIO + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_pinsel + * + * Description: + * Get the address of the PINSEL register corresponding to this port and + * pin number. + * + ****************************************************************************/ + +#ifdef LPC176x +static uint32_t lpc11_pinsel(unsigned int port, unsigned int pin) +{ + if (pin < 16) + { + return g_lopinsel[port]; + } + else + { + return g_hipinsel[port]; + } +} +#endif /* LPC176x */ + +/**************************************************************************** + * Name: lpc11_pinmode + * + * Description: + * Get the address of the PINMODE register corresponding to this port and + * pin number. + * + ****************************************************************************/ + +#ifdef LPC176x +static uint32_t lpc11_pinmode(unsigned int port, unsigned int pin) +{ + if (pin < 16) + { + return g_lopinmode[port]; + } + else + { + return g_hipinmode[port]; + } +} +#endif /* LPC176x */ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lpc11_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg) +{ + irqstate_t flags; + uint32_t base; +#if defined(LPC176x) + uint32_t pinsel; + uint32_t pinmode; +#elif defined(LPC178x) + uint32_t iocon; +#endif /* LPC176x */ + unsigned int port; + unsigned int pin; + + /* Get the base address associated with the GPIO port */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + +#if defined(LPC176x) + pinsel = lpc11_pinsel(port, pin); + pinmode = lpc11_pinmode(port, pin); +#elif defined(LPC178x) + iocon = LPC17_IOCON_P(port, pin); +#endif /* LPC176x */ + + /* The following requires exclusive access to the GPIO registers */ + + flags = irqsave(); + lldbg("GPIO%c pin%d (pinset: %08x) -- %s\n", + port + '0', pin, pinset, msg); + +#if defined(LPC176x) + lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n", + pinsel, pinsel ? getreg32(pinsel) : 0, + pinmode, pinmode ? getreg32(pinmode) : 0, + g_odmode[port], getreg32(g_odmode[port])); +#elif defined(LPC178x) + lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon)); +#endif + + base = g_fiobase[port]; + lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n", + base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET), + base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET), + base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET)); + + base = g_intbase[port]; + lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n", + LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS), + base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET), + base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET)); + lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n", + base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET), + base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET)); + irqrestore(flags); + return OK; +} +#endif /* CONFIG_DEBUG_GPIO */ + diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c new file mode 100644 index 00000000000..82e22d564fc --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c @@ -0,0 +1,547 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_gpioint.c + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc11_gpio.h" + +#ifdef CONFIG_GPIO_IRQ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_getintedge + * + * Description: + * Get the stored interrupt edge configuration. + * + ****************************************************************************/ + +static unsigned int lpc11_getintedge(unsigned int port, unsigned int pin) +{ + uint64_t *intedge; + + /* Which word to we use? */ + + if (port == 0) + { + intedge = &g_intedge0; + } + else if (port == 2) + { + intedge = &g_intedge2; + } + else + { + return 0; + } + + /* Return the value for the PINSEL */ + + return (unsigned int)(((*intedge) >> (pin << 1)) & 3); +} + +/**************************************************************************** + * Name: lpc11_setintedge + * + * Description: + * Set the edge interrupt enabled bits for this pin. + * + ****************************************************************************/ + +static void lpc11_setintedge(uint32_t intbase, unsigned int pin, + unsigned int edges) +{ + irqstate_t flags; + int regval; + + /* These must be atomic */ + + flags = irqsave(); + + /* Set/clear the rising edge enable bit */ + + regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + if ((edges & 2) != 0) + { + regval |= GPIOINT(pin); + } + else + { + regval &= ~GPIOINT(pin); + } + + putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET); + + /* Set/clear the falling edge enable bit */ + + regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + if ((edges & 1) != 0) + { + regval |= GPIOINT(pin); + } + else + { + regval &= ~GPIOINT(pin); + } + + putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET); + irqrestore(flags); +} + +/**************************************************************************** + * Name: lpc11_irq2port + * + * Description: + * Given an IRQ number, return the GPIO port number (0 or 2) of the interrupt. + * + ****************************************************************************/ + +static int lpc11_irq2port(int irq) +{ + /* Set 1: + * LPC176x: 12 interrupts p0.0-p0.11 + * LPC178x: 16 interrupts p0.0-p0.15 + */ + + if (irq >= LPC17_VALID_FIRST0L && + irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L)) + { + return 0; + } + + /* Set 2: + * LPC176x: 16 interrupts p0.15-p0.30 + * LPC178x: 16 interrupts p0.16-p0.31 + */ + + else if (irq >= LPC17_VALID_FIRST0H && + irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H)) + { + return 0; + } + +#if defined (LPC176x) + /* Set 3: + * LPC17x: 14 interrupts p2.0-p2.13 + */ + + else if (irq >= LPC17_VALID_FIRST2 && + irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2)) + { + return 2; + } + +#elif defined (LPC178x) + /* Set 3: + * LPC18x: 16 interrupts p2.0-p2.15 + */ + + else if (irq >= LPC17_VALID_FIRST2L && + irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L)) + { + return 2; + } + + /* Set 4: + * LPC178x: 16 interrupts p2.16-p2.31 + */ + + else if (irq >= LPC17_VALID_FIRST2H && + irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H)) + { + return 2; + } + +#endif + + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc11_irq2pin + * + * Description: + * Given an IRQ number, return the GPIO pin number (0..31) of the interrupt. + * + ****************************************************************************/ + +static int lpc11_irq2pin(int irq) +{ + /* Set 1: + * LPC17x: 12 interrupts p0.0-p0.11 + * LPC18x: 16 interrupts p0.0-p0.15 + * + * See arch/arm/include/lpc11xx/irq.h: + * LPC17_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of + * 12/16 interrupts + * LPC17_VALID_FIRST0L irq - IRQ number associated with p0.0 + * LPC17_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group + */ + + if (irq >= LPC17_VALID_FIRST0L && + irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L)) + { + return irq - LPC17_VALID_FIRST0L + LPC17_VALID_SHIFT0L; + } + + /* Set 2: + * LPC176x: 16 interrupts p0.15-p0.30 + * LPC178x: 16 interrupts p0.16-p0.31 + * + * LPC17_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group + * of 16 interrupts + * LPC17_VALID_FIRST0L irq - IRQ number associated with p0.15/16 + * LPC17_VALID_NIRQS0L 16 - 16 interrupt bits in the group + */ + + else if (irq >= LPC17_VALID_FIRST0H && + irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H)) + { + return irq - LPC17_VALID_FIRST0H + LPC17_VALID_SHIFT0H; + } + +#if defined(LPC176x) + /* Set 3: + * LPC17x: 14 interrupts p2.0-p2.13 + * + * LPC17_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14 + * interrupts + * LPC17_VALID_FIRST2 irq - IRQ number associated with p2.0 + * LPC17_VALID_NIRQS2 14 - 14 interrupt bits in the group + */ + + else if (irq >= LPC17_VALID_FIRST2 && + irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2)) + { + return irq - LPC17_VALID_FIRST2 + LPC17_VALID_SHIFT2; + } + +#elif defined(LPC178x) + + /* Set 3: + * LPC18x: 16 interrupts p2.0-p2.15 + * + * LPC17_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16 + * interrupts + * LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0 + * LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group + */ + + else if (irq >= LPC17_VALID_FIRST2L && + irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L)) + { + return irq - LPC17_VALID_FIRST2L + LPC17_VALID_SHIFT2L; + } + + /* Set 3: + * LPC18x: 16 interrupts p2.16-p2.31 + * + * LPC17_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16 + * interrupts + * LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0 + * LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group + */ + + else if (irq >= LPC17_VALID_FIRST2H && + irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H)) + { + return irq - LPC17_VALID_FIRST2H + LPC17_VALID_SHIFT2H; + } + +#endif + + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc11_gpiodemux + * + * Description: + * Demux all interrupts on one GPIO interrupt status register. + * + ****************************************************************************/ + +static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask, + int irqbase, void *context) +{ + uint32_t intstatr; + uint32_t intstatf; + uint32_t intstatus; + uint32_t bit; + int irq; + + /* Get the interrupt rising and falling edge status and mask out only the + * interrupts that are enabled. + */ + + intstatr = getreg32(intbase + LPC17_GPIOINT_INTSTATR_OFFSET); + intstatr &= getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET); + + intstatf = getreg32(intbase + LPC17_GPIOINT_INTSTATF_OFFSET); + intstatf &= getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET); + + /* And get the OR of the enabled interrupt sources. We do not make any + * distinction between rising and falling edges (but the hardware does support + * the ability to handle them differently if needed). + */ + + intstatus = intstatr | intstatf; + + /* Now march through the (valid) bits and dispatch each interrupt */ + + irq = irqbase; + bit = 1; + while (intstatus != 0) + { + /* Does this pin support an interrupt? If no, skip over it WITHOUT + * incrementing irq. + */ + + if ((intmask & bit) != 0) + { + /* This pin can support an interrupt. Is there an interrupt pending + * and enabled? + */ + + if ((intstatus & bit) != 0) + { + /* Clear the interrupt status */ + + putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET); + + /* And dispatch the interrupt */ + + irq_dispatch(irq, context); + } + + /* Increment the IRQ number on each interrupt pin */ + + irq++; + } + + /* Next bit */ + + intstatus &= ~bit; + bit <<= 1; + } +} + +/**************************************************************************** + * Name: lpc11_gpiointerrupt + * + * Description: + * Handle the GPIO interrupt. For the LPC176x family, that interrupt could + * also that also indicates that an EINT3 interrupt has occurred. NOTE: + * This logic would have to be extended if EINT3 is actually used for + * External Interrupt 3 on an LPC176x platform. + * + ****************************************************************************/ + +static int lpc11_gpiointerrupt(int irq, void *context) +{ + /* Get the GPIO interrupt status */ + + uint32_t intstatus = getreg32(LPC17_GPIOINT_IOINTSTATUS); + + /* Check for an interrupt on GPIO0 */ + + if ((intstatus & GPIOINT_IOINTSTATUS_P0INT) != 0) + { + lpc11_gpiodemux(LPC17_GPIOINT0_BASE, LPC17_VALID_GPIOINT0, + LPC17_VALID_FIRST0L, context); + } + +#if defined(LPC176x) + /* Check for an interrupt on GPIO2 */ + + if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) + { + lpc11_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2, + LPC17_VALID_FIRST2, context); + } + +#elif defined(LPC178x) + /* Check for an interrupt on GPIO2 */ + + if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0) + { + lpc11_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2, + LPC17_VALID_FIRST2L, context); + } + +#endif + + return OK; +} + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +void lpc11_gpioirqinitialize(void) +{ + /* Disable all GPIO interrupts */ + + putreg32(0, LPC17_GPIOINT0_INTENR); + putreg32(0, LPC17_GPIOINT0_INTENF); + putreg32(0, LPC17_GPIOINT2_INTENR); + putreg32(0, LPC17_GPIOINT2_INTENF); + + /* Attach and enable the GPIO IRQ. */ + +#if defined(LPC176x) + /* For the LPC176x family, GPIO0 and GPIO2 interrupts share the same + * position in the NVIC with External Interrupt 3 + */ + + (void)irq_attach(LPC17_IRQ_EINT3, lpc11_gpiointerrupt); + up_enable_irq(LPC17_IRQ_EINT3); + +#elif defined(LPC178x) + /* the LPC178x family has a single, dedicated interrupt for GPIO0 and + * GPIO2. + */ + + (void)irq_attach(LPC17_IRQ_GPIO, lpc11_gpiointerrupt); + up_enable_irq(LPC17_IRQ_GPIO); + +#endif +} + +/**************************************************************************** + * Name: lpc11_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +void lpc11_gpioirqenable(int irq) +{ + /* Map the IRQ number to a port number */ + + int port = lpc11_irq2port(irq); + if (port >= 0) + { + /* The IRQ number does correspond to an interrupt port. Now get the base + * address of the GPIOINT registers for the port. + */ + + uint32_t intbase = g_intbase[port]; + if (intbase != 0) + { + /* And get the pin number associated with the port */ + + unsigned int pin = lpc11_irq2pin(irq); + unsigned int edges = lpc11_getintedge(port, pin); + lpc11_setintedge(intbase, pin, edges); + } + } +} + +/**************************************************************************** + * Name: lpc11_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +void lpc11_gpioirqdisable(int irq) +{ + /* Map the IRQ number to a port number */ + + int port = lpc11_irq2port(irq); + if (port >= 0) + { + /* The IRQ number does correspond to an interrupt port. Now get the base + * address of the GPIOINT registers for the port. + */ + + uint32_t intbase = g_intbase[port]; + if (intbase != 0) + { + /* And get the pin number associated with the port */ + + unsigned int pin = lpc11_irq2pin(irq); + lpc11_setintedge(intbase, pin, 0); + } + } +} + +#endif /* CONFIG_GPIO_IRQ */ + diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c new file mode 100644 index 00000000000..f17a318595f --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -0,0 +1,608 @@ +/******************************************************************************* + * arch/arm/src/lpc11xx/lpc11_i2c.c + * + * Copyright (C) 2011 Li Zhuoyi. All rights reserved. + * Author: Li Zhuoyi + * History: 0.1 2011-08-20 initial version + * + * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c + * + * Author: David Hewson + * + * Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +/******************************************************************************* + * Included Files + *******************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip.h" +#include "chip/lpc11_syscon.h" +#include "lpc11_gpio.h" +#include "lpc11_i2c.h" + +#if defined(CONFIG_LPC11_I2C0) || defined(CONFIG_LPC11_I2C1) || defined(CONFIG_LPC11_I2C2) + +/******************************************************************************* + * Pre-processor Definitions + *******************************************************************************/ + +#ifndef GPIO_I2C1_SCL + #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 + #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#endif + +#ifndef CONFIG_I2C0_FREQ + #define CONFIG_I2C0_FREQ 100000 +#endif + +#ifndef CONFIG_I2C1_FREQ + #define CONFIG_I2C1_FREQ 100000 +#endif + +#ifndef CONFIG_I2C2_FREQ + #define CONFIG_I2C2_FREQ 100000 +#endif + +#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ + +/******************************************************************************* + * Private Types + *******************************************************************************/ + +struct lpc11_i2cdev_s +{ + struct i2c_dev_s dev; /* Generic I2C device */ + struct i2c_msg_s msg; /* a single message for legacy read/write */ + unsigned int base; /* Base address of registers */ + uint16_t irqid; /* IRQ for this device */ + + sem_t mutex; /* Only one thread can access at a time */ + sem_t wait; /* Place to wait for state machine completion */ + volatile uint8_t state; /* State of state machine */ + WDOG_ID timeout; /* watchdog to timeout when bus hung */ + + uint16_t wrcnt; /* number of bytes sent to tx fifo */ + uint16_t rdcnt; /* number of bytes read from rx fifo */ +}; + +/******************************************************************************* + * Private Function Prototypes + *******************************************************************************/ + +static int i2c_start(struct lpc11_i2cdev_s *priv); +static void i2c_stop(struct lpc11_i2cdev_s *priv); +static int i2c_interrupt(int irq, FAR void *context); +static void i2c_timeout(int argc, uint32_t arg, ...); + +/* I2C device operations */ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency); +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen); +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); +static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); + +/******************************************************************************* + * Private Data + *******************************************************************************/ + +static struct lpc11_i2cdev_s i2cdevices[3]; + +struct i2c_ops_s lpc11_i2c_ops = +{ + .setfrequency = i2c_setfrequency, + .setaddress = i2c_setaddress, + .write = i2c_write, + .read = i2c_read, +#ifdef CONFIG_I2C_TRANSFER + .transfer = i2c_transfer +#endif +}; + +/******************************************************************************* + * Name: lpc11_i2c_setfrequency + * + * Description: + * Set the frequency for the next transfer + * + *******************************************************************************/ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; + + if (frequency > 100000) + { + /* Asymetric per 400Khz I2C spec */ + + putreg32(LPC11_CCLK / (83 + 47) * 47 / frequency, + priv->base + LPC11_I2C_SCLH_OFFSET); + putreg32(LPC11_CCLK / (83 + 47) * 83 / frequency, + priv->base + LPC11_I2C_SCLL_OFFSET); + } + else + { + /* 50/50 mark space ratio */ + + putreg32(LPC11_CCLK / 100 * 50 / frequency, + priv->base + LPC11_I2C_SCLH_OFFSET); + putreg32(LPC11_CCLK / 100 * 50 / frequency, + priv->base + LPC11_I2C_SCLL_OFFSET); + } + + /* FIXME: This function should return the actual selected frequency */ + + return frequency; +} + +/******************************************************************************* + * Name: lpc11_i2c_setaddress + * + * Description: + * Set the I2C slave address for a subsequent read/write + * + *******************************************************************************/ + +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(nbits == 7 ); + + priv->msg.addr = addr << 1; + priv->msg.flags = 0 ; + + return OK; +} + +/******************************************************************************* + * Name: lpc11_i2c_write + * + * Description: + * Send a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ + +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, + int buflen) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; + int ret; + + DEBUGASSERT(dev != NULL); + + priv->wrcnt = 0; + priv->rdcnt = 0; + priv->msg.addr &= ~0x01; + priv->msg.buffer = (uint8_t*)buffer; + priv->msg.length = buflen; + + ret = i2c_start(priv); + + return ret > 0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: lpc11_i2c_read + * + * Description: + * Receive a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ + +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; + int ret; + + DEBUGASSERT(dev != NULL); + + priv->wrcnt = 0; + priv->rdcnt = 0; + priv->msg.addr |= 0x01; + priv->msg.buffer = buffer; + priv->msg.length = buflen; + + ret = i2c_start(priv); + + return ret > 0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: i2c_start + * + * Description: + * Perform a I2C transfer start + * + *******************************************************************************/ + +static int i2c_start(struct lpc11_i2cdev_s *priv) +{ + int ret = -1; + + sem_wait(&priv->mutex); + + putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET); + putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET); + + wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); + sem_wait(&priv->wait); + wd_cancel(priv->timeout); + sem_post(&priv->mutex); + + if (priv-> state == 0x18 || priv->state == 0x28) + { + ret = priv->wrcnt; + } + else if (priv-> state == 0x50 || priv->state == 0x58) + { + ret = priv->rdcnt; + } + + return ret; +} + +/******************************************************************************* + * Name: i2c_stop + * + * Description: + * Perform a I2C transfer stop + * + *******************************************************************************/ + +static void i2c_stop(struct lpc11_i2cdev_s *priv) +{ + if (priv->state != 0x38) + { + putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET); + } + + sem_post(&priv->wait); +} + +/******************************************************************************* + * Name: i2c_timeout + * + * Description: + * Watchdog timer for timeout of I2C operation + * + *******************************************************************************/ + +static void i2c_timeout(int argc, uint32_t arg, ...) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) arg; + + irqstate_t flags = irqsave(); + priv->state = 0xff; + sem_post(&priv->wait); + irqrestore(flags); +} + +/******************************************************************************* + * Name: i2c_interrupt + * + * Description: + * The I2C Interrupt Handler + * + *******************************************************************************/ + +static int i2c_interrupt(int irq, FAR void *context) +{ + struct lpc11_i2cdev_s *priv; + uint32_t state; + +#ifdef CONFIG_LPC11_I2C0 + if (irq == LPC11_IRQ_I2C0) + { + priv=&i2cdevices[0]; + } + else +#endif +#ifdef CONFIG_LPC11_I2C1 + if (irq == LPC11_IRQ_I2C1) + { + priv=&i2cdevices[1]; + } + else +#endif +#ifdef CONFIG_LPC11_I2C2 + if (irq == LPC11_IRQ_I2C2) + { + priv=&i2cdevices[2]; + } + else +#endif + { + PANIC(); + } + + /* Reference UM10360 19.10.5 */ + + state = getreg32(priv->base + LPC11_I2C_STAT_OFFSET); + putreg32(I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET); + priv->state = state; + state &= 0xf8; + + switch (state) + { + case 0x00: // Bus Error + case 0x20: + case 0x30: + case 0x38: + case 0x48: + i2c_stop(priv); + break; + + case 0x08: // START + case 0x10: // Repeat START + putreg32(priv->msg.addr, priv->base + LPC11_I2C_DAT_OFFSET); + putreg32(I2C_CONCLR_STAC, priv->base + LPC11_I2C_CONCLR_OFFSET); + break; + + case 0x18: + priv->wrcnt = 0; + putreg32(priv->msg.buffer[0], priv->base + LPC11_I2C_DAT_OFFSET); + break; + + case 0x28: + priv->wrcnt++; + if (priv->wrcntmsg.length) + { + putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC11_I2C_DAT_OFFSET); + } + else + { + i2c_stop(priv); + } + break; + + case 0x40: + priv->rdcnt = 0; + putreg32(I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET); + break; + + case 0x50: + if (priv->rdcnt < priv->msg.length) + { + priv->msg.buffer[priv->rdcnt] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET); + priv->rdcnt++; + } + + if (priv->rdcnt >= priv->msg.length) + { + putreg32(I2C_CONCLR_AAC | I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET); + } + break; + + case 0x58: + i2c_stop(priv); + break; + + default: + i2c_stop(priv); + break; + } + + return OK; +} + +/******************************************************************************* + * Public Functions + *******************************************************************************/ + +/******************************************************************************* + * Name: up_i2cinitialize + * + * Description: + * Initialise an I2C device + * + *******************************************************************************/ + +struct i2c_dev_s *up_i2cinitialize(int port) +{ + struct lpc11_i2cdev_s *priv; + irqstate_t flags; + uint32_t regval; + + if (port > 2) + { + dbg("lpc I2C Only support 0,1,2\n"); + return NULL; + } + + flags = irqsave(); + + priv= &i2cdevices[port]; +#ifdef CONFIG_LPC11_I2C0 + if (port == 0) + { + priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[0]; + priv->base = LPC11_I2C0_BASE; + priv->irqid = LPC11_IRQ_I2C0; + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C0; + putreg32(regval, LPC11_SYSCON_PCONP); + + regval = getreg32(LPC11_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_I2C0_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL0); + + lpc11_configgpio(GPIO_I2C0_SCL); + lpc11_configgpio(GPIO_I2C0_SDA); + + putreg32(LPC11_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET); + putreg32(LPC11_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET); + } + else +#endif +#ifdef CONFIG_LPC11_I2C1 + if (port == 1) + { + priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[1]; + priv->base = LPC11_I2C1_BASE; + priv->irqid = LPC11_IRQ_I2C1; + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C1; + putreg32(regval, LPC11_SYSCON_PCONP); + + regval = getreg32(LPC11_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL1); + + lpc11_configgpio(GPIO_I2C1_SCL); + lpc11_configgpio(GPIO_I2C1_SDA); + + putreg32(LPC11_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET); + putreg32(LPC11_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET); + } + else +#endif +#ifdef CONFIG_LPC11_I2C2 + if (port == 2) + { + priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[2]; + priv->base = LPC11_I2C2_BASE; + priv->irqid = LPC11_IRQ_I2C2; + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C2; + putreg32(regval, LPC11_SYSCON_PCONP); + + regval = getreg32(LPC11_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL1); + + lpc11_configgpio(GPIO_I2C2_SCL); + lpc11_configgpio(GPIO_I2C2_SDA); + + putreg32(LPC11_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET); + putreg32(LPC11_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET); + } + else +#endif + { + irqrestore(flags); + return NULL; + } + + putreg32(I2C_CONSET_I2EN, priv->base + LPC11_I2C_CONSET_OFFSET); + + sem_init(&priv->mutex, 0, 1); + sem_init(&priv->wait, 0, 0); + + /* Allocate a watchdog timer */ + + priv->timeout = wd_create(); + DEBUGASSERT(priv->timeout != 0); + + /* Attach Interrupt Handler */ + + irq_attach(priv->irqid, i2c_interrupt); + + /* Enable Interrupt Handler */ + + up_enable_irq(priv->irqid); + + /* Install our operations */ + + priv->dev.ops = &lpc11_i2c_ops; + + irqrestore(flags); + return &priv->dev; +} + +/******************************************************************************* + * Name: up_i2cuninitalize + * + * Description: + * Uninitialise an I2C device + * + *******************************************************************************/ + +int up_i2cuninitialize(FAR struct i2c_dev_s * dev) +{ + struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev; + + /* Disable I2C */ + + putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC11_I2C_CONCLR_OFFSET); + + /* Reset data structures */ + + sem_destroy(&priv->mutex); + sem_destroy(&priv->wait); + + /* Free the watchdog timer */ + + wd_delete(priv->timeout); + priv->timeout = NULL; + + /* Disable interrupts */ + + up_disable_irq(priv->irqid); + + /* Detach Interrupt Handler */ + + irq_detach(priv->irqid); + return OK; +} + +#endif diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.h b/arch/arm/src/lpc11xx/lpc11_i2c.h new file mode 100644 index 00000000000..4b5097a955f --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_i2c.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_i2c.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc11_i2c.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_idle.c b/arch/arm/src/lpc11xx/lpc11_idle.c new file mode 100644 index 00000000000..f258c2b0c96 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_idle.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/arm/src/lpc11/lpc11_idle.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_led_on(LED_IDLE) +# define END_IDLE() board_led_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + +/* If the g_dma_inprogress is zero, then there is no DMA in progress. This + * value is needed in the IDLE loop to determine if the IDLE loop should + * go into lower power power consumption modes. According to the LPC17xx + * User Manual: "The DMA controller can continue to work in Sleep mode, and + * has access to the peripheral SRAMs and all peripheral registers. The + * flash memory and the Main SRAM are not available in Sleep mode, they are + * disabled in order to save power." + */ + +#ifdef CONFIG_LPC17_GPDMA + if (g_dma_inprogress == 0) +#endif + { + /* Sleep until an interrupt occurs in order to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); + } +#endif +} diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c new file mode 100644 index 00000000000..edd22842a9a --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_irq.c @@ -0,0 +1,338 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_irq.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "up_internal.h" + +//#include "lpc11_irq.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ) +static void lpc11_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = irqsave(); + + lldbg("NVIC (%s, irq=%d):\n", msg, irq); + lldbg(" ISER: %08x ICER: %08x\n", + getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER)); + lldbg(" ISPR: %08x ICPR: %08x\n", + getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); + lldbg(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1), + getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3)); + lldbg(" %08x %08x %08x %08x\n", + getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5), + getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7)); + + lldbg("SYSCON:\n"); + lldbg(" CPUID: %08x\n", + getreg32(ARMV6M_SYSCON_CPUID)); + lldbg(" ICSR: %08x AIRCR: %08x\n", + getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR)); + lldbg(" SCR: %08x CCR: %08x\n", + getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR)); + lldbg(" SHPR2: %08x SHPR3: %08x\n", + getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); + + irqrestore(flags); +} + +#else +# define lpc11_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: lpc11_nmi, lpc11_busfault, lpc11_usagefault, lpc11_pendsv, + * lpc11_dbgmonitor, lpc11_pendsv, lpc11_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +static int lpc11_nmi(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int lpc11_pendsv(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int lpc11_reserved(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: lpc11_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. + * + ****************************************************************************/ + +static inline void lpc11_clrpend(int irq) +{ + /* This will be called on each interrupt exit whether the interrupt can be + * enambled or not. So this assertion is necessarily lame. + */ + + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for an external interrupt */ + + if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ISER register to enable the + * interrupt + */ + + putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICPR); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int i; + + /* Disable all interrupts */ + + putreg32(0xffffffff, ARMV6M_NVIC_ICER); + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2); + putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3); + + /* Now set all of the interrupt lines to the default priority */ + + for (i = 0; i < 8; i++) + { + regaddr = ARMV6M_NVIC_IPR(i); + putreg32(DEFPRIORITY32, regaddr); + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(LPC11_IRQ_SVCALL, up_svcall); + irq_attach(LPC11_IRQ_HARDFAULT, up_hardfault); + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG + irq_attach(LPC11_IRQ_NMI, lpc11_nmi); + irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv); + irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved); +#endif + + lpc11_dumpnvic("initial", NR_IRQS); + + /* Initialize logic to support a second level of interrupt decoding for + * configured pin interrupts. + */ + +#ifdef CONFIG_GPIO_IRQ + lpc11_gpioirqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + irqenable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for an external interrupt */ + + if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ICER register to disable the + * interrupt + */ + + putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICER); + } + + /* Handle processor exceptions. Only SysTick can be disabled */ + + else if (irq == LPC11_IRQ_SYSTICK) + { + modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0); + } + + lpc11_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + /* This will be called on each interrupt exit whether the interrupt can be + * enabled or not. So this assertion is necessarily lame. + */ + + DEBUGASSERT((unsigned)irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32)) + { + /* Set the appropriate bit in the ISER register to enable the + * interrupt + */ + + putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ISER); + } + + /* Handle processor exceptions. Only SysTick can be disabled */ + + else if (irq == LPC11_IRQ_SYSTICK) + { + modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE); + } + + lpc11_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ + lpc11_clrpend(irq); +} diff --git a/arch/arm/src/lpc11xx/lpc11_lowputc.c b/arch/arm/src/lpc11xx/lpc11_lowputc.c new file mode 100644 index 00000000000..b0818cb3cd6 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_lowputc.c @@ -0,0 +1,355 @@ +/************************************************************************** + * arch/arm/src/lpc11xx/lpc11_lowputc.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/lpc11_syscon.h" +#include "chip/lpc11_uart.h" + +#include "lpc11_gpio.h" +#include "lpc11_lowputc.h" +#include "lpc11_serial.h" + +/************************************************************************** + * Private Definitions + **************************************************************************/ + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC11_UART0_BASE +# define CONSOLE_BAUD CONFIG_UART0_BAUD +# define CONSOLE_BITS CONFIG_UART0_BITS +# define CONSOLE_PARITY CONFIG_UART0_PARITY +# define CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(HAVE_CONSOLE) +# error "No CONFIG_UART0_SERIAL_CONSOLE Setting" +#endif + +/* Get word length setting for the console */ + +#if CONSOLE_BITS == 5 +# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT +#elif CONSOLE_BITS == 6 +# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT +#elif CONSOLE_BITS == 7 +# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT +#elif CONSOLE_BITS == 8 +# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT +#elif defined(HAVE_CONSOLE) +# error "Invalid CONFIG_UARTn_BITS setting for console " +#endif + +/* Get parity setting for the console */ + +#if CONSOLE_PARITY == 0 +# define CONSOLE_LCR_PAR 0 +#elif CONSOLE_PARITY == 1 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD) +#elif CONSOLE_PARITY == 2 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN) +#elif CONSOLE_PARITY == 3 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1) +#elif CONSOLE_PARITY == 4 +# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0) +#elif defined(HAVE_CONSOLE) +# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE" +#endif + +/* Get stop-bit setting for the console and UART0-3 */ + +#if CONSOLE_2STOP != 0 +# define CONSOLE_LCR_STOP UART_LCR_STOP +#else +# define CONSOLE_LCR_STOP 0 +#endif + +/* LCR and FCR values for the console */ + +#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP) +#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\ + UART_FCR_RXRST | UART_FCR_FIFOEN) + +/* Select a CCLK divider to produce the UART PCLK. The strategy is to select the + * smallest divisor that results in an solution within range of the 16-bit + * DLM and DLL divisor: + * + * BAUD = PCLK / (16 * DL), or + * DL = PCLK / BAUD / 16 + * + * The PCLK is determined by the UART-specific divisor: + * + * PCLK = CCLK / divisor + * + * Ignoring the fractional divider for now. (If you want to extend this driver + * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses + * the same peripheral and that logic could easily leveraged here). + */ + +/* Calculate and optimal PCLKSEL0/1 divisor. + * First, check divisor == 1. This works if the upper limit is met: + * + * DL < 0xffff, or + * PCLK / BAUD / 16 < 0xffff, or + * CCLK / BAUD / 16 < 0xffff, or + * CCLK < BAUD * 0xffff * 16 + * BAUD > CCLK / 0xffff / 16 + * + * And the lower limit is met (we can't allow DL to get very close to one). + * + * DL >= MinDL + * CCLK / BAUD / 16 >= MinDL, or + * BAUD <= CCLK / 16 / MinDL + */ + +#if CONSOLE_BAUD < (LPC11_CCLK / 16 / UART_MINDL) +# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK +# define CONSOLE_NUMERATOR (LPC11_CCLK) + +/* Check divisor == 2. This works if: + * + * 2 * CCLK / BAUD / 16 < 0xffff, or + * BAUD > CCLK / 0xffff / 8 + * + * And + * + * 2 * CCLK / BAUD / 16 >= MinDL, or + * BAUD <= CCLK / 8 / MinDL + */ + +#elif CONSOLE_BAUD < (LPC11_CCLK / 8 / UART_MINDL) +# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2 +# define CONSOLE_NUMERATOR (LPC11_CCLK / 2) + +/* Check divisor == 4. This works if: + * + * 4 * CCLK / BAUD / 16 < 0xffff, or + * BAUD > CCLK / 0xffff / 4 + * + * And + * + * 4 * CCLK / BAUD / 16 >= MinDL, or + * BAUD <= CCLK / 4 / MinDL + */ + +#elif CONSOLE_BAUD < (LPC11_CCLK / 4 / UART_MINDL) +# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4 +# define CONSOLE_NUMERATOR (LPC11_CCLK / 4) + +/* Check divisor == 8. This works if: + * + * 8 * CCLK / BAUD / 16 < 0xffff, or + * BAUD > CCLK / 0xffff / 2 + * + * And + * + * 8 * CCLK / BAUD / 16 >= MinDL, or + * BAUD <= CCLK / 2 / MinDL + */ + +#else /* if CONSOLE_BAUD < (LPC11_CCLK / 2 / UART_MINDL) */ +# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8 +# define CONSOLE_NUMERATOR (LPC11_CCLK / 8) +#endif + +/* Then this is the value to use for the DLM and DLL registers */ + +#define CONSOLE_DL (CONSOLE_NUMERATOR / (CONSOLE_BAUD << 4)) + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#if defined HAVE_UART && defined HAVE_CONSOLE + /* Wait for the transmitter to be available */ + + while ((getreg32(CONSOLE_BASE+LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); + + /* Send the character */ + + putreg32((uint32_t)ch, CONSOLE_BASE+LPC11_UART_THR_OFFSET); +#endif +} + +/************************************************************************** + * Name: lpc11_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + * The UART peripheral is configured using the following registers: + * 1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be + * configured in the IOCONFIG register block before the UART clocks can + * be enabled in the SYSAHBCLKCTRL register. For all other parts, no + * special enabling sequence is required. + * 2. Power: In the SYSAHBCLKCTRL register, set bit 12. + * On reset, UART is disabled. + * 3. Peripheral clock: Enable the UART peripheral clock by writing to the + * UARTCLKDIV register. + * + **************************************************************************/ + +void lpc11_lowsetup(void) +{ +#ifdef HAVE_UART + uint32_t regval; + + /* Enable clock for GPIO and I/O block */ + + regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); + regval |= (SYSCON_SYSAHBCLKCTRL_GPIO | SYSCON_SYSAHBCLKCTRL_IOCON); + putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); + + + /* Step 1: Pins configuration */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) + lpc11_configgpio(GPIO_UART0_TXD); + lpc11_configgpio(GPIO_UART0_RXD); +#endif + + /* Step 2: Enable power for all console UART and disable power for + * other UARTs + */ + regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) + regval |= SYSCON_SYSAHBCLKCTRL_UART; +#endif + putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); + + /* Step 3: Enable peripheral clocking for the console UART and disable + * clocking for all other UARTs + */ + + putreg32(1, LPC11_SYSCON_UARTCLKDIV); + + /* Configure Baud rate */ + + + /* Configure the console (only) */ + +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + + /* Clear fifos */ + + putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC11_UART_FCR_OFFSET); + + /* Set trigger */ + + putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC11_UART_FCR_OFFSET); + + /* Set up the LCR and set DLAB=1 */ + + putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC11_UART_LCR_OFFSET); + + /* Set the BAUD divisor */ + + //putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC11_UART_DLM_OFFSET); + //putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC11_UART_DLL_OFFSET); + + regval = getreg32(LPC11_UART0_LCR); + regval |= UART_LCR_DLAB; + putreg32(regval, LPC11_UART0_LCR); + + putreg32((1 << UART_FDR_MULVAL_SHIFT), LPC11_UART0_FDR); + + putreg32(56, LPC11_UART0_DLL); + + putreg32(1, LPC11_UART0_DLM); + + regval = getreg32(LPC11_UART0_LCR); + regval &= ~UART_LCR_DLAB; + putreg32(regval, LPC11_UART0_LCR); + + regval = getreg32(LPC11_UART0_LCR); + regval |= UART_LCR_WLS_8BIT; + putreg32(regval, LPC11_UART0_LCR); + + /* Clear DLAB */ + + //putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC11_UART_LCR_OFFSET); + + /* Configure the FIFOs */ + + putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN, + CONSOLE_BASE+LPC11_UART_FCR_OFFSET); +#endif +#endif /* HAVE_UART */ +} diff --git a/arch/arm/src/lpc11xx/lpc11_lowputc.h b/arch/arm/src/lpc11xx/lpc11_lowputc.h new file mode 100644 index 00000000000..9bf68ec1151 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_lowputc.h @@ -0,0 +1,84 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_lowputc.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART done early so that the serial + * console is available for debugging very early in the boot sequence. + * + ************************************************************************************/ + +void lpc11_lowsetup(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c new file mode 100644 index 00000000000..b8b6a3f05e4 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_serial.c @@ -0,0 +1,1042 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_serial.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip.h" +#include "chip/lpc11_uart.h" +#include "lpc11_gpio.h" +#include "lpc11_serial.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(USE_SERIALDRIVER) && defined(HAVE_UART) + +/* Configuration ************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t ier; /* Saved IER value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ +#ifdef LPC111x + uint8_t cclkdiv; /* Divisor needed to get PCLK from CCLK */ +#endif + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_LPC11_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +/* This describes the state of the LPC11xx uart0 port. */ + +#ifdef CONFIG_LPC11_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = LPC11_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = LPC11_IRQ_UART, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* Which UART with be tty0/console and which tty1? tty2? tty3? */ + +#ifdef HAVE_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0=console */ +# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ +# endif +#else /* No console */ +# define TTYS0_DEV g_uart0port /* UART0=ttyS0 */ +#endif /*HAVE_CONSOLE*/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *ier) +{ + if (ier) + { + *ier = priv->ier & UART_IER_ALLIE; + } + + priv->ier &= ~UART_IER_ALLIE; + up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t ier) +{ + priv->ier |= ier & UART_IER_ALLIE; + up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_enablebreaks + ****************************************************************************/ + +static inline void up_enablebreaks(struct up_dev_s *priv, bool enable) +{ + uint32_t lcr = up_serialin(priv, LPC11_UART_LCR_OFFSET); + + if (enable) + { + lcr |= UART_LCR_BRK; + } + else + { + lcr &= ~UART_LCR_BRK; + } + + up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); +} + +/************************************************************************************ + * Name: lpc11_uartcclkdiv + * + * Description: + * Select a CCLK divider to produce the UART PCLK. The strategy is to select the + * smallest divisor that results in an solution within range of the 16-bit + * DLM and DLL divisor: + * + * PCLK = MCLK / divisor + * BAUD = PCLK / (16 * DL) + * + * Ignoring the fractional divider for now. (If you want to extend this driver + * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses + * the same peripheral and that logic could easily leveraged here). + * + * For the LPC111x the PCLK is determined by the UART-specific divisor in + * PCLKSEL0 or PCLKSEL1: + * + * PCLK = MCLK / divisor + * + * For the LPC111x, the PCLK is determined by the global divisor setting in + * the PLKSEL register (and, in that case, this function is not needed). + * + * NOTE: This is an inline function. If a typical optimization level is used and + * a constant is provided for the desired frequency, then most of the following + * logic will be optimized away. + * + ************************************************************************************/ + +#ifdef LPC111x +static inline uint32_t lpc11_uartcclkdiv(uint32_t baud) +{ + /* Ignoring the fractional divider, the BAUD is given by: + * + * BAUD = PCLK / (16 * DL), or + * DL = PCLK / BAUD / 16 + * + * Where for the LPC111x the PCLK is determined by the UART-specific divisor in + * : + * + * UART_PCLK = MAIN_CLOCK / divisor + * + */ + + /* Calculate and optimal PCLKSEL0/1 divisor. + * First, check divisor == 1. This works if the upper limit is met: + * + * DL < 0xffff, or + * PCLK / BAUD / 16 < 0xffff, or + * MCLK / BAUD / 16 < 0xffff, or + * MCLK < BAUD * 0xffff * 16 + * BAUD > MCLK / 0xffff / 16 + * + * And the lower limit is met (we can't allow DL to get very close to one). + * + * DL >= MinDL + * MCLK / BAUD / 16 >= MinDL, or + * BAUD <= CCLK / 16 / MinDL + */ + + return 1; +} +#endif /* LPC111x */ + +/************************************************************************************ + * Name: lpc11_uart0config + * + * Description: + * Configure the UART. UART0 peripherals are configured using the following + * registers: + * + * 1. Power: In the PCONP register, set bits PCUART0. + * On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1) + * and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0). + * 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and + * PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3. + * 3. Pins: Select UART pins through the PINSEL registers and pin modes + * through the PINMODE registers. UART receive pins should not have + * pull-down resistors enabled. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC11_UART0 +static inline void lpc11_uart0config(void) +{ + uint32_t regval; + irqstate_t flags; + + /* Step 1: Pins configuration */ + + flags = irqsave(); + lpc11_configgpio(GPIO_UART0_TXD); + lpc11_configgpio(GPIO_UART0_RXD); + + /* Step 2: Enable power on UART0 */ + + regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL); + regval |= SYSCON_SYSAHBCLKCTRL_UART; + putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL); + + /* Step 3: Enable clocking UART */ + + putreg32(1, LPC11_SYSCON_UARTCLKDIV); + irqrestore(flags); +}; +#endif + +/************************************************************************************ + * Name: lpc11_uartdl + * + * Descrption: + * Select a divider to produce the BAUD from the UART PCLK. + * + * BAUD = PCLK / (16 * DL), or + * DL = PCLK / BAUD / 16 + * + * Ignoring the fractional divider for now. (If you want to extend this driver + * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses + * the same peripheral and that logic could easily leveraged here). + * + ************************************************************************************/ + +#ifdef LPC111x +static inline uint32_t lpc11_uartdl(uint32_t baud, uint8_t divcode) +{ + + /*TODO: Calculate DL automatically */ + uint32_t num = 312; + + return num; +} +#else +static inline uint32_t lpc11_uartdl(uint32_t baud) +{ + return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4); +} +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This method is + * called the first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint16_t dl; + uint32_t lcr; + + /* Clear fifos */ + + up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST)); + + /* Set trigger */ + + up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8)); + + /* Set up the IER */ + + priv->ier = up_serialin(priv, LPC11_UART_IER_OFFSET); + + /* Set up the LCR */ + + lcr = 0; + + if (priv->bits == 7) + { + lcr |= UART_LCR_WLS_7BIT; + } + else + { + lcr |= UART_LCR_WLS_8BIT; + } + + if (priv->stopbits2) + { + lcr |= UART_LCR_STOP; + } + + if (priv->parity == 1) + { + lcr |= (UART_LCR_PE|UART_LCR_PS_ODD); + } + else if (priv->parity == 2) + { + lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN); + } + + /* Enter DLAB=1 */ + + up_serialout(priv, LPC11_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + + /* Set the BAUD divisor */ + +#ifdef LPC111x + dl = lpc11_uartdl(priv->baud, priv->cclkdiv); +#else + dl = lpc11_uartdl(priv->baud); +#endif + up_serialout(priv, LPC11_UART_DLM_OFFSET, dl >> 8); + up_serialout(priv, LPC11_UART_DLL_OFFSET, dl & 0xff); + + /* Clear DLAB */ + + up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); + + /* Configure the FIFOs */ + + up_serialout(priv, LPC11_UART_FCR_OFFSET, + (UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN)); + +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, up_interrupt); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + uint32_t status; + int passes; + +#ifdef CONFIG_LPC11_UART0 + if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else +#endif + { + PANIC(); + } + + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + for (passes = 0; passes < 256; passes++) + { + /* Get the current UART status and check for loop + * termination conditions + */ + + status = up_serialin(priv, LPC11_UART_IIR_OFFSET); + + /* The UART_IIR_INTSTATUS bit should be zero if there are pending + * interrupts + */ + + if ((status & UART_IIR_INTSTATUS) != 0) + { + /* Break out of the loop when there is no longer a + * pending interrupt + */ + + break; + } + + /* Handle the interrupt by its interrupt ID field */ + + switch (status & UART_IIR_INTID_MASK) + { + /* Handle incoming, receive bytes (with or without timeout) */ + + case UART_IIR_INTID_RDA: + case UART_IIR_INTID_CTI: + { + uart_recvchars(dev); + break; + } + + /* Handle outgoing, transmit bytes */ + + case UART_IIR_INTID_THRE: + { + uart_xmitchars(dev); + break; + } + + /* Just clear any line status interrupts */ + + case UART_IIR_INTID_RLS: + { + /* Read the line status register (LSR) to clear */ + + status = up_serialin(priv, LPC11_UART_LSR_OFFSET); + vdbg("LSR: %02x\n", status); + break; + } + + /* There should be no other values */ + + default: + { + dbg("Unexpected IIR: %02x\n", status); + break; + } + } + } + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags = irqsave(); + up_enablebreaks(priv, true); + irqrestore(flags); + } + break; + + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; + flags = irqsave(); + up_enablebreaks(priv, false); + irqrestore(flags); + } + break; + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios*)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Other termios fields are not yet returned. + * Note that cfsetospeed is not necessary because we have + * knowledge that only one speed is supported. + * Both cfset(i|o)speed() translate to cfsetspeed. + */ + + cfsetispeed(termiosp, priv->baud); + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios*)arg; + uint32_t lcr; /* Holds current values of line control register */ + uint16_t dl; /* Divisor latch */ + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Handle other termios settings. + * Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ + + /* Get the c_speed field in the termios struct */ + + priv->baud = cfgetispeed(termiosp); + + /* TODO: Re-calculate the optimal CCLK divisor for the new baud and + * and reset the divider in the CLKSEL0/1 register. + */ + +#ifdef LPC111x + priv->cclkdiv = lpc11_uartcclkdiv(priv->baud); +#endif + /* DLAB open latch */ + /* REVISIT: Shouldn't we just call up_setup() to do all of the following? */ + + lcr = getreg32(priv->uartbase + LPC11_UART_LCR_OFFSET); + up_serialout(priv, LPC11_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB)); + + /* Set the BAUD divisor */ + +#ifdef LPC111x + dl = lpc11_uartdl(priv->baud, priv->cclkdiv); +#else + dl = lpc11_uartdl(priv->baud); +#endif + up_serialout(priv, LPC11_UART_DLM_OFFSET, dl >> 8); + up_serialout(priv, LPC11_UART_DLL_OFFSET, dl & 0xff); + + /* Clear DLAB */ + + up_serialout(priv, LPC11_UART_LCR_OFFSET, lcr); + } + break; +#endif + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + uint32_t rbr; + + *status = up_serialin(priv, LPC11_UART_LSR_OFFSET); + rbr = up_serialin(priv, LPC11_UART_RBR_OFFSET); + return rbr; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_RBRIE; +#endif + } + else + { + priv->ier &= ~UART_IER_RBRIE; + } + + up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_RDR) != 0); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + up_serialout(priv, LPC11_UART_THR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ier |= UART_IER_THREIE; + up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + priv->ier &= ~UART_IER_THREIE; + up_serialout(priv, LPC11_UART_IER_OFFSET, priv->ier); + } + + irqrestore(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the transmit fifo is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s*)dev->priv; + return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0); +} + +/**************************************************************************** + * Public Funtions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + * NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup() + * very early in the boot sequence. + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ + +#ifdef CONFIG_LPC11_UART0 +#ifdef LPC111x + g_uart0priv.cclkdiv = lpc11_uartcclkdiv(CONFIG_UART0_BAUD); +#endif +#ifndef CONFIG_UART0_SERIAL_CONSOLE + lpc11_uart0config(); +#endif + up_disableuartint(&g_uart0priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef CONSOLE_DEV + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv; + uint32_t ier; + up_disableuartint(priv, &ier); +#endif + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#ifdef HAVE_CONSOLE + up_restoreuartint(priv, ier); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/lpc11xx/lpc11_serial.h b/arch/arm/src/lpc11xx/lpc11_serial.h new file mode 100644 index 00000000000..11b4fd19897 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_serial.h @@ -0,0 +1,98 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_serial.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip/lpc11_uart.h" +#include "chip/lpc11_syscon.h" + +#include "lpc11_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_LPC11_UART0) +# define HAVE_UART 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC11_UART0) +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* We cannot allow the DLM/DLL divisor to become to small or will will lose too + * much accuracy. This following is a "fudge factor" that represents the minimum + * value of the divisor that we will permit. + */ + +#define UART_MINDL 32 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c new file mode 100644 index 00000000000..f9ef42812e0 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_spi.c @@ -0,0 +1,623 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_spi.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "chip/lpc11_syscon.h" +#include "lpc11_gpio.h" +#include "lpc11_spi.h" + +#ifdef CONFIG_LPC11_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* This driver does not support the SPI exchange method. */ + +#ifdef CONFIG_SPI_EXCHANGE +# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration" +#endif + +/* Debug ********************************************************************/ +/* The following enable debug output from this file: + * + * CONFIG_DEBUG - Define to enable general debug features + * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG) + * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug + */ + +#ifdef CONFIG_DEBUG_SPI +# define spidbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# define spidbg(x...) +# define spivdbg(x...) +#endif + +/* SSP Clocking *************************************************************/ +/* The CPU clock by 1, 2, 4, or 8 to get the SPI peripheral clock (SPI_CLOCK). + * SPI_CLOCK may be further divided by 8-254 to get the SPI clock. If we + * want a usable range of 4KHz to 25MHz for the SPI, then: + * + * 1. SPICLK must be greater than (8*25MHz) = 200MHz (so we can't reach 25MHz), + * and + * 2. SPICLK must be less than (254*40Khz) = 101.6MHz. + * + * If we assume that CCLK less than or equal to 100MHz, we can just + * use the CCLK undivided to get the SPI_CLOCK. + */ + +#define SPI_PCLKSET_DIV SYSCON_PCLKSEL_CCLK +#define SPI_CLOCK LPC11_CCLK + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of the SSP driver */ + +struct lpc11_spidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode); +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch); +static void spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spiops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = lpc11_spiselect, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, + .status = lpc11_spistatus, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lpc11_spicmddata, +#endif + .send = spi_send, + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#ifdef CONFIG_SPI_CALLBACK + .registercallback = lpc11_spiregister, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +static struct lpc11_spidev_s g_spidev = +{ + .spidev = { &g_spiops }, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait + * was awakened by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) +{ + FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; + uint32_t divisor; + uint32_t actual; + + /* Check if the requested frequence is the same as the frequency selection */ + + DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); +#ifndef CONFIG_SPI_OWNBUS + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } +#endif + + /* frequency = SPI_CLOCK / divisor, or divisor = SPI_CLOCK / frequency */ + + divisor = SPI_CLOCK / frequency; + + /* The SPI CCR register must contain an even number greater than or equal + * to 8. + */ + + if (divisor < 8) + { + divisor = 8; + } + else if (divisor > 254) + { + divisor = 254; + } + + divisor = (divisor + 1) & ~1; + + /* Save the new divisor value */ + + putreg32(divisor, LPC11_SPI_CCR); + + /* Calculate the new actual */ + + actual = SPI_CLOCK / divisor; + + /* Save the frequency setting */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; +#endif + + spidbg("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/**************************************************************************** + * Name: spi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; + uint32_t regval; + + /* Has the mode changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Yes... Set CR appropriately */ + + regval = getreg32(LPC11_SPI_CR); + regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + regval |= SPI_CR_CPHA; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + regval |= SPI_CR_CPOL; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + regval |= (SPI_CR_CPOL|SPI_CR_CPHA); + break; + + default: + DEBUGASSERT(FALSE); + return; + } + + putreg32(regval, LPC11_SPI_CR); + + /* Save the mode so that subsequent re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +/**************************************************************************** + * Name: spi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + FAR struct lpc11_spidev_s *priv = (FAR struct lpc11_spidev_s *)dev; + uint32_t regval; + + /* Has the number of bits changed? */ + + DEBUGASSERT(priv && nbits > 7 && nbits < 17); +#ifndef CONFIG_SPI_OWNBUS + if (nbits != priv->nbits) + { +#endif + /* Yes... Set CR appropriately */ + + regval = getreg32(LPC11_SPI_CR); + regval &= ~SPI_CR_BITS_MASK; + regval |= (nbits << SPI_CR_BITS_SHIFT) & SPI_CR_BITS_MASK; + regval |= SPI_CR_BITENABLE; + regval = getreg32(LPC11_SPI_CR); + + /* Save the selection so the subsequence re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->nbits = nbits; + } +#endif +} + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + /* Write the data to transmitted to the SPI Data Register */ + + putreg32((uint32_t)wd, LPC11_SPI_DR); + + /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The + * SPIF bit will be set after the last sampling clock edge of the SPI + * data transfer. + */ + + while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); + + /* Read the SPI Status Register again to clear the status bit */ + + (void)getreg32(LPC11_SPI_SR); + return (uint16_t)getreg32(LPC11_SPI_DR); +} + +/************************************************************************* + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords) +{ + FAR uint8_t *ptr = (FAR uint8_t*)buffer; + uint8_t data; + + spidbg("nwords: %d\n", nwords); + while (nwords) + { + /* Write the data to transmitted to the SPI Data Register */ + + data = *ptr++; + putreg32((uint32_t)data, LPC11_SPI_DR); + + /* Wait for the SPIF bit in the SPI Status Register to be set to 1. + * The SPIF bit will be set after the last sampling clock edge of + * the SPI data transfer. + */ + + while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); + + /* Read the SPI Status Register again to clear the status bit */ + + (void)getreg32(LPC11_SPI_SR); + nwords--; + } +} + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords) +{ + FAR uint8_t *ptr = (FAR uint8_t*)buffer; + + spidbg("nwords: %d\n", nwords); + while (nwords) + { + /* Write some dummy data to the SPI Data Register in order to clock the + * read data. + */ + + putreg32(0xff, LPC11_SPI_DR); + + /* Wait for the SPIF bit in the SPI Status Register to be set to 1. The + * SPIF bit will be set after the last sampling clock edge of the SPI + * data transfer. + */ + + while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0); + + /* Read the SPI Status Register again to clear the status bit */ + + (void)getreg32(LPC11_SPI_SR); + + /* Read the received data from the SPI Data Register */ + + *ptr++ = (uint8_t)getreg32(LPC11_SPI_DR); + nwords--; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_spiinitialize + * + * Description: + * Initialize the selected SPI port. + * + * Input Parameter: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *lpc11_spiinitialize(int port) +{ + FAR struct lpc11_spidev_s *priv = &g_spidev; + irqstate_t flags; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select + * pins must be configured by board-specific logic. All SPI pins and + * one SPI1 pin (SCK) have multiple, alternative pin selection. + * Definitions in the board.h file must be provided to resolve the + * board-specific pin configuration like: + * + * #define GPIO_SPI_SCK GPIO_SPI_SCK_1 + */ + + flags = irqsave(); + lpc11_configgpio(GPIO_SPI_SCK); + lpc11_configgpio(GPIO_SPI_MISO); + lpc11_configgpio(GPIO_SPI_MOSI); + + /* Configure clocking */ + + regval = getreg32(LPC11_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_SPI_MASK; + regval |= (SPI_PCLKSET_DIV << SYSCON_PCLKSEL0_SPI_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL0); + + /* Enable peripheral clocking to SPI and SPI1 */ + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCSPI; + putreg32(regval, LPC11_SYSCON_PCONP); + irqrestore(flags); + + /* Configure 8-bit SPI mode and master mode */ + + putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC11_SPI_CR); + + /* Set the initial SPI configuration */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = 0; + priv->nbits = 8; + priv->mode = SPIDEV_MODE0; +#endif + + /* Select a default frequency of approx. 400KHz */ + + spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); + + /* Initialize the SPI semaphore that enforces mutually exclusive access */ + +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + return &priv->spidev; +} + +#endif /* CONFIG_LPC11_SPI */ diff --git a/arch/arm/src/lpc11xx/lpc11_spi.h b/arch/arm/src/lpc11xx/lpc11_spi.h new file mode 100644 index 00000000000..572bffd64e7 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_spi.h @@ -0,0 +1,170 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_spi.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip/lpc11_spi.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifdef CONFIG_LPC11_SPI + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_spiinitialize + * + * Description: + * Initialize the selected SPI port. + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ************************************************************************************/ + +FAR struct spi_dev_s *lpc11_spiinitialize(int port); + +/************************************************************************************ + * Name: lpc11_spiselect, lpc11_status, and lpc11_spicmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including lpc11_spiinitialize()) are provided by common LPC11xx logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in lpc11_boardinitialize() to configure SPI chip select pins. + * 2. Provide lpc11_spiselect() and lpc11_spistatus() functions in your board- + * specific logic. These functions will perform chip selection and status + * operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * lpc11_spicmddata() functions in your board-specific logic. This function + * will perform cmd/data selection operations using GPIOs in the way your + * board is configured. + * 3. Add a call to lpc11_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by lpc11_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SPI driver to the SPI MMC/SD driver). + * + ************************************************************************************/ + +void lpc11_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc11_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc11_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif + +/************************************************************************************ + * Name: spi_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spiselect after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ************************************************************************************/ + +void spi_flush(FAR struct spi_dev_s *dev); + +/************************************************************************************ + * Name: lpc11_spiregister + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD drvier when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function must + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +int lpc11_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC11_SPI */ +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.c b/arch/arm/src/lpc11xx/lpc11_ssp.c new file mode 100644 index 00000000000..cae1db66307 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_ssp.c @@ -0,0 +1,1093 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_ssp.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "chip/lpc11_syscon.h" +#include "lpc11_gpio.h" +#include "lpc11_ssp.h" + +#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) || \ + defined(CONFIG_LPC11_SSP2) + +/**************************************************************************** + * Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* This driver does not support the SPI exchange method. */ + +#ifdef CONFIG_SPI_EXCHANGE +# error "CONFIG_SPI_EXCHANGE must not be defined in the configuration" +#endif + +/* Debug ********************************************************************/ +/* The following enable debug output from this file: + * + * CONFIG_DEBUG - Define to enable general debug features + * CONFIG_DEBUG_SPI - Define to enable basic SSP debug (needs CONFIG_DEBUG) + * CONFIG_DEBUG_VERBOSE - Define to enable verbose SSP debug + */ + +#ifdef CONFIG_DEBUG_SPI +# define sspdbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# define sspdbg(x...) +# define spivdbg(x...) +#endif + +/* SSP Clocking *************************************************************/ + +#if defined(LPC111x) +/* The CPU clock by 1, 2, 4, or 8 to get the SSP peripheral clock (SSP_CLOCK). + * SSP_CLOCK may be further divided by 2-254 to get the SSP clock. If we + * want a usable range of 4KHz to 25MHz for the SSP, then: + * + * 1. SSPCLK must be greater than (2*25MHz) = 50MHz, and + * 2. SSPCLK must be less than (254*40Khz) = 101.6MHz. + * + * If we assume that CCLK less than or equal to 100MHz, we can just + * use the CCLK undivided to get the SSP_CLOCK. + */ + +# if LPC11_CCLK > 100000000 +# error "CCLK <= 100,000,000 assumed" +# endif + +# define SSP_PCLKSET_DIV SYSCON_PCLKSEL_CCLK +# define SSP_CLOCK LPC11_CCLK + +#elif defined(LPC111x) +/* All peripherals are clocked by the same peripheral clock in the LPC111x + * family. + */ + +# define SSP_CLOCK BOARD_PCLK_FREQUENCY + +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure descibes the state of the SSP driver */ + +struct lpc11_sspdev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t sspbase; /* SPIn base address */ +#ifdef CONFIG_LPC11_SSP_INTERRUPTS + uint8_t sspirq; /* SPI IRQ number */ +#endif +#ifndef CONFIG_SPI_OWNBUS + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t nbits; /* Width of word in bits (4 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint32_t ssp_getreg(FAR struct lpc11_sspdev_s *priv, + uint8_t offset); +static inline void ssp_putreg(FAR struct lpc11_sspdev_s *priv, + uint8_t offset, uint32_t value); + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int ssp_lock(FAR struct spi_dev_s *dev, bool lock); +#endif +static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void ssp_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode); +static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t ch); +static void ssp_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords); +static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords); + +/* Initialization */ + +#ifdef CONFIG_LPC11_SSP0 +static inline FAR struct lpc11_sspdev_s *lpc11_ssp0initialize(void); +#endif +#ifdef CONFIG_LPC11_SSP1 +static inline FAR struct lpc11_sspdev_s *lpc11_ssp1initialize(void); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_LPC11_SSP0 +static const struct spi_ops_s g_spi0ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssp_lock, +#endif + .select = lpc11_ssp0select, /* Provided externally */ + .setfrequency = ssp_setfrequency, + .setmode = ssp_setmode, + .setbits = ssp_setbits, + .status = lpc11_ssp0status, /* Provided externally */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lpc11_ssp0cmddata, /* Provided externally */ +#endif + .send = ssp_send, + .sndblock = ssp_sndblock, + .recvblock = ssp_recvblock, +#ifdef CONFIG_SPI_CALLBACK + .registercallback = lpc11_ssp0register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +static struct lpc11_sspdev_s g_ssp0dev = +{ + .spidev = { &g_spi0ops }, + .sspbase = LPC11_SSP0_BASE, +#ifdef CONFIG_LPC11_SSP_INTERRUPTS + .sspirq = LPC11_IRQ_SSP0, +#endif +}; +#endif /* CONFIG_LPC11_SSP0 */ + +#ifdef CONFIG_LPC11_SSP1 +static const struct spi_ops_s g_spi1ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssp_lock, +#endif + .select = lpc11_ssp1select, /* Provided externally */ + .setfrequency = ssp_setfrequency, + .setmode = ssp_setmode, + .setbits = ssp_setbits, + .status = lpc11_ssp1status, /* Provided externally */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lpc11_ssp1cmddata, /* Provided externally */ +#endif + .send = ssp_send, + .sndblock = ssp_sndblock, + .recvblock = ssp_recvblock, +#ifdef CONFIG_SPI_CALLBACK + .registercallback = lpc11_ssp1register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +static struct lpc11_sspdev_s g_ssp1dev = +{ + .spidev = { &g_spi1ops }, + .sspbase = LPC11_SSP1_BASE, +#ifdef CONFIG_LPC11_SSP_INTERRUPTS + .sspirq = LPC11_IRQ_SSP1, +#endif +}; +#endif /* CONFIG_LPC11_SSP1 */ + +#ifdef CONFIG_LPC11_SSP2 +static const struct spi_ops_s g_spi2ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = ssp_lock, +#endif + .select = lpc11_ssp2select, /* Provided externally */ + .setfrequency = ssp_setfrequency, + .setmode = ssp_setmode, + .setbits = ssp_setbits, + .status = lpc11_ssp2status, /* Provided externally */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lpc11_ssp2cmddata, /* Provided externally */ +#endif + .send = ssp_send, + .sndblock = ssp_sndblock, + .recvblock = ssp_recvblock, +#ifdef CONFIG_SPI_CALLBACK + .registercallback = lpc11_ssp2register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +static struct lpc11_sspdev_s g_ssp2dev = +{ + .spidev = { &g_spi2ops }, + .sspbase = LPC11_SSP2_BASE, +#ifdef CONFIG_LPC11_SSP_INTERRUPTS + .sspirq = LPC11_IRQ_SSP2, +#endif +}; +#endif /* CONFIG_LPC11_SSP2 */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ssp_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline uint32_t ssp_getreg(FAR struct lpc11_sspdev_s *priv, + uint8_t offset) +{ + return getreg32(priv->sspbase + (uint32_t)offset); +} + +/**************************************************************************** + * Name: ssp_putreg + * + * Description: + * Write a 32-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * None + * + ***************************************************************************/ + +static inline void ssp_putreg(FAR struct lpc11_sspdev_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->sspbase + (uint32_t)offset); +} + +/**************************************************************************** + * Name: ssp_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int ssp_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait + * was awakened by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + return OK; +} +#endif + +/**************************************************************************** + * Name: ssp_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + uint32_t cpsdvsr; + uint32_t scr; + uint32_t regval; + uint32_t actual; + + /* Check if the requested frequency is the same as the frequency selection */ + + DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2); +#ifndef CONFIG_SPI_OWNBUS + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } +#endif + + /* The SSP bit frequency is given by: + * + * frequency = SSP_CLOCK / (CPSDVSR * (SCR+1)). + * + * Let's try for a solution with the smallest value of SCR. NOTES: + * (1) In the calculations below, the value of the variable 'scr' is + * (SCR+1) in the above equation. (2) On slower LPC11xx parts, SCR + * will probably always be zero. + */ + + for (scr = 1; scr <= 256; scr++) + { + /* CPSDVSR = SSP_CLOCK / (SCR + 1) / frequency */ + + cpsdvsr = SSP_CLOCK / (scr * frequency); + + /* Break out on the first solution we find with the smallest value + * of SCR and with CPSDVSR within the maximum range or 254. + */ + + if (cpsdvsr < 255) + { + break; + } + } + + DEBUGASSERT(scr <= 256 && cpsdvsr <= 255); + + /* "In master mode, CPSDVSRmin = 2 or larger (even numbers only)" */ + + if (cpsdvsr < 2) + { + /* Clip to the minimum value. */ + + cpsdvsr = 2; + } + else if (cpsdvsr > 254) + { + /* This should never happen */ + + cpsdvsr = 254; + } + + /* Force even */ + + cpsdvsr = (cpsdvsr + 1) & ~1; + + /* Save the new CPSDVSR and SCR values */ + + ssp_putreg(priv, LPC11_SSP_CPSR_OFFSET, cpsdvsr); + + regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); + regval &= ~SSP_CR0_SCR_MASK; + regval |= ((scr - 1) << SSP_CR0_SCR_SHIFT); + ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); + + /* Calculate the new actual */ + + actual = SSP_CLOCK / (cpsdvsr * scr); + + /* Save the frequency setting */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; +#endif + + sspdbg("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/**************************************************************************** + * Name: ssp_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + uint32_t regval; + + /* Has the mode changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Yes... Set CR0 appropriately */ + + regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); + regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + regval |= SSP_CR0_CPHA; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + regval |= SSP_CR0_CPOL; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA); + break; + + default: + sspdbg("Bad mode: %d\n", mode); + DEBUGASSERT(FALSE); + return; + } + + ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); + + /* Save the mode so that subsequent re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +/**************************************************************************** + * Name: ssp_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + uint32_t regval; + + /* Has the number of bits changed? */ + + DEBUGASSERT(priv && nbits > 3 && nbits < 17); +#ifndef CONFIG_SPI_OWNBUS + if (nbits != priv->nbits) + { +#endif + /* Yes... Set CR1 appropriately */ + + regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET); + regval &= ~SSP_CR0_DSS_MASK; + regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT); + ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, regval); + + /* Save the selection so the subsequence re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->nbits = nbits; + } +#endif +} + +/**************************************************************************** + * Name: ssp_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + register uint32_t regval; + + /* Wait while the TX FIFO is full */ + + while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF)); + + /* Write the byte to the TX FIFO */ + + ssp_putreg(priv, LPC11_SSP_DR_OFFSET, (uint32_t)wd); + + /* Wait for the RX FIFO not empty */ + + while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)); + + /* Get the value from the RX FIFO and return it */ + + regval = ssp_getreg(priv, LPC11_SSP_DR_OFFSET); + sspdbg("%04x->%04x\n", wd, regval); + return (uint16_t)regval; +} + +/************************************************************************* + * Name: ssp_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, + size_t nwords) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + union + { + FAR const uint8_t *p8; + FAR const uint16_t *p16; + FAR const void *pv; + } u; + uint32_t data; + uint32_t sr; + + /* Loop while thre are bytes remaining to be sent */ + + sspdbg("nwords: %d\n", nwords); + u.pv = buffer; + while (nwords > 0) + { + /* While the TX FIFO is not full and there are bytes left to send */ + + while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) && nwords) + { + /* Fetch the data to send */ + + if (priv->nbits > 8) + { + data = (uint32_t)*u.p16++; + } + else + { + data = (uint32_t)*u.p8++; + } + + /* Send the data */ + + ssp_putreg(priv, LPC11_SSP_DR_OFFSET, data); + nwords--; + } + } + + /* Then discard all card responses until the RX & TX FIFOs are emptied. */ + + sspdbg("discarding\n"); + do + { + /* Is there anything in the RX fifo? */ + + sr = ssp_getreg(priv, LPC11_SSP_SR_OFFSET); + if ((sr & SSP_SR_RNE) != 0) + { + /* Yes.. Read and discard */ + + (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); + } + + /* There is a race condition where TFE may go true just before + * RNE goes true and this loop terminates prematurely. The nasty + * little delay in the following solves that (it could probably be + * tuned to improve performance). + */ + + else if ((sr & SSP_SR_TFE) != 0) + { + up_udelay(100); + sr = ssp_getreg(priv, LPC11_SSP_SR_OFFSET); + } + } + while ((sr & SSP_SR_RNE) != 0 || (sr & SSP_SR_TFE) == 0); +} + +/**************************************************************************** + * Name: ssp_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + union + { + FAR uint8_t *p8; + FAR uint16_t *p16; + FAR void *pv; + } u; + uint32_t data; + uint32_t rxpending = 0; + + /* While there is remaining to be sent (and no synchronization error has + * occurred). + */ + + sspdbg("nwords: %d\n", nwords); + u.pv = buffer; + while (nwords || rxpending) + { + /* Fill the transmit FIFO with 0xffff... + * Write 0xff to the data register while (1) the TX FIFO is + * not full, (2) we have not exceeded the depth of the TX FIFO, + * and (3) there are more bytes to be sent. + */ + + spivdbg("TX: rxpending: %d nwords: %d\n", rxpending, nwords); + while ((ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF) && + (rxpending < LPC11_SSP_FIFOSZ) && nwords) + { + ssp_putreg(priv, LPC11_SSP_DR_OFFSET, 0xffff); + nwords--; + rxpending++; + } + + /* Now, read the RX data from the RX FIFO while the RX FIFO is not + * empty. + */ + + spivdbg("RX: rxpending: %d\n", rxpending); + while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE) + { + data = (uint8_t)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); + if (priv->nbits > 8) + { + *u.p16++ = (uint16_t)data; + } + else + { + *u.p8++ = (uint8_t)data; + } + rxpending--; + } + } +} + +/**************************************************************************** + * Name: lpc11_ssp0initialize + * + * Description: + * Initialize the SSP0 + * + * Input Parameter: + * None + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC11_SSP0 +static inline FAR struct lpc11_sspdev_s *lpc11_ssp0initialize(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select + * pins must be configured by board-specific logic. All SSP0 pins and + * one SSP1 pin (SCK) have multiple, alternative pin selection. + * Definitions in the board.h file must be provided to resolve the + * board-specific pin configuration like: + * + * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 + */ + + flags = irqsave(); + lpc11_configgpio(GPIO_SSP0_SCK); + lpc11_configgpio(GPIO_SSP0_MISO); + lpc11_configgpio(GPIO_SSP0_MOSI); + + /* Configure clocking */ + +#ifdef LPC111x + regval = getreg32(LPC11_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_SSP0_MASK; + regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL1_SSP0_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL1); +#endif + + /* Enable peripheral clocking to SSP0 */ + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCSSP0; + putreg32(regval, LPC11_SYSCON_PCONP); + irqrestore(flags); + + return &g_ssp0dev; +} +#endif + +/**************************************************************************** + * Name: lpc11_ssp1initialize + * + * Description: + * Initialize the SSP1 + * + * Input Parameter: + * None + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC11_SSP1 +static inline FAR struct lpc11_sspdev_s *lpc11_ssp1initialize(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select + * pins must be configured by board-specific logic. All SSP0 pins and + * one SSP1 pin (SCK) have multiple, alternative pin selection. + * Definitions in the board.h file must be provided to resolve the + * board-specific pin configuration like: + * + * #define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 + */ + + flags = irqsave(); + lpc11_configgpio(GPIO_SSP1_SCK); + lpc11_configgpio(GPIO_SSP1_MISO); + lpc11_configgpio(GPIO_SSP1_MOSI); + + /* Configure clocking */ + +#ifdef LPC111x + regval = getreg32(LPC11_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_SSP1_MASK; + regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP1_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL0); +#endif + + /* Enable peripheral clocking to SSP0 and SSP1 */ + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCSSP1; + putreg32(regval, LPC11_SYSCON_PCONP); + irqrestore(flags); + + return &g_ssp1dev; +} +#endif + +/**************************************************************************** + * Name: lpc11_ssp2initialize + * + * Description: + * Initialize the SSP2 + * + * Input Parameter: + * None + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC11_SSP2 +static inline FAR struct lpc11_sspdev_s *lpc11_ssp2initialize(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Configure multiplexed pins as connected on the board. Chip select + * pins must be configured by board-specific logic. All SSP2 pins have + * multiple, alternative pin selection. Definitions in the board.h file + * must be provided to resolve the board-specific pin configuration like: + * + * #define GPIO_SSP2_SCK GPIO_SSP2_SCK_1 + */ + + flags = irqsave(); + lpc11_configgpio(GPIO_SSP2_SCK); + lpc11_configgpio(GPIO_SSP2_MISO); + lpc11_configgpio(GPIO_SSP2_MOSI); + + /* Configure clocking */ + +#ifdef LPC111x + regval = getreg32(LPC11_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_SSP2_MASK; + regval |= (SSP_PCLKSET_DIV << SYSCON_PCLKSEL0_SSP2_SHIFT); + putreg32(regval, LPC11_SYSCON_PCLKSEL0); +#endif + + /* Enable peripheral clocking to SSP0 and SSP1 */ + + regval = getreg32(LPC11_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCSSP2; + putreg32(regval, LPC11_SYSCON_PCONP); + irqrestore(flags); + + return &g_ssp2dev; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_sspinitialize + * + * Description: + * Initialize the selected SSP port. + * + * Input Parameter: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *lpc11_sspinitialize(int port) +{ + FAR struct lpc11_sspdev_s *priv; + uint32_t regval; + int i; + + /* Only the SSP0 and SSP1 interfaces are supported */ + + switch (port) + { +#ifdef CONFIG_LPC11_SSP0 + case 0: + priv = lpc11_ssp0initialize(); + break; +#endif +#ifdef CONFIG_LPC11_SSP1 + case 1: + priv = lpc11_ssp1initialize(); + break; +#endif +#ifdef CONFIG_LPC11_SSP2 + case 2: + priv = lpc11_ssp2initialize(); + break; +#endif + default: + return NULL; + } + + /* Configure 8-bit SPI mode */ + + ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI); + + /* Disable the SSP and all interrupts (we'll poll for all data) */ + + ssp_putreg(priv, LPC11_SSP_CR1_OFFSET, 0); + ssp_putreg(priv, LPC11_SSP_IMSC_OFFSET, 0); + + /* Set the initial SSP configuration */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = 0; + priv->nbits = 8; + priv->mode = SPIDEV_MODE0; +#endif + + /* Select a default frequency of approx. 400KHz */ + + ssp_setfrequency((FAR struct spi_dev_s *)priv, 400000); + + /* Initialize the SPI semaphore that enforces mutually exclusive access */ + +#ifndef CONFIG_SPI_OWNBUS + sem_init(&priv->exclsem, 0, 1); +#endif + + /* Enable the SPI */ + + regval = ssp_getreg(priv, LPC11_SSP_CR1_OFFSET); + ssp_putreg(priv, LPC11_SSP_CR1_OFFSET, regval | SSP_CR1_SSE); + for (i = 0; i < LPC11_SSP_FIFOSZ; i++) + { + (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); + } + + return &priv->spidev; +} + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be done + * after a device is deselected if you worry about such things. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void ssp_flush(FAR struct spi_dev_s *dev) +{ + FAR struct lpc11_sspdev_s *priv = (FAR struct lpc11_sspdev_s *)dev; + + /* Wait for the TX FIFO not full indication */ + + while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_TNF)); + ssp_putreg(priv, LPC11_SSP_DR_OFFSET, 0xff); + + /* Wait until TX FIFO and TX shift buffer are empty */ + + while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_BSY); + + /* Wait until RX FIFO is not empty */ + + while (!(ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE)); + + /* Then read and discard bytes until the RX FIFO is empty */ + + do + { + (void)ssp_getreg(priv, LPC11_SSP_DR_OFFSET); + } + while (ssp_getreg(priv, LPC11_SSP_SR_OFFSET) & SSP_SR_RNE); +} + +#endif /* CONFIG_LPC11_SSP0/1 */ diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.h b/arch/arm/src/lpc11xx/lpc11_ssp.h new file mode 100644 index 00000000000..c9a06368ad5 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_ssp.h @@ -0,0 +1,189 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_ssp.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip/lpc11_ssp.h" + +#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_sspinitialize + * + * Description: + * Initialize the selected SSP port. + * + * Input Parameter: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ************************************************************************************/ + +FAR struct spi_dev_s *lpc11_sspinitialize(int port); + +/************************************************************************************ + * Name: lpc11_ssp0/ssp1select, lpc11_ssp0/ssp1status, and lpc11_ssp0/ssp1cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including lpc11_sspinitialize()) are provided by common LPC11xx logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in lpc11_boardinitialize() to configure SSP chip select pins. + * 2. Provide lpc11_ssp0/ssp1select() and lpc11_ssp0/ssp1status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * lpc11_ssp0/ssp1cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to lpc11_sspinitialize() in your low level application + * initialization logic + * 4. The handle returned by lpc11_sspinitialize() may then be used to bind the + * SSP driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SSP driver to the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC11_SSP0 +void lpc11_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc11_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc11_ssp0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +#ifdef CONFIG_LPC11_SSP1 +void lpc11_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t lpc11_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int lpc11_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/************************************************************************************ + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from ssp0/1select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ************************************************************************************/ + +#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) +void ssp_flush(FAR struct spi_dev_s *dev); +#endif + +/************************************************************************************ + * Name: lpc11_ssp0/1register + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD drvier when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) must + * must be implemented. These functiosn implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +#ifdef CONFIG_LPC11_SSP0 +int lpc11_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif + +#ifdef CONFIG_LPC11_SSP1 +int lpc11_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, + FAR void *arg); +#endif +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC11_SSP0 || CONFIG_LPC11_SSP1 */ +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c new file mode 100644 index 00000000000..6ec8f727fc1 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_start.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_start.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc11_clockconfig.h" +#include "lpc11_lowputc.h" +#include "lpc11_userspace.h" + +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const uint32_t g_idle_topstack = IDLE_STACK; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Configure the uart so that we can get debug output as soon as possible */ + + lpc11_clockconfig(); + lpc11_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + showprogress('C'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + showprogress('D'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + lpc11_userspace(); + showprogress('E'); +#endif + + /* Initialize onboard resources */ + + lpc11_boardinitialize(); + showprogress('F'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + + os_start(); + + /* Shouldn't get here */ + + for (;;); +} diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c new file mode 100644 index 00000000000..2401529cb79 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_timer.c @@ -0,0 +1,633 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_timer.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "chip/lpc11_syscon.h" +#include "lpc11_timer.h" +#include "chip/lpc116x_pinconfig.h" +#include "lpc11_gpio.h" +#include "lpc116x_gpio.h" + +/* This module then only compiles if there is at least one enabled timer + * intended for use with the TIMER upper half driver. + */ + +#if defined(CONFIG_LPC17_TMR0) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* PWM/Timer Definitions ****************************************************/ +/* The following definitions are used to identify the various time types */ + +#define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */ +#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */ +#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */ +#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */ + +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED + + +/* Debug ********************************************************************/ +/* Non-standard debug that may be enabled just for testing PWM */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_PWM +#endif + +#ifdef CONFIG_DEBUG_PWM +# define pwmdbg dbg +# define pwmlldbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define pwmvdbg vdbg +# define pwmllvdbg llvdbg +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) +# else +# define pwmlldbg(x...) +# define pwmllvdbg(x...) +# define pwm_dumpgpio(p,m) +# endif +#else +# define pwmdbg(x...) +# define pwmlldbg(x...) +# define pwmvdbg(x...) +# define pwmllvdbg(x...) +# define pwm_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure represents the state of one PWM timer */ + +struct lpc11_timer_s +{ + FAR const struct pwm_ops_s *ops; /* PWM operations */ + uint8_t timid; /* Timer ID {0,...,7} */ + uint8_t channel; /* Timer output channel: {1,..4} */ + uint8_t timtype; /* See the TIMTYPE_* definitions */ + uint32_t base; /* The base address of the timer */ + uint32_t pincfg; /* Output pin configuration */ + uint32_t pclk; /* The frequency of the peripheral clock + * that drives the timer module. */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ +/* Register access */ + +static uint32_t timer_getreg(struct lpc11_timer_s *priv, int offset); +static void timer_putreg(struct lpc11_timer_s *priv, int offset, uint32_t value); + +#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE) +static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg); +#else +# define timer_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int timer_timer(FAR struct lpc11_timer_s *priv, + FAR const struct pwm_info_s *info); + +/* PWM driver methods */ + +static int timer_setup(FAR struct pwm_lowerhalf_s *dev); +static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev); + +static int timer_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info); + +static int timer_stop(FAR struct pwm_lowerhalf_s *dev); +static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* This is the list of lower half PWM driver methods used by the upper half driver */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = timer_setup, + .shutdown = timer_shutdown, + .start = timer_start, + .stop = timer_stop, + .ioctl = timer_ioctl, +}; + +#ifdef CONFIG_LPC17_TMR0 +static struct lpc11_timer_s g_pwm1dev = +{ + .ops = &g_pwmops, + .timid = 1, + .channel = CONFIG_LPC17_MAT0_PIN, + .timtype = TIMTYPE_TIM1, + .base = LPC17_TMR1_BASE, + .pincfg = GPIO_MAT0p1_2, + .pclk = (0x1 << 12), +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_getreg + * + * Description: + * Read the value of an PWM timer register. + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t timer_getreg(struct lpc11_timer_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: timer_putreg + * + * Description: + * Read the value of an PWM timer register. + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void timer_putreg(struct lpc11_timer_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: timer_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input parameters: + * priv - A reference to the PWM block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_PWM) && defined(CONFIG_DEBUG_VERBOSE) +static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg) +{ + pwmdbg("%s:\n", msg); + pwmdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + timer_getreg(priv, LPC17_PWM_MR0_OFFSET), + timer_getreg(priv, LPC17_PWM_MR1_OFFSET), + timer_getreg(priv, LPC17_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); +#if defined(CONFIG_LPC17_TMR0) + if (priv->timtype == TIMTYPE_ADVANCED) + { + pwmdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + timer_getreg(priv, LPC17_PWM_MR0_OFFSET), + timer_getreg(priv, LPC17_PWM_MR1_OFFSET), + timer_getreg(priv, LPC17_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); + } + else +#endif + { + pwmdbg(" DCR: %04x DMAR: %04x\n", + timer_getreg(priv, LPC17_PWM_MR2_OFFSET), + timer_getreg(priv, LPC17_PWM_MR3_OFFSET)); + } +} +#endif + +/**************************************************************************** + * Name: timer_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input parameters: + * priv - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_timer(FAR struct lpc11_timer_s *priv, + FAR const struct pwm_info_s *info) +{ + irqstate_t flags; + uint32_t regval; + + flags = irqsave(); + + putreg32(info->frequency, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + putreg32(info->frequency, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + + putreg32(1, LPC17_TMR0_TCR); /* Start timer0 */ + putreg32(1, LPC17_TMR1_TCR); /* Start timer1 */ + + irqrestore(flags); + timer_dumpregs(priv, "After starting"); + return OK; +} + +#ifdef XXXXX +/**************************************************************************** + * Name: timer_interrupt + * + * Description: + * Handle timer interrupts. + * + * Input parameters: + * priv - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_interrupt(struct lpc11_timer_s *priv) +{ + uint16_t regval; + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = timer_getreg(priv, STM32_ATIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + timer_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + + /* Calculate the new count by subtracting the number of pulses + * since the last interrupt. + */ + + return OK; +} + +/**************************************************************************** + * Name: timer_tim1/8interrupt + * + * Description: + * Handle timer 1 and 8 interrupts. + * + * Input parameters: + * Standard NuttX interrupt inputs + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_tim1interrupt(int irq, void *context) +{ + return timer_interrupt(&g_pwm1dev); +} + +#endif /* XXXXX */ + +/**************************************************************************** + * Name: timer_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int timer_setup(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; + irqstate_t flags; + uint32_t regval; + + flags = irqsave(); + + /* Power on the timer peripherals*/ + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCTIM0; + regval |= SYSCON_PCONP_PCTIM1; + regval |= SYSCON_PCONP_PCTIM2; + regval |= SYSCON_PCONP_PCTIM3; + putreg32(regval, LPC17_SYSCON_PCONP); + + /* Select clock for the timer peripheral*/ + + regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval &= ~(0x3 << 2); + regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval &= ~(0x3 << 4); + regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + putreg32(regval, LPC17_SYSCON_PCLKSEL0); + regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval &= ~(0x3 << 12); + regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + regval &= ~(0x3 << 14); + regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */ + putreg32(regval, LPC17_SYSCON_PCLKSEL1); + priv->pclk = (0x1 << 12) | (0x1 << 4); + + putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */ + + putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR0_CTCR);/* Prescaler count frequency: Fpclk/1 */ + putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */ + + /* Output bit toggle on external match event External match on MR1, Toggle + * external bit + */ + + putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR); + putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0*/ + + /* Configure the output pins GPIO3.26 */ + + lpc11_configgpio(GPIO_MAT0p1_2); + + putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */ + + putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */ + putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */ + putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */ +// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0*/ + putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1*/ + + /* configure the output pins GPIO3.26 */ +// lpc11_configgpio(GPIO_MAT0p1_2); + + irqrestore(flags); + pwm_dumpgpio(priv->pincfg, "TIMER setup"); + return OK; +} + +/**************************************************************************** + * Name: timer_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input parameters: + * dev - A reference to the lower half TIMER driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; + uint32_t pincfg; + + pwmdbg("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + + /* Make sure that the output has been stopped */ + + return OK; +} + +/**************************************************************************** + * Name: timer_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input parameters: + * dev - A reference to the lower half TIMER driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; + return timer_timer(priv, info); +} + +/**************************************************************************** + * Name: timer_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input parameters: + * dev - A reference to the lower half TIMER driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int timer_stop(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; + uint32_t resetbit; + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + pwmdbg("TIM%d\n", priv->timid); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = irqsave(); + + /* Disable further interrupts and stop the timer */ + + /* Determine which timer to reset */ + + switch (priv->timid) + { +#ifdef CONFIG_LPC17_TMR0 + case 1: + break; +#endif + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where timer_start() can be called. + */ + + irqrestore(flags); + + pwmdbg("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + timer_dumpregs(priv, "After stop"); + return OK; +} + +/**************************************************************************** + * Name: timer_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input parameters: + * dev - A reference to the lower half TIMER driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_TIMER + FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; + + /* There are no platform-specific ioctl commands */ + + pwmdbg("TIM%d\n", priv->timid); +#endif + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_timerinitialize + * + * Description: + * Initialize one timer for use with the upper_level TIMER driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,14}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half TIMER driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer) +{ + FAR struct lpc11_timer_s *lower; + + pwmdbg("TIM%d\n", timer); + + switch (timer) + { +#ifdef CONFIG_LPC17_TMR0 + case 0: + lower = &g_pwm1dev; + + /* Attach but disable the TIM1 update interrupt */ + + break; +#endif + + default: + pwmdbg("No such timer configured\n"); + return NULL; + } + + return (FAR struct pwm_lowerhalf_s *)lower; +} + +#endif /* CONFIG_LPC17_TIMn_TIMER, n = 1,...,14 */ diff --git a/arch/arm/src/lpc11xx/lpc11_timer.h b/arch/arm/src/lpc11xx/lpc11_timer.h new file mode 100644 index 00000000000..d548fada516 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_timer.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_timer.h + * + * Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc17_timer.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_timerisr.c b/arch/arm/src/lpc11xx/lpc11_timerisr.c new file mode 100644 index 00000000000..38790f44800 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_timerisr.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_timerisr.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* "The CLKSOURCE bit in SysTick Control and Status register selects either + * the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock + * (when CLKSOURCE = 0). ..." + */ + +#if defined(CONFIG_LPC11_SYSTICK_CORECLK) +# define SYSTICK_CLOCK LPC11_MCLK /* Core clock */ +#elif defined(CONFIG_LPC11_SYSTICK_CORECLK_DIV16) +# define SYSTICK_CLOCK (LPC11_MCLK / 16) /* Core clock divided by 16 */ +#endif + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * Then, for example, if the external high speed crystal is the SysTick + * clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then + * the reload value would be: + * + * SYSTICK_RELOAD = (12,000,000 / 100) - 1 + * = 119,999 + * = 0x1d4bf + * + * Which fits within the maximum 24-bit reload value. + */ + +#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(ARMV6M_SYSCON_SHPR3); + regval &= ~SYSCON_SHPR3_PRI_15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT); + putreg32(regval, ARMV6M_SYSCON_SHPR3); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(LPC11_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and + * Status register selects either the core clock (when CLKSOURCE = 1) or + * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." + */ + +#ifdef CONFIG_LPC11_SYSTICK_CORECLK + putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), + ARMV6M_SYSTICK_CSR); +#else + putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR); +#endif + + /* And enable the timer interrupt */ + + up_enable_irq(LPC11_IRQ_SYSTICK); +} diff --git a/arch/arm/src/lpc11xx/lpc11_userspace.c b/arch/arm/src/lpc11xx/lpc11_userspace.c new file mode 100644 index 00000000000..f2372643ac3 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_userspace.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/arm/src/lpc11xx/lpc11_userspace.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "lpc11_mpuinit.h" +#include "lpc11_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc11_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void lpc11_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t*)USERSPACE->us_bssstart; + end = (uint8_t*)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t*)USERSPACE->us_datasource; + dest = (uint8_t*)USERSPACE->us_datastart; + end = (uint8_t*)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure the MPU to permit user-space access to its FLASH and RAM */ + + lpc11_mpuinitialize(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/lpc11xx/lpc11_userspace.h b/arch/arm/src/lpc11xx/lpc11_userspace.h new file mode 100644 index 00000000000..6737b3b32d1 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_userspace.h @@ -0,0 +1,76 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_userspace.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: lpc17_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void lpc17_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H */ diff --git a/arch/arm/src/lpc11xx/lpc11_wdt.h b/arch/arm/src/lpc11xx/lpc11_wdt.h new file mode 100644 index 00000000000..613aac42969 --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_wdt.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_wdt.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc11_wdt.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ diff --git a/configs/Kconfig b/configs/Kconfig index 7ddf22e5915..c530f22811e 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -272,6 +272,14 @@ config ARCH_BOARD_LM4F120_LAUNCHPAD ---help--- Stellaris LM4F120 LaunchPad. +config ARCH_BOARD_LPCXPRESSO_LPC1115 + bool "NXP LPCXpresso LPC1115" + depends on ARCH_CHIP_LPC1115 + select ARCH_HAVE_LEDS + ---help--- + Embedded Artists base board with NXP LPCExpresso LPC1115. This board + is based on the NXP LPC1115. + config ARCH_BOARD_LPCXPRESSO bool "NXP LPCExpresso LPC1768" depends on ARCH_CHIP_LPC1768 @@ -1171,6 +1179,7 @@ config ARCH_BOARD default "lm4f120-launchpad" if ARCH_BOARD_LM4F120_LAUNCHPAD default "lpc4330-xplorer" if ARCH_BOARD_LPC4330_XPLORER default "lpc4357-evb" if ARCH_BOARD_LPC4357_EVB + default "lpcxpresso-lpc1115" if ARCH_BOARD_LPCXPRESSO_LPC1115 default "lpcxpresso-lpc1768" if ARCH_BOARD_LPCXPRESSO default "maple" if ARCH_BOARD_MAPLE default "mbed" if ARCH_BOARD_MBED diff --git a/configs/lpcxpresso-lpc1115/Kconfig b/configs/lpcxpresso-lpc1115/Kconfig new file mode 100644 index 00000000000..f1e54d99c94 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_LPCXPRESSO_LPC1115 +endif diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt new file mode 100644 index 00000000000..a0c375f3118 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/README.txt @@ -0,0 +1,556 @@ +README +^^^^^^ + +README for NuttX port to the Embedded Artists' base board with the NXP +the LPCXpresso daughter board. Product code: EA-XPR-009 + +Contents +^^^^^^^^ + + LCPXpresso LPC1115 Board + Embedded Artist's Base Board + Development Environment + GNU Toolchain Options + NuttX EABI "buildroot" Toolchain + NuttX OABI "buildroot" Toolchain + NXFLAT Toolchain + Code Red IDE + LEDs + LPCXpresso Configuration Options + Configurations + +LCPXpresso LPC1115 Board +^^^^^^^^^^^^^^^^^^^^^^^^ + + Pin Description Connector + -------------------------------- --------- + + P0[0]/RD1/TXD3/SDA1 J6-9 + P0[1]/TD1/RXD3/SCL J6-10 + P0[2]/TXD0/AD0[7] J6-21 + P0[3]/RXD0/AD0[6] J6-22 + P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 + P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 + P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 + P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 + P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 + P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 + P0[10] J6-40 + P0[11] J6-41 + + P1[0]/ENET-TXD0 J6-34? + P1[1]/ENET_TXD1 J6-35? + P1[4]/ENET_TX_EN + P1[8]/ENET_CRS + P1[9]/ENET_RXD0 + P1[10]/ENET_RXD1 + + P2[0]/PWM1.1/TXD1 + P2[1]/PWM1.2/RXD1 J6-43 + P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 + P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 + P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 + P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 + P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 + P2[7]/RD2/RTS1 J6-49 + P2[8]/TD2/TXD2 J6-50 + P2[9]/USB_CONNECT/RXD2 PAD19 + P2[10]/EINT0/NMI J6-51 + + P3[25]/MAT0.0/PWM1.2 PAD13 + P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 + +Development Environment +^^^^^^^^^^^^^^^^^^^^^^^ + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +GNU Toolchain Options +^^^^^^^^^^^^^^^^^^^^^ + + The NuttX make system has been modified to support the following different + toolchain options. + + 1. The Code Red GNU toolchain + 2. The CodeSourcery GNU toolchain, + 3. The devkitARM GNU toolchain, + 4. The NuttX buildroot Toolchain (see below). + + All testing has been conducted using the Code Red toolchain and the + make system is setup to default to use the Code Red Linux toolchain. To use + the other toolchain, you simply need add one of the following configuration + options to your .config (or defconfig) file: + + CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows + CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux + CONFIG_ARMV6M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows + CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) + CONFIG_ARMV6M_TOOLCHAIN_CODEREDW=n : Code Red toolchain under Windows + CONFIG_ARMV6M_TOOLCHAIN_CODEREDL=y : Code Red toolchain under Linux + + You may also have to modify the PATH in the setenv.h file if your make cannot + find the tools. + + NOTE: the CodeSourcery (for Windows), devkitARM, and Code Red (for Windoes) + are Windows native toolchains. The CodeSourcey (for Linux), Code Red (for Linux) + and NuttX buildroot toolchains are Cygwin and/or Linux native toolchains. There + are several limitations to using a Windows based toolchain in a Cygwin + environment. The three biggest are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + + 3. Dependencies are not made when using Windows versions of the GCC. This is + because the dependencies are generated using Windows pathes which do not + work with the Cygwin make. + + MKDEP = $(TOPDIR)/tools/mknulldeps.sh + + NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization + level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with + -Os. + + NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that + the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM + path or will get the wrong version of make. + +Code Red IDE +^^^^^^^^^^^^ + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. + + Makefile Build + -------------- + Under Linux Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/arm/src/lpc11xx, + arch/arm/src/common, arch/arm/src/armv7-m, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/arm/src/lpc11x/lpc11_vectors.S. + + Using Code Red GNU Tools from Cygwin + ------------------------------------ + + Under Cygwin, the Code Red command line tools (e.g., arm-non-eabi-gcc) cannot + be executed because the they only have execut privileges for Administrators. I + worked around this by: + + Opening a native Cygwin RXVT as Administrator (Right click, "Run as administrator"), + then executing 'chmod 755 *.exe' in the following directories: + + /cygdrive/c/nxp/lpcxpreeso_3.6/bin, and + /cygdrive/c/nxp/lpcxpreeso_3.6/Tools/bin + + Command Line Flash Programming + ------------------------------ + + During the port development was used a STLink-v2 SWD programmer with OpenOCD to + write the firmware in the flash and GDB to debug NuttX initialization. + + If using LPCLink as your debug connection, first of all boot the LPC-Link using + the script: + + bin\Scripts\bootLPCXpresso type + + where type = winusb for Windows XP, or type = hid for Windows Vista / 7. + + Now run the flash programming utility with the following options + + flash_utility wire -ptarget -flash-load[-exec]=filename [-load-base=base_address] + + Where flash_utility is one of: + + crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts) + crt_emu_cm3_nxp (for LPC11xx parts) + crt_emu_a7_nxp (for LPC21/22/23/24 parts) + crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts) + crt_emu_cm3_lmi (for TI Stellaris parts) + + wire is one of: + + (empty) (for Red Probe+, Red Probe, RDB1768v1, or TI Stellaris evaluation boards) + -wire=hid (for RDB1768v2 without upgraded firmware) + -wire=winusb (for RDB1768v2 with upgraded firmware) + -wire=winusb (for LPC-Link on Windows XP) + -wire=hid (for LPC-Link on Windows Vista/ Windows 7) + + target is the target chip name. For example LPC1343, LPC1114/301, LPC1115 etc. + + filename is the file to flash program. It may be an executable (axf) or a binary + (bin) file. If using a binary file, the base_address must be specified. + + base_address is the base load address when flash programming a binary file. It + should be specified as a hex value with a leading 0x. + + Note: + - flash-load will leave the processor in a stopped state + - flash-load-exec will start execution of application as soon as download has + completed. + + Examples + To load the executable file app.axf and start it executing on an LPC1158 + target using Red Probe, use the following command line: + + crt_emu_cm3_nxp -pLPC1158 -flash-load-exec=app.axf + + To load the binary file binary.bin to address 0x1000 to an LPC1343 target + using LPC-Link on Windows XP, use the following command line: + + crt_emu_lpc11_13_nxp -wire=hid -pLPC1343 -flash-load=binary.bin -load-base=0x1000 + + tools/flash.sh + -------------- + + All of the above steps are automated in the bash script flash.sh that can + be found in the configs/lpcxpresso/tools directory. + +NuttX EABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the Cortex-M3 GCC toolchain (if + different from the default in your PATH variable). + + If you have no Cortex-M0 toolchain, one can be downloaded from the NuttX + SourceForge download site (https://sourceforge.net/projects/nuttx/files/). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1115/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm0-eabi-defconfig-4.6.3 .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + See the file configs/README.txt in the buildroot source tree. That has more + details PLUS some special instructions that you will need to follow if you + are building a Cortex-M3 toolchain for Cygwin under Windows. + + NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the + the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for + more information about this problem. If you plan to use NXFLAT, please do not + use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. + See instructions below. + +NuttX OABI "buildroot" Toolchain +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The older, OABI buildroot toolchain is also available. To use the OABI + toolchain: + + 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 + configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI + configuration such as cortexm3-defconfig-4.3.3 + + 2. Modify the Make.defs file to use the OABI conventions: + + +CROSSDEV = arm-nuttx-elf- + +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv6-m -mfloat-abi=soft + +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections + -CROSSDEV = arm-nuttx-eabi- + -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +NXFLAT Toolchain +^^^^^^^^^^^^^^^^ + + If you are *not* using the NuttX buildroot toolchain and you want to use + the NXFLAT tools, then you will still have to build a portion of the buildroot + tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can + be downloaded from the NuttX SourceForge download site + (https://sourceforge.net/projects/nuttx/files/). + + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh lpcxpresso-lpc1115/ + + 2. Download the latest buildroot package into + + 3. unpack the buildroot tarball. The resulting directory may + have versioning information on it like buildroot-x.y.z. If so, + rename /buildroot-x.y.z to /buildroot. + + 4. cd /buildroot + + 5. cp configs/cortexm0-defconfig-nxflat .config + + 6. make oldconfig + + 7. make + + 8. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly builtNXFLAT binaries. + +LEDs +^^^^ + + If CONFIG_ARCH_LEDS is defined, then support for the LPCXpresso LEDs will be + included in the build. See: + + - configs/lpcxpresso-lpc1115/include/board.h - Defines LED constants, types and + prototypes the LED interface functions. + + - configs/lpcxpresso-lpc1115/src/lpcxpresso_internal.h - GPIO settings for the LEDs. + + - configs/lpcxpresso-lpc1115/src/up_leds.c - LED control logic. + + The LPCXpresso LPC1115 has a single LEDs (there are more on the Embedded Artists + base board, but those are not controlled by NuttX). Usage this single LED by NuttX + is as follows: + + - The LED is not illuminated until the LPCXpresso completes initialization. + + If the LED is stuck in the OFF state, this means that the LPCXpresso did not + complete initializeation. + + - Each time the OS enters an interrupt (or a signal) it will turn the LED OFF and + restores its previous stated upon return from the interrupt (or signal). + + The normal state, after initialization will be a dull glow. The brightness of + the glow will be inversely related to the proportion of time spent within interrupt + handling logic. The glow may decrease in brightness when the system is very + busy handling device interrupts and increase in brightness as the system becomes + idle. + + Stuck in the OFF state suggests that that the system never completed + initialization; Stuck in the ON state would indicated that the system + intialialized, but is not takint interrupts. + + - If a fatal assertion or a fatal unhandled exception occurs, the LED will flash + strongly as a slow, 2Hz rate. + +LPCXpresso Configuration Options +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + General Architecture Settings: + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM0=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=lpc11xx + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_LPC1115=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=lpcxpresso-lpc1115 + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_LPCEXPRESSO=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case): + + CONFIG_RAM_SIZE=(8*1024) (8Kb) + + There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1. + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x10000000 + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + CONFIG_LPC11_MAINOSC=y + CONFIG_LPC11_PLL0=y + CONFIG_LPC11_UART0=y + CONFIG_LPC11_CAN1=n + CONFIG_LPC11_SPI=n + CONFIG_LPC11_SSP0=n + CONFIG_LPC11_SSP1=n + CONFIG_LPC11_I2C0=n + CONFIG_LPC11_I2S=n + CONFIG_LPC11_TMR0=n + CONFIG_LPC11_TMR1=n + CONFIG_LPC11_PWM0=n + CONFIG_LPC11_ADC=n + CONFIG_LPC11_FLASH=n + + LPC11xx specific device driver settings + + CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the + console and ttys0 (default is the UART0). + CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_UARTn_2STOP - Two stop bits + + LPC11xx specific CAN device driver settings. These settings all + require CONFIG_CAN: + + CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default + Standard 11-bit IDs. + CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC11_CAN1 is defined. + CONFIG_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. + (the CCLK frequency is divided by this number to get the CAN clock). + Options = {1,2,4,6}. Default: 4. + CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 + +Configurations +^^^^^^^^^^^^^^ + +Each LPCXpresso configuration is maintained in a sub-directory and can be +selected as follow: + + cd tools + ./configure.sh lpcxpresso-lpc1115/ + cd - + . ./setenv.sh + +Where is one of the following: + + dhcpd: + This builds the DCHP server using the apps/examples/dhcpd application + (for execution from FLASH.) See apps/examples/README.txt for information + about the dhcpd example. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Jumpers: Nothing special. Use the default base board jumper + settings. + + nsh: + Configures the NuttShell (nsh) located at apps/examples/nsh. The + Configuration enables both the serial and telnet NSH interfaces. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. This configuration has been used for testing the microSD card. + This support is, however, disabled in the base configuration. + + At last attempt, the SPI-based mircroSD does not work at + higher fequencies. Setting the SPI frequency to 400000 + removes the problem. There must be some more optimal + value that could be determined with additional experimetnation. + + Jumpers: J55 must be set to provide chip select PIO1_11 signal as + the SD slot chip select. + + nx: + And example using the NuttX graphics system (NX). This example + uses the UG-9664HSWAG01 driver. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + and misc/tools/ + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + diff --git a/configs/lpcxpresso-lpc1115/include/board.h b/configs/lpcxpresso-lpc1115/include/board.h new file mode 100644 index 00000000000..d935ea27bf8 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/include/board.h @@ -0,0 +1,246 @@ +/************************************************************************************ + * configs/lpcxpresso-lpc1115/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_BOARD_BOARD_H +#define __ARCH_BOARD_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* NOTE: The following definitions require lpc11_syscon.h. It is not included here + * because the including C file may not have that file in its include path. + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ +#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */ +#define BOARD_INTRCOSC_FREQUENCY (1200000) /* Internal RC oscillator frequency */ + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 + * MCLK = 480MHz / 6 = 80MHz -> MCLK divider = 6 + */ + +#define LPC11_MCLK 48000000 /* 48Mhz */ + +/* Select the internal RC oscillator as the frequency source. SYSCLK is then the frequency + * of the main oscillator. + */ + +#undef CONFIG_LPC11_INTRCOSC +#define CONFIG_LPC11_INTRCOSC 1 +#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN + +/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. + * The input to the divider (PLLCLK) will be determined by the PLL output. + */ + +#define BOARD_CCLKCFG_DIVIDER 6 +#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) + +/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). + * + * Source clock: Main oscillator + * PLL0 Multiplier value (M): 20 + * PLL0 Pre-divider value (N): 1 + * + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz + */ + +#undef CONFIG_LPC11_PLL0 +#define CONFIG_LPC11_PLL0 1 +#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN + +#define BOARD_PLL0CFG_MSEL 20 +#define BOARD_PLL0CFG_NSEL 1 +#define BOARD_PLL0CFG_VALUE \ + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) + +/* PLL1 -- Not used. */ + +#undef CONFIG_LPC11_PLL1 +#define BOARD_PLL1CFG_MSEL 36 +#define BOARD_PLL1CFG_NSEL 1 +#define BOARD_PLL1CFG_VALUE \ + (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ + ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) + +/* USB divider. This divider is used when PLL1 is not enabled to get the + * USB clock from PLL0: + * + * USBCLK = PLL0CLK / 10 = 48MHz + */ + +#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10 + +/* FLASH Configuration */ + +#undef CONFIG_LPC11_FLASH +#define CONFIG_LPC11_FLASH 1 +#define BOARD_FLASHCFG_VALUE 0x0000303a + +/* LED definitions ******************************************************************/ +/* The LPCXpresso LPC1115 board has a single red LED (there are additional LEDs on + * the base board not considered here). + */ + /* ON OFF */ +#define LED_STARTED 0 /* OFF ON (never happens) */ +#define LED_HEAPALLOCATE 0 /* OFF ON (never happens) */ +#define LED_IRQSENABLED 0 /* OFF ON (never happens) */ +#define LED_STACKCREATED 1 /* ON ON (never happens) */ +#define LED_INIRQ 2 /* OFF NC (momentary) */ +#define LED_SIGNAL 2 /* OFF NC (momentary) */ +#define LED_ASSERTION 2 /* OFF NC (momentary) */ +#define LED_PANIC 0 /* OFF ON (1Hz flashing) */ + +/* Alternate pin selections *********************************************************/ +/* Pin Description Connector On Board Base Board + * -------------------------------- --------- -------------- --------------------- + * P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 + * P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1 + * P0[2]/TXD0/AD0[7] J6-21 + * P0[3]/RXD0/AD0[6] J6-22 + * P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 + * P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 + * P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1, OLED CS + * P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1, OLED SCK + * P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 + * P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1, OLED data in + * P0[10] J6-40 TXD2/SDA2 + * P0[11] J6-41 RXD2/SCL2 + */ + +#define GPIO_UART3_TXD GPIO_UART3_TXD_1 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#define GPIO_UART3_RXD GPIO_UART3_RXD_1 +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 +#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1 +#define GPIO_UART2_TXD GPIO_UART2_TXD_1 +#define GPIO_UART2_RXD GPIO_UART2_RXD_1 +#define GPIO_UART1_TXD GPIO_UART1_TXD_1 +#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 +#define GPIO_UART1_RXD GPIO_UART1_RXD_1 +#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1 +#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1 +#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1 + +/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) + * P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) + * P1[4]/ENET_TX_EN TXEN N/A + * P1[8]/ENET_CRS CRS_DV/MODE2 N/A + * P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) + * P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) + */ + +#define GPIO_ENET_MDC GPIO_ENET_MDC_1 +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 + +/* P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 / RGB LED / RS422 RX + * P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 / OLED voltage / RGB LED / RS422 RX + * P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 + * P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 + * P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 + * P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 + * P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 + * P2[7]/RD2/RTS1 J6-49 OLED command/data + * P2[8]/TD2/TXD2 J6-50 + * P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A + * P2[10]/EINT0/NMI J6-51 + * P2[11]/EINT1/I2STX_CLK J6-52 + */ + +#define GPIO_PWM1p1 GPIO_PWM1p1_2 +#define GPIO_PWM1p2 GPIO_PWM1p2_2 +#define GPIO_PWM1p3 GPIO_PWM1p3_2 +#define GPIO_PWM1p4 GPIO_PWM1p4_2 +#define GPIO_PWM1p5 GPIO_PWM1p5_2 +#define GPIO_PWM1p6 GPIO_PWM1p6_2 + +/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A + * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: lpc11_boardinitialize + * + * Description: + * All LPC11xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +EXTERN void lpc11_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lpcxpresso-lpc1115/nsh/Make.defs b/configs/lpcxpresso-lpc1115/nsh/Make.defs new file mode 100644 index 00000000000..836c4e5095c --- /dev/null +++ b/configs/lpcxpresso-lpc1115/nsh/Make.defs @@ -0,0 +1,123 @@ +############################################################################ +# configs/freedom-kl25z/nsh/Make.defs +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHWARNINGSXX = -Wall -Wshadow +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = +ifeq ($(CONFIG_HOST_WINDOWS),y) + HOSTEXEEXT = .exe +else + HOSTEXEEXT = +endif + +ifeq ($(WINTOOL),y) + # Windows-native host tools + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mknulldeps.sh +else + # Linux/Cygwin-native host tools + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +endif + diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig new file mode 100644 index 00000000000..b03d5e1ab68 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/nsh/defconfig @@ -0,0 +1,831 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set + +# +# Debug Options +# +# CONFIG_DEBUG is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +CONFIG_ARCH_CHIP_LPC11XX=y +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +CONFIG_ARCH_CORTEXM0=y +# CONFIG_ARCH_CORTEXM3 is not set +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +CONFIG_ARCH_FAMILY="armv6-m" +CONFIG_ARCH_CHIP="lpc11xx" +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set + +# +# ARMV6M Configuration Options +# +# CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV6M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV6M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_GPIO_IRQ is not set + +# +# LPC11xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC1114 is not set +CONFIG_ARCH_CHIP_LPC1115=y +CONFIG_ARCH_FAMILY_LPC111X=y + +# +# LPC11xx Peripheral Support +# +CONFIG_LPC11_INTRCOSC=y +# CONFIG_LPC11_MAINOSC is not set +CONFIG_LPC11_SYSTICK_CORECLK=y +# CONFIG_LPC11_SYSTICK_CORECLK_DIV16 is not set +CONFIG_LPC11_PLL=y +CONFIG_LPC11_UART0=y +# CONFIG_LPC11_CAN0 is not set +# CONFIG_LPC11_SPI is not set +# CONFIG_LPC11_SSP0 is not set +# CONFIG_LPC11_SSP1 is not set +# CONFIG_LPC11_I2C0 is not set +# CONFIG_LPC11_TMR0 is not set +# CONFIG_LPC11_TMR1 is not set +# CONFIG_LPC11_WDT is not set +# CONFIG_LPC11_ADC is not set +# CONFIG_LPC11_FLASH is not set + +# +# Serial driver options +# +# CONFIG_SERIAL_TERMIOS is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=2988 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_SIZE=8192 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_LPCXPRESSO_LPC1115=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="lpcxpresso-lpc1115" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_NSH_MMCSDMINOR=0 + +# +# Board-Specific Options +# + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=2 +CONFIG_START_DAY=26 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=0 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=4 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=0 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# Work Queue Support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set +# CONFIG_LCD is not set +# CONFIG_MMCSD is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_ARCH_HAVE_UART is not set +CONFIG_ARCH_HAVE_UART0=y +# CONFIG_ARCH_HAVE_UART1 is not set +# CONFIG_ARCH_HAVE_UART2 is not set +# CONFIG_ARCH_HAVE_UART3 is not set +# CONFIG_ARCH_HAVE_UART4 is not set +# CONFIG_ARCH_HAVE_UART5 is not set +# CONFIG_ARCH_HAVE_UART6 is not set +# CONFIG_ARCH_HAVE_UART7 is not set +# CONFIG_ARCH_HAVE_UART8 is not set +# CONFIG_ARCH_HAVE_SCI0 is not set +# CONFIG_ARCH_HAVE_SCI1 is not set +# CONFIG_ARCH_HAVE_USART0 is not set +# CONFIG_ARCH_HAVE_USART1 is not set +# CONFIG_ARCH_HAVE_USART2 is not set +# CONFIG_ARCH_HAVE_USART3 is not set +# CONFIG_ARCH_HAVE_USART4 is not set +# CONFIG_ARCH_HAVE_USART5 is not set +# CONFIG_ARCH_HAVE_USART6 is not set +# CONFIG_ARCH_HAVE_USART7 is not set +# CONFIG_ARCH_HAVE_USART8 is not set +# CONFIG_ARCH_HAVE_OTHER_UART is not set + +# +# USART Configuration +# +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=64 +CONFIG_UART0_TXBUFSIZE=64 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_WIRELESS is not set + +# +# System Logging Device Options +# + +# +# System Logging +# +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_CONSOLE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set + +# +# System Logging +# +# CONFIG_SYSLOG is not set +# CONFIG_SYSLOG_TIMESTAMP is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +CONFIG_MM_SMALL=y +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=0 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXFLAT is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_ROMFS is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_THTTPD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_PCODE is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set + +# +# Network Utilities +# + +# +# Networking Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_THTTPD is not set +# CONFIG_NETUTILS_NETLIB is not set +# CONFIG_NETUTILS_WEBCLIENT is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DD=y +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +CONFIG_NSH_DISABLE_MKDIR=y +# CONFIG_NSH_DISABLE_MKFIFO is not set +CONFIG_NSH_DISABLE_MKRD=y +# CONFIG_NSH_DISABLE_MH is not set +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_NSH_DISABLE_PUT=y +# CONFIG_NSH_DISABLE_PWD is not set +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +CONFIG_NSH_DISABLE_UMOUNT=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +CONFIG_NSH_DISABLE_WGET=y +# CONFIG_NSH_DISABLE_XD is not set + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=64 + +# +# Scripting Support +# +CONFIG_NSH_DISABLESCRIPT=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# + +# +# Custom Free Memory Command +# +# CONFIG_SYSTEM_FREE is not set + +# +# EMACS-like Command Line Editor +# +# CONFIG_SYSTEM_CLE is not set + +# +# CU Minimal Terminal +# +# CONFIG_SYSTEM_CUTERM is not set + +# +# FLASH Program Installation +# +# CONFIG_SYSTEM_INSTALL is not set + +# +# FLASH Erase-all Command +# + +# +# Intel HEX to binary conversion +# +# CONFIG_SYSTEM_HEX2BIN is not set + +# +# I2C tool +# + +# +# INI File Parser +# +# CONFIG_SYSTEM_INIFILE is not set + +# +# NxPlayer media player library / command Line +# + +# +# RAM test +# +# CONFIG_SYSTEM_RAMTEST is not set + +# +# readline() +# +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y + +# +# P-Code Support +# + +# +# PHY Tool +# + +# +# Power Off +# +# CONFIG_SYSTEM_POWEROFF is not set + +# +# RAMTRON +# +# CONFIG_SYSTEM_RAMTRON is not set + +# +# SD Card +# +# CONFIG_SYSTEM_SDCARD is not set + +# +# Sudoku +# +# CONFIG_SYSTEM_SUDOKU is not set + +# +# Sysinfo +# +# CONFIG_SYSTEM_SYSINFO is not set + +# +# Temperature +# + +# +# VI Work-Alike Editor +# +# CONFIG_SYSTEM_VI is not set + +# +# Stack Monitor +# + +# +# USB CDC/ACM Device Commands +# + +# +# USB Composite Device Commands +# + +# +# USB Mass Storage Device Commands +# + +# +# USB Monitor +# + +# +# Zmodem Commands +# +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1115/nsh/setenv.sh b/configs/lpcxpresso-lpc1115/nsh/setenv.sh new file mode 100644 index 00000000000..73ecd99413a --- /dev/null +++ b/configs/lpcxpresso-lpc1115/nsh/setenv.sh @@ -0,0 +1,59 @@ +#!/bin/bash +# configs/lpcxpresso-lpc1768/nsh/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi + +WD=`pwd` + +# This is where the buildroot might reside on a Linux or Cygwin system +# export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin" + +# This is the default install location for Code Red on Linux +export TOOLCHAIN_BIN="/usr/local/LPCXpresso/tools/bin" + +# This is the Cygwin path to the LPCXpresso 3.6 install location under Windows +#export TOOLCHAIN_BIN="/cygdrive/c/nxp/lpcxpresso_3.6/Tools/bin" + +# This is the path to the LPCXpression tool subdirectory +export LPCTOOL_DIR="${WD}/configs/lpcxpresso-lpc1768/tools" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/lpcxpresso-lpc1115/scripts/ld.script b/configs/lpcxpresso-lpc1115/scripts/ld.script new file mode 100644 index 00000000000..44ca50b8d69 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/scripts/ld.script @@ -0,0 +1,129 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc1115/scripts/ld.script + * + * Copyright (C) 2011-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1115 has 64Kb of FLASH beginning at address 0x00000000 and + * 8Kb of SRAM at address 0x10000000. + */ + +MEMORY +{ + vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 0x00c0 + progflash (rx) : ORIGIN = 0x00000410, LENGTH = 64k + datasram (rwx) : ORIGIN = 0x10000000, LENGTH = 8K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(_cfmconfig) +ENTRY(_stext) +SECTIONS +{ + .vectors : { + _svectors = ABSOLUTE(.); + *(.vectors) + _evectors = ABSOLUTE(.); + } > vectflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progflash + + .ARM.extab : { + *(.ARM.extab*) + } > progflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progflash + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datasram AT > progflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > datasram AT > progflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datasram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpcxpresso-lpc1115/src/.gitignore b/configs/lpcxpresso-lpc1115/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/lpcxpresso-lpc1115/src/Makefile b/configs/lpcxpresso-lpc1115/src/Makefile new file mode 100644 index 00000000000..93f16b23ab3 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/Makefile @@ -0,0 +1,108 @@ +############################################################################ +# configs/lpcxpresso-lpc1115/src/Makefile +# +# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = up_boot.c + +ifeq ($(CONFIG_NSH_ARCHINIT),y) +CSRCS += up_nsh.c +endif + +ifeq ($(CONFIG_KL_SPI0),y) +CSRCS += kl_spi.c +else +ifeq ($(CONFIG_KL_SPI1),y) +CSRCS += kl_spi.c +endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += up_leds.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += up_pwm.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + CFLAGS += -I$(ARCH_SRCDIR)\chip -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\armv7-m +else +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m +endif +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/configs/lpcxpresso-lpc1115/src/lpcxpresso_internal.h b/configs/lpcxpresso-lpc1115/src/lpcxpresso_internal.h new file mode 100644 index 00000000000..30b156a2742 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/lpcxpresso_internal.h @@ -0,0 +1,236 @@ +/************************************************************************************ + * configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h + * arch/arm/src/board/lpcxpresso_internal.n + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_INTERNAL_H +#define _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* LPCXpresso LPC1115 board pin usage ***********************************************/ +/* Pin Description Connector On Board Base Board + * -------------------------------- --------- -------------- --------------------- + * P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 + * P0[1]/TD1/RXD3/SCL J6-10 RXD2/SCL1 + * P0[2]/TXD0/AD0[7] J6-21 + * P0[3]/RXD0/AD0[6] J6-22 + * P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 + * P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 + * P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1 + * P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1 + * P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 + * P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1 + * P0[10] J6-40 TXD2/SDA2 + * P0[11] J6-41 RXD2/SCL2 + * P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0 + * P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0 + * P0[17]/CTS1/MISO0/MISO J6-12 MISO0 + * P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0 + * P0[19]/DSR1/SDA1 PAD17 N/A + * P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A + * P0[21]/RI1/MCIPWR/RD1 J6-23 + * P0[22]/RTS1/TD1 J6-24 LED + * P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0 + * P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1 + * P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2 + * P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT + * P0[27]/SDA0/USB_SDA J6-25 + * P0[28]/SCL0 J6-26 + * P0[29]/USB_D+ J6-37 USB_D+ + * P0[30]/USB_D- J6-36 USB_D- + */ + +#define LPCXPRESSO_I2C1_EPROM_SDA GPIO_I2C1_SDA_1 +#define LPCXPRESSO_I2C1_EPROM_SDL GPIO_I2C1_SCL_2 +#define LPCXPRESSO_LED (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT0 | GPIO_PIN7) + +/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) + * P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) + * P1[4]/ENET_TX_EN TXEN N/A + * P1[8]/ENET_CRS CRS_DV/MODE2 N/A + * P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) + * P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) + * P1[14]/ENET_RX_ER RXER/PHYAD0 N/A + * P1[15]/ENET_REF_CLK REFCLK N/A + * P1[16]/ENET_MDC MDC N/A + * P1[17]/ENET_MDIO MDIO N/A + * P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A + * P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A + * P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A + * P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A + * P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A + * P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A + * P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A + * P1[25]/MC1A/MAT1.1 PAD8 N/A + * P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A + * P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A + * P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A + * P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A + * P1[30]/VBUS/AD0[4] J6-19 AD0.4 + * P1[31]/SCK1/AD0[5] J6-20 AD0.5 + * + * P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 + * P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 + * P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 + * P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 + * P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 + * P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 + * P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 + * P2[7]/RD2/RTS1 J6-49 + * P2[8]/TD2/TXD2 J6-50 + * P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A + * P2[10]/EINT0/NMI J6-51 + * P2[11]/EINT1/I2STX_CLK J6-52 + * P2[12]/EINT2/I2STX_WS J6-53 + * P2[13]/EINT3/I2STX_SDA J6-27 + */ + +#define LPCXPRESSO_USB_PULLUP (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN9) + +/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A + * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A + * + * P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A + * P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A + */ + +/* SD Slot + * + * Base-board J4/J6 LPC1115 + * SD Signal Pin Pin + * --- ----------- ----- -------- + * CS PIO1_11* 55 P2.2 (See LPCXPRESSO_SD_CS) + * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in chip/lpc17_ssp.h) + * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in chip/lpc17_ssp.h) + * CLK PIO2_11-SCK 7 P0.9 SCK1 (See GPIO_SSP1_SCK in board.h) + * CD PIO2_10 52 P2.11 (See LPCXPRESSO_SD_CD) + */ + +#define LPCXPRESSO_SD_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT2 | GPIO_PIN2) +#ifdef CONFIG_GPIO_IRQ +# define LPCXPRESSO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#else +# define LPCXPRESSO_SD_CD (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN11) +#endif + +/* USB: + * + * Base-board J4/J6 LPC1115 + * Signal Pin Pin + * ------------------- ----- -------- + * USB_DM 36 P0.30/USB-D- + * USB_DP 37 P0.29/USB-D+ + * N/C N/C P1.18/USB-UP-LED/PWM1.1/CAP1.0 + * PIO1_3 (not used) 19 P1.30/VBUS/AD0.4 + * N/C N/C P2.9/USB-CONNECT/RXD2 (See Notes) + * ------------------- ----- -------- + * PIO0_6-USB_CONNECT* 23 P0.21/RI1/RD1 + * PIO0_3-VBUS_SENSE 39 P0.5/I2SRX-WS/TD2/CAP2.1 + * + * Notes: + * - The standard USB CONNECT (P0.9) provides USB D+ pullup on board the + * LPCXpresso card; it should be un-necessary to use the based board + * version of the pullup. + * - No changes to jumper settings are required. There are few USB- + * related jumpers on the based board, but none are required: + * - J14 must be set to permit GPIO control of the base board USB + * connect pin. NOT USED + * - J12 must be set to permit GPIO control of the USB vbus sense pin + * - The standard VBUS (P1.30) is not connected. As a consequence, the + * USB driver will not correctly respond to USB insertion or removal + * events. + * - The standard USB LED (P1.18) is not connected. + */ + +#define LPCXPRESSO_USB_CONNECT (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN21) +#ifdef CONFIG_GPIO_IRQ +# define LPCXPRESSO_USB_VBUSSENSE (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#else +# define LPCXPRESSO_USB_VBUSSENSE (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5) +#endif + +/* 96x64 White OLED with I2C/SPI interface + * + * ----------------------------+-------+-------------- ----------------------------- + * LPC1758 Pin | J4/6 | Base Board Description + * ----------------------------+-------+-------------- ----------------------------- + * P2.1/PWM1.2/RXD1 | 43 | PIO1_10 FAN5331 Power Control (SHDN#) + * P0.6/I2SRX-SDA/SSEL1/MAT2.0 | 8 | PIO0_2 OLED chip select (CS#) + * P2.7/RD2/RTS1 | 49 | PIO2_7 OLED command/data (D/C#) + * P0.7/I2STX-CLK/SCK1/MAT2.1 | 7 | PIO2_11-SCK OLED clock (D0) + * P0.9/I2STX-SDA/MOSI1/MAT2.3 | 5 | PIO0_9-MOSI OLED data in (D1) + * ----------------------------+-------+-------------- ----------------------------- + */ + +#define LPCXPRESSO_OLED_POWER (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1) +#define LPCXPRESSO_OLED_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN6) +#define LPCXPRESSO_OLED_DC (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN7) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpcxpresso_sspinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPCXpresso board. + * + ************************************************************************************/ + +void weak_function lpcxpresso_sspinitialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LPCXPRESSO_LPC1115_SRC_LPCXPRESSO_INTERNAL_H */ + diff --git a/configs/lpcxpresso-lpc1115/src/up_adc.c b/configs/lpcxpresso-lpc1115/src/up_adc.c new file mode 100644 index 00000000000..cb5b296b9d4 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_adc.c @@ -0,0 +1,123 @@ +/************************************************************************************ + * configs/lpcexpresso-1768/src/up_adc.c + * arch/arm/src/board/up_adc.c + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Kannan + * + * Based on configs/stm3220g-eval/src/up_adc.c + * + * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "lpc17_adc.h" +#include "lpcxpresso_internal.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: adc_devinit + * + * Description: + * All LPC17 architectures must provide the following interface to work with + * examples/adc. + * + ************************************************************************************/ + +int adc_devinit(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + + adc = lpc17_adcinitialize(); + if (adc == NULL) + { + adbg("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC */ diff --git a/configs/lpcxpresso-lpc1115/src/up_boot.c b/configs/lpcxpresso-lpc1115/src/up_boot.c new file mode 100644 index 00000000000..13456fa2b5f --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_boot.c @@ -0,0 +1,93 @@ +/************************************************************************************ + * configs/lpcxpresso-lpc1115/src/up_boot.c + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc11_ssp.h" +#include "lpcxpresso_internal.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_boardinitialize + * + * Description: + * All LPC11xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc11_boardinitialize(void) +{ + /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak + * function lpcxpresso_sspinitialize() has been brought into the link. + */ + +#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1) + if (lpcxpresso_sspinitialize) + { + lpcxpresso_sspinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_led_initialize(); +#endif +} diff --git a/configs/lpcxpresso-lpc1115/src/up_dac.c b/configs/lpcxpresso-lpc1115/src/up_dac.c new file mode 100644 index 00000000000..9b54bea185f --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_dac.c @@ -0,0 +1,100 @@ +/************************************************************************************ + * configs/zkit-arm-1769/src/up_dac.c + * arch/arm/src/board/up_dac.c + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Kannan + * + * Based on configs/stm3220g-eval/src/up_dac.c + * + * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_dac.h" + +#ifdef CONFIG_DAC + +/************************************************************************************ + * Name: dac_devinit + * + * Description: + * All LPC17xx architectures must provide the following interface to work with + * examples/diag. + * + ************************************************************************************/ + +int dac_devinit(void) +{ + static bool initialized = false; + struct dac_dev_s *dac; + int ret; + + if (!initialized) + { + /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + + dac = lpc17_dacinitialize(); + if (dac == NULL) + { + adbg("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } + + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + adbg("dac_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/configs/lpcxpresso-lpc1115/src/up_leds.c b/configs/lpcxpresso-lpc1115/src/up_leds.c new file mode 100644 index 00000000000..2317b135df1 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_leds.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc1168/src/up_leds.c + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc11_gpio.h" +#include "lpcxpresso_internal.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG + * with CONFIG_DEBUG_VERBOSE too) + */ + +#ifdef CONFIG_DEBUG_LEDS +# define leddbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define ledvdbg lldbg +# else +# define ledvdbg(x...) +# endif +#else +# define leddbg(x...) +# define ledvdbg(x...) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_ncstate; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_led_initialize + ****************************************************************************/ + +void board_led_initialize(void) +{ + /* Configure all LED GPIO lines */ + + lpc11_configgpio(LPCXPRESSO_LED); + g_ncstate = true; +} + +/**************************************************************************** + * Name: board_led_on + ****************************************************************************/ + +void board_led_on(int led) +{ + bool off; + + switch (led) + { + case 0: + case 2: + off = true; + break; + + case 1: + off = false; + g_ncstate = false; + break; + + default: + return; + } + + lpc11_gpiowrite(LPCXPRESSO_LED, off); +} + +/**************************************************************************** + * Name: board_led_off + ****************************************************************************/ + +void board_led_off(int led) +{ + bool off; + + switch (led) + { + case 0: + case 1: + off = false; + break; + + case 2: + off = g_ncstate; + break; + + default: + return; + } + + lpc11_gpiowrite(LPCXPRESSO_LED, off); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lpcxpresso-lpc1115/src/up_nsh.c b/configs/lpcxpresso-lpc1115/src/up_nsh.c new file mode 100644 index 00000000000..93cb3c0b2c1 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_nsh.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * config/lpcxpresso-lpc1768/src/up_nsh.c + * arch/arm/src/board/up_nsh.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_LPCXPRESSO +# define NSH_HAVEUSBDEV 1 +# ifdef CONFIG_LPC17_SSP1 +# define NSH_HAVEMMCSD 1 +# else +# undef NSH_HAVEMMCSD +# endif +#else +# error "Unrecognized board" +# undef NSH_HAVEUSBDEV +# undef NSH_HAVEMMCSD +#endif + +/* Do we have SPI support for MMC/SD? */ + +#ifdef NSH_HAVEMMCSD +# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1 +# error "The LPCXpresso MMC/SD is on SSP1" +# undef CONFIG_NSH_MMCSDSPIPORTNO +# define CONFIG_NSH_MMCSDSPIPORTNO 1 +# endif +# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0 +# error "The LPCXpresso MMC/SD has only one slot (0)" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/* Can't support USB device features if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_archinitialize + * + * Description: + * Perform architecture specific initialization + * + ****************************************************************************/ + +int nsh_archinitialize(void) +{ +#ifdef NSH_HAVEMMCSD + FAR struct spi_dev_s *ssp; + int ret; + + /* Get the SSP port */ + + ssp = lpc17_sspinitialize(CONFIG_NSH_MMCSDSPIPORTNO); + if (!ssp) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + + /* Bind the SSP port to the slot */ + + ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, CONFIG_NSH_MMCSDSLOTNO, ssp); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to bind SSP port %d to MMC/SD slot %d: %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO, ret); + return ret; + } + + syslog(LOG_INFO, "Successfuly bound SSP port %d to MMC/SD slot %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); +#endif + return OK; +} diff --git a/configs/lpcxpresso-lpc1115/src/up_pwm.c b/configs/lpcxpresso-lpc1115/src/up_pwm.c new file mode 100644 index 00000000000..88741fd0d7c --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_pwm.c @@ -0,0 +1,152 @@ +/************************************************************************************ + * configs/lpcexpresso-lpc1768/up_pwm.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "lpc17_pwm.h" +#include "lpc17_timer.h" +#include "lpcxpresso_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +#ifdef CONFIG_PWM + +FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: pwm_devinit + * + * Description: + * All LPC17 architectures must provide the following interface to work with + * examples/pwm. + * + ************************************************************************************/ + +int pwm_devinit(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + struct pwm_lowerhalf_s *mcpwm; + struct pwm_lowerhalf_s *timer; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + + pwm = lpc17_pwminitialize(0); + if (!pwm) + { + adbg("Failed to get the LPC17XX PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + adbg("pwm_register failed: %d\n", ret); + return ret; + } + + mcpwm = lpc17_mcpwminitialize(0); + if (!mcpwm) + { + adbg("Failed to get the LPC17XX MOTOR PWM lower half\n"); + return -ENODEV; + } + + /* Register the MOTOR CONTROL PWM driver at "/dev/mcpwm0" */ + + ret = pwm_register("/dev/mcpwm0", mcpwm); + if (ret < 0) + { + adbg("mcpwm_register failed: %d\n", ret); + return ret; + } + + timer = lpc17_timerinitialize(0); + if (!timer) + { + adbg("Failed to get the LPC17XX TIMER lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/timer0" */ + + ret = pwm_register("/dev/timer0", timer); + if (ret < 0) + { + adbg("timer_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/configs/lpcxpresso-lpc1115/src/up_ssp.c b/configs/lpcxpresso-lpc1115/src/up_ssp.c new file mode 100644 index 00000000000..f16bc396c69 --- /dev/null +++ b/configs/lpcxpresso-lpc1115/src/up_ssp.c @@ -0,0 +1,214 @@ +/************************************************************************************ + * configs/lpcxpresso-lpc1768/src/up_ssp.c + * arch/arm/src/board/up_ssp.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc17_gpio.h" +#include "lpc17_ssp.h" +#include "lpcxpresso_internal.h" + +#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SSP_DEBUG /* Define to enable debug */ +#undef SSP_VERBOSE /* Define to enable verbose debug */ + +#ifdef SSP_DEBUG +# define sspdbg lldbg +# ifdef SSP_VERBOSE +# define sspvdbg lldbg +# else +# define sspvdbg(x...) +# endif +#else +# undef SSP_VERBOSE +# define sspdbg(x...) +# define sspvdbg(x...) +#endif + +/* Dump GPIO registers */ + +#ifdef SSP_VERBOSE +# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +#else +# define ssp_dumpgpio(m) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpcxpresso_sspinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPCXpresso. + * + ************************************************************************************/ + +void weak_function lpcxpresso_sspinitialize(void) +{ + /* Configure the SPI-based microSD CS GPIO */ + + ssp_dumpgpio("lpcxpresso_sspinitialize() Entry)"); + + /* Configure card detect and chip select for the SD slot. NOTE: Jumper J55 must + * be set correctly for the SD slot chip select. + */ + +#ifdef CONFIG_LPC17_SSP1 + (void)lpc17_configgpio(LPCXPRESSO_SD_CS); + (void)lpc17_configgpio(LPCXPRESSO_SD_CD); + + /* Configure chip select for the OLED. For the SPI interface, insert jumpers in + * J42, J43, J45 pin1-2 and J46 pin 1-2. + */ + +#ifdef CONFIG_NX_LCDDRIVER + (void)lpc17_configgpio(LPCXPRESSO_OLED_CS); +#endif +#endif + + ssp_dumpgpio("lpcxpresso_sspinitialize() Exit"); +} + +/************************************************************************************ + * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * + * Description: + * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * must be provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including lpc17_sspinitialize()) + * are provided by common LPC17xx logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * pins. + * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 3. Add a calls to lpc17_sspinitialize() in your low level application + * initialization logic + * 4. The handle returned by lpc17_sspinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_SSP0 +void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssp_dumpgpio("lpc17_ssp0select() Entry"); + +#warning "Assert CS here (false)" + + ssp_dumpgpio("lpc17_ssp0select() Exit"); +} + +uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + sspdbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_LPC17_SSP1 +void lpc17_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssp_dumpgpio("lpc17_ssp1select() Entry"); + + if (devid == SPIDEV_MMCSD) + { + /* Assert/de-assert the CS pin to the card */ + + (void)lpc17_gpiowrite(LPCXPRESSO_SD_CS, !selected); + } +#ifdef CONFIG_NX_LCDDRIVER + else if (devid == SPIDEV_DISPLAY) + { + /* Assert the CS pin to the OLED display */ + + (void)lpc17_gpiowrite(LPCXPRESSO_OLED_CS, !selected); + } +#endif + ssp_dumpgpio("lpc17_ssp1select() Exit"); +} + +uint8_t lpc17_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + if (devid == SPIDEV_MMCSD) + { + /* Read the state of the card-detect bit */ + + if (lpc17_gpioread(LPCXPRESSO_SD_CD) == 0) + { + sspdbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; + } + } + + sspdbg("Returning zero\n"); + return 0; +} +#endif + +#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */