From bb73c45a611f39775ef08bfd97f40b0b94c272de Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 10 Jun 2015 08:38:35 -0600 Subject: [PATCH] SAML21: Since SERCOM5 usese a different output channel, it will also need a different GCLK generator --- arch/arm/src/samdl/sam_lowputc.c | 2 +- arch/arm/src/samdl/sam_sercom.c | 2 +- arch/arm/src/samdl/sam_spi.c | 9 ++++++++- arch/arm/src/samdl/sam_usart.c | 8 +++++++- arch/arm/src/samdl/sam_usart.h | 1 + configs/samd20-xplained/include/board.h | 7 ++++++- configs/saml21-xplained/include/board.h | 11 +++++++++-- 7 files changed, 33 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/samdl/sam_lowputc.c b/arch/arm/src/samdl/sam_lowputc.c index 5b7ebc2a0ff..64a3189ef01 100644 --- a/arch/arm/src/samdl/sam_lowputc.c +++ b/arch/arm/src/samdl/sam_lowputc.c @@ -310,7 +310,7 @@ int sam_usart_internal(const struct sam_usart_config_s * const config) sam_gclk_chan_enable(config->sercom + GCLK_CHAN_SERCOM0_CORE, config->gclkgen); #endif - sercom_slowclk_configure(config->sercom, BOARD_SERCOM_SLOW_GCLKGEN); + sercom_slowclk_configure(config->sercom, config->slowgen); /* Set USART configuration according to the board configuration */ diff --git a/arch/arm/src/samdl/sam_sercom.c b/arch/arm/src/samdl/sam_sercom.c index b024ea6ae1a..33ab89f367d 100644 --- a/arch/arm/src/samdl/sam_sercom.c +++ b/arch/arm/src/samdl/sam_sercom.c @@ -254,7 +254,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen) break; #endif /* CONFIG_SAMDL_SERCOM5 */ - /* Unsupport or invalid SERCOM number provided */ + /* Unsupported or invalid SERCOM number provided */ default: DEBUGPANIC(); diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 89a84ca1022..a90737debac 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -118,6 +118,7 @@ struct sam_spidev_s uint8_t irq; /* SERCOM IRQ number */ #endif uint8_t gclkgen; /* Source GCLK generator */ + uint8_t slowgen; /* Slow GCLK generator */ port_pinset_t pad0; /* Pin configuration for PAD0 */ port_pinset_t pad1; /* Pin configuration for PAD1 */ port_pinset_t pad2; /* Pin configuration for PAD2 */ @@ -269,6 +270,7 @@ static struct sam_spidev_s g_spi0dev = .irq = SAM_IRQ_SERCOM0, #endif .gclkgen = BOARD_SERCOM0_GCLKGEN, + .slowgen = BOARD_SERCOM0_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM0_PINMAP_PAD0, .pad1 = BOARD_SERCOM0_PINMAP_PAD1, .pad2 = BOARD_SERCOM0_PINMAP_PAD2, @@ -321,6 +323,7 @@ static struct sam_spidev_s g_spi1dev = .irq = SAM_IRQ_SERCOM1, #endif .gclkgen = BOARD_SERCOM1_GCLKGEN, + .slowgen = BOARD_SERCOM1_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM1_PINMAP_PAD0, .pad1 = BOARD_SERCOM1_PINMAP_PAD1, .pad2 = BOARD_SERCOM1_PINMAP_PAD2, @@ -373,6 +376,7 @@ static struct sam_spidev_s g_spi2dev = .irq = SAM_IRQ_SERCOM2, #endif .gclkgen = BOARD_SERCOM2_GCLKGEN, + .slowgen = BOARD_SERCOM2_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM2_PINMAP_PAD0, .pad1 = BOARD_SERCOM2_PINMAP_PAD1, .pad2 = BOARD_SERCOM2_PINMAP_PAD2, @@ -425,6 +429,7 @@ static struct sam_spidev_s g_spi3dev = .irq = SAM_IRQ_SERCOM3, #endif .gclkgen = BOARD_SERCOM3_GCLKGEN, + .slowgen = BOARD_SERCOM3_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM3_PINMAP_PAD0, .pad1 = BOARD_SERCOM3_PINMAP_PAD1, .pad2 = BOARD_SERCOM3_PINMAP_PAD2, @@ -477,6 +482,7 @@ static struct sam_spidev_s g_spi4dev = .irq = SAM_IRQ_SERCOM4, #endif .gclkgen = BOARD_SERCOM4_GCLKGEN, + .slowgen = BOARD_SERCOM4_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM4_PINMAP_PAD0, .pad1 = BOARD_SERCOM4_PINMAP_PAD1, .pad2 = BOARD_SERCOM4_PINMAP_PAD2, @@ -529,6 +535,7 @@ static struct sam_spidev_s g_spi5dev = .irq = SAM_IRQ_SERCOM5, #endif .gclkgen = BOARD_SERCOM5_GCLKGEN, + .slowgen = BOARD_SERCOM5_SLOW_GCLKGEN, .pad0 = BOARD_SERCOM5_PINMAP_PAD0, .pad1 = BOARD_SERCOM5_PINMAP_PAD1, .pad2 = BOARD_SERCOM5_PINMAP_PAD2, @@ -1528,7 +1535,7 @@ struct spi_dev_s *up_spiinitialize(int port) /* Configure the GCLKs for the SERCOM module */ sercom_coreclk_configure(priv->sercom, priv->gclkgen, false); - sercom_slowclk_configure(priv->sercom, BOARD_SERCOM_SLOW_GCLKGEN); + sercom_slowclk_configure(priv->sercom, priv->slowgen); /* Set the SERCOM in SPI master mode (no address) */ diff --git a/arch/arm/src/samdl/sam_usart.c b/arch/arm/src/samdl/sam_usart.c index 431a4f28f3e..01a2d977c3d 100644 --- a/arch/arm/src/samdl/sam_usart.c +++ b/arch/arm/src/samdl/sam_usart.c @@ -63,7 +63,8 @@ const struct sam_usart_config_s g_usart0config = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .irq = SAM_IRQ_SERCOM0, - .gclkgen = BOARD_SERCOM0_GCLKGEN , + .gclkgen = BOARD_SERCOM0_GCLKGEN, + .slowgen = BOARD_SERCOM0_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART0_2STOP, .baud = CONFIG_USART0_BAUD, .pad0 = BOARD_SERCOM0_PINMAP_PAD0, @@ -84,6 +85,7 @@ const struct sam_usart_config_s g_usart1config = .bits = CONFIG_USART1_BITS, .irq = SAM_IRQ_SERCOM1, .gclkgen = BOARD_SERCOM1_GCLKGEN, + .slowgen = BOARD_SERCOM1_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, .pad0 = BOARD_SERCOM1_PINMAP_PAD0, @@ -104,6 +106,7 @@ const struct sam_usart_config_s g_usart2config = .bits = CONFIG_USART2_BITS, .irq = SAM_IRQ_SERCOM2, .gclkgen = BOARD_SERCOM2_GCLKGEN, + .slowgen = BOARD_SERCOM2_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, .pad0 = BOARD_SERCOM2_PINMAP_PAD0, @@ -124,6 +127,7 @@ const struct sam_usart_config_s g_usart3config = .bits = CONFIG_USART3_BITS, .irq = SAM_IRQ_SERCOM3, .gclkgen = BOARD_SERCOM3_GCLKGEN, + .slowgen = BOARD_SERCOM3_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, .pad0 = BOARD_SERCOM3_PINMAP_PAD0, @@ -144,6 +148,7 @@ const struct sam_usart_config_s g_usart4config = .bits = CONFIG_USART4_BITS, .irq = SAM_IRQ_SERCOM4, .gclkgen = BOARD_SERCOM4_GCLKGEN, + .slowgen = BOARD_SERCOM4_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART4_2STOP, .baud = CONFIG_USART4_BAUD, .pad0 = BOARD_SERCOM4_PINMAP_PAD0, @@ -164,6 +169,7 @@ const struct sam_usart_config_s g_usart5config = .bits = CONFIG_USART5_BITS, .irq = SAM_IRQ_SERCOM5, .gclkgen = BOARD_SERCOM5_GCLKGEN, + .slowgen = BOARD_SERCOM5_SLOW_GCLKGEN, .stopbits2 = CONFIG_USART5_2STOP, .baud = CONFIG_USART5_BAUD, .pad0 = BOARD_SERCOM5_PINMAP_PAD0, diff --git a/arch/arm/src/samdl/sam_usart.h b/arch/arm/src/samdl/sam_usart.h index 640bb2af451..46ea9d25e14 100644 --- a/arch/arm/src/samdl/sam_usart.h +++ b/arch/arm/src/samdl/sam_usart.h @@ -91,6 +91,7 @@ struct sam_usart_config_s uint8_t bits; /* Number of bits (5-9) */ uint8_t irq; /* SERCOM IRQ number */ uint8_t gclkgen; /* Source GCLK generator */ + uint8_t slowgen; /* Slow GCLK generator */ bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */ uint32_t baud; /* Configured baud */ port_pinset_t pad0; /* Pin configuration for PAD0 */ diff --git a/configs/samd20-xplained/include/board.h b/configs/samd20-xplained/include/board.h index b0d05741ac0..f98c0f9c587 100644 --- a/configs/samd20-xplained/include/board.h +++ b/configs/samd20-xplained/include/board.h @@ -359,7 +359,7 @@ * to all SERCOM modules. */ -#define BOARD_SERCOM_SLOW_GCLKGEN 0 +#define BOARD_SERCOM05_SLOW_GCLKGEN 0 /* SERCOM0 SPI is available on EXT1 * @@ -372,6 +372,7 @@ */ #define BOARD_SERCOM0_GCLKGEN 0 +#define BOARD_SERCOM0_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN #define BOARD_SERCOM0_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0) #define BOARD_SERCOM0_PINMAP_PAD0 PORT_SERCOM0_PAD0_2 /* SPI_MISO */ #define BOARD_SERCOM0_PINMAP_PAD1 0 /* microSD_SS */ @@ -391,6 +392,7 @@ */ #define BOARD_SERCOM1_GCLKGEN 0 +#define BOARD_SERCOM1_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN #define BOARD_SERCOM1_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0) #define BOARD_SERCOM1_PINMAP_PAD0 PORT_SERCOM1_PAD0_1 /* SPI_MISO */ #define BOARD_SERCOM1_PINMAP_PAD1 0 /* microSD_SS */ @@ -409,6 +411,7 @@ */ #define BOARD_SERCOM3_GCLKGEN 0 +#define BOARD_SERCOM3_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN #define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2) #define BOARD_SERCOM3_PINMAP_PAD0 0 #define BOARD_SERCOM3_PINMAP_PAD1 0 @@ -433,6 +436,7 @@ */ #define BOARD_SERCOM4_GCLKGEN 0 +#define BOARD_SERCOM4_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN #if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT1) # define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0) @@ -467,6 +471,7 @@ */ #define BOARD_SERCOM5_GCLKGEN 0 +#define BOARD_SERCOM5_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN #define BOARD_SERCOM5_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0) #define BOARD_SERCOM5_PINMAP_PAD0 PORT_SERCOM5_PAD0_1 /* SPI_MISO */ #define BOARD_SERCOM5_PINMAP_PAD1 0 /* microSD_SS */ diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h index b446333a850..d9a2fdcc0cf 100644 --- a/configs/saml21-xplained/include/board.h +++ b/configs/saml21-xplained/include/board.h @@ -498,9 +498,12 @@ /* This is the source clock generator for the GCLK_SERCOM_SLOW clock that is common * to SERCOM modules 0-4. It will generate clocking on the common SERCOM0-4 * channel. + * + * SERCOM5 uses a different channel and will probably need to use a different GCLK + * generator. */ -#define BOARD_SERCOM_SLOW_GCLKGEN 0 +#define BOARD_SERCOM04_SLOW_GCLKGEN 0 /* SERCOM0 SPI is available on EXT1 * @@ -513,6 +516,7 @@ */ #define BOARD_SERCOM0_GCLKGEN 0 +#define BOARD_SERCOM0_SLOW_GCLKGEN BOARD_SERCOM04_SLOW_GCLKGEN #define BOARD_SERCOM0_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0) #define BOARD_SERCOM0_PINMAP_PAD0 PORT_SERCOM0_PAD0_2 /* SPI_MISO */ #define BOARD_SERCOM0_PINMAP_PAD1 0 /* SPI_SS (not used) */ @@ -532,6 +536,7 @@ */ #define BOARD_SERCOM1_GCLKGEN 0 +#define BOARD_SERCOM1_SLOW_GCLKGEN BOARD_SERCOM04_SLOW_GCLKGEN #define BOARD_SERCOM1_MUXCONFIG (USART_CTRLA_TXPAD2 | USART_CTRLA_RXPAD3) #define BOARD_SERCOM1_PINMAP_PAD0 0 /* (not used) */ #define BOARD_SERCOM1_PINMAP_PAD1 0 /* (not used) */ @@ -550,6 +555,7 @@ */ #define BOARD_SERCOM3_GCLKGEN 0 +#define BOARD_SERCOM3_SLOW_GCLKGEN BOARD_SERCOM04_SLOW_GCLKGEN #define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2) #define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* USART TX */ #define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* USART RX */ @@ -569,7 +575,7 @@ */ #define BOARD_SERCOM4_GCLKGEN 0 - +#define BOARD_SERCOM4_SLOW_GCLKGEN BOARD_SERCOM04_SLOW_GCLKGEN #define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_2) #define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */ #define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART RX */ @@ -589,6 +595,7 @@ */ #define BOARD_SERCOM5_GCLKGEN 0 +#define BOARD_SERCOM5_SLOW_GCLKGEN ? #define BOARD_SERCOM5_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0) #define BOARD_SERCOM5_PINMAP_PAD0 PORT_SERCOM5_PAD0_1 /* SPI_MISO */ #define BOARD_SERCOM5_PINMAP_PAD1 0 /* SPI_SS (not used) */