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SAMA5 serial: Restore logic to minimize TX interrupts. Oddly, seems to improve ADC stability
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@@ -58,7 +58,7 @@ CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.
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CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
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CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
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CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
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CMN_CSRCS += up_createstack.c up_releasestack.c up_usestack.c up_vfork.c
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CMN_CSRCS += up_mdelay.c up_udelay.c
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CMN_CSRCS += up_puts.c up_mdelay.c up_udelay.c
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CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
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CMN_CSRCS += arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_dataabort.c
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@@ -1059,13 +1059,12 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
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#ifndef CONFIG_SUPPRESS_SERIAL_INTS
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#ifndef CONFIG_SUPPRESS_SERIAL_INTS
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up_serialout(priv, SAM_UART_IER_OFFSET, UART_INT_TXRDY);
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up_serialout(priv, SAM_UART_IER_OFFSET, UART_INT_TXRDY);
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# if 0 /* Seems to be unnecessary */
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/* Fake a TX interrupt here by just calling uart_xmitchars() with
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/* Fake a TX interrupt here by just calling uart_xmitchars() with
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* interrupts disabled (note this may recurse).
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* interrupts disabled (note this may recurse).
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*/
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*/
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uart_xmitchars(dev);
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uart_xmitchars(dev);
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# endif
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#endif
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#endif
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}
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}
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else
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else
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@@ -153,7 +153,7 @@ void uart_recvchars(FAR uart_dev_t *dev)
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while (uart_rxavailable(dev))
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while (uart_rxavailable(dev))
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{
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{
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char ch = uart_receive(dev, &status);
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char ch = uart_receive(dev, &status);
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/* If the RX buffer becomes full, then the serial data is discarded. This is
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/* If the RX buffer becomes full, then the serial data is discarded. This is
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* necessary because on most serial hardware, you must read the data in order
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* necessary because on most serial hardware, you must read the data in order
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