diff --git a/arch/arm/include/arm/spinlock.h b/arch/arm/include/arm/spinlock.h new file mode 100644 index 00000000000..ee3db052cf0 --- /dev/null +++ b/arch/arm/include/arm/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */ diff --git a/arch/arm/include/armv6-m/spinlock.h b/arch/arm/include/armv6-m/spinlock.h new file mode 100644 index 00000000000..c1d154b3700 --- /dev/null +++ b/arch/arm/include/armv6-m/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h new file mode 100644 index 00000000000..5c5d1ae6ac6 --- /dev/null +++ b/arch/arm/include/armv7-a/spinlock.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_SMP + /* In SMP configurations, save spinlocks and other inter-CPU communications + * data in a non-cached memory region. + */ + +# define SP_SECTION __attribute__((section(".nocache"))) +#endif + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-m/spinlock.h b/arch/arm/include/armv7-m/spinlock.h new file mode 100644 index 00000000000..79a06b4173f --- /dev/null +++ b/arch/arm/include/armv7-m/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-r/spinlock.h b/arch/arm/include/armv7-r/spinlock.h new file mode 100644 index 00000000000..ab7900fa733 --- /dev/null +++ b/arch/arm/include/armv7-r/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-r/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H */ diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 45f26e00065..16079cc81a3 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -44,6 +44,26 @@ # include #endif /* __ASSEMBLY__ */ +/* Include ARM architecture-specific IRQ definitions (including register + * save structure and up_irq_save()/up_irq_restore() functions) + */ + +#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \ + defined(CONFIG_ARCH_CORTEXA9) +# include +#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \ + defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \ + defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F) +# include +#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \ + defined(CONFIG_ARCH_CORTEXM7) +# include +#elif defined(CONFIG_ARCH_CORTEXM0) +# include +#else +# include +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index c84deda6194..64406572420 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -601,11 +601,13 @@ #define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1) #define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) - #define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1) #define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1) #define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS +#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) +#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1) + /* Mapped section size */ #define SECTION_SHIFT (20) @@ -1423,6 +1425,28 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry); # define mmu_l1_clrentry(v) mmu_l1_restore(v,0) #endif +/**************************************************************************** + * Name: mmu_l2_setentry + * + * Description: + * Set one small (4096B) entry in a level2 translation table. + * + * Input Parameters: + * l2vaddr - the virtual address of the beginning of the L2 translation + * table. + * paddr - The physical address to be mapped. Must be aligned to a 4KB + * address boundary + * vaddr - The virtual address to be mapped. Must be aligned to a 4KB + * address boundary + * mmuflags - The MMU flags to use in the mapping. + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_ROMPGTABLE +void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr, + uint32_t mmuflags); +#endif + /************************************************************************************ * Name: mmu_l1_map_region * diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index 36095a87a45..7318a70caad 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -191,6 +191,11 @@ # define _DATA_INIT &_eronly # define _START_DATA &_sdata # define _END_DATA &_edata + +#ifdef CONFIG_SMP +# define _START_NOCACHE &_snocache +# define _END_NOCACHE &_enocache +#endif #endif /* This is the value used to mark the stack for subsequent stack monitoring @@ -279,6 +284,11 @@ EXTERN uint32_t _edata; /* End+1 of .data */ EXTERN uint32_t _sbss; /* Start of .bss */ EXTERN uint32_t _ebss; /* End+1 of .bss */ +#ifdef CONFIG_SMP +EXTERN uint32_t _snocache; /* Start of .nocache */ +EXTERN uint32_t _enocache; /* End+1 of .nocache */ +#endif + /* Sometimes, functions must be executed from RAM. In this case, the following * macro may be used (with GCC!) to specify a function that will execute from * RAM. For example, diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 1a6fc0508df..f71eecb4327 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -917,6 +917,8 @@ * the address space. */ +#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ + #ifndef CONFIG_ARCH_LOWVECTORS /* Memory map * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION @@ -924,6 +926,10 @@ * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) + * + * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES + * pages are taken from the end of the Paging L2 page table to hold non- + * cacheable, inter-processor communication data. */ /* Vector L2 page table offset/size */ @@ -941,10 +947,18 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) - /* Paging L2 page table offset/size */ +# ifdef CONFIG_SMP + /* Paging L2 page table offset/size */ -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001800 +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE 0x000001400 + +# else + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE 0x000001800 +# endif #else /* Memory map @@ -952,12 +966,25 @@ * START END OFFSET SIZE * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) + * + * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES + * pages are taken from the end of the Paging L2 page table to hold non- + * cacheable, inter-processor communication data. */ - /* Paging L2 page table offset/size */ +# ifdef CONFIG_SMP + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE 0x000001800 + +# else + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE 0x000001c00 +# endif -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001c00 #endif /* Paging L2 page table base addresses @@ -974,6 +1001,23 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) +#ifdef CONFIG_SMP +/* Non-cached inter-processor communication data */ + +# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) +# define INTERCPU_L2_SIZE (0x00000400) + + /* on-cached inter-processor communication page table base addresses */ + +# define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET) +# define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) + + /* on-cached inter-processor communication end addresses */ + +# define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE) +# define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE) +#endif + /* Base address of the interrupt vector table. * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM @@ -996,7 +1040,8 @@ * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) - * 0x00010000 0x0003c000 Unused + * 0x00010000 0x00011000 Inter-CPU communications + * 0x00011000 0x0003c000 Unused * 0x0003c000 0x00004000 Page table (PGTABLE_SIZE) */ @@ -1004,13 +1049,27 @@ # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 +#ifdef CONFIG_SMP +/* Inter-processor communications. + * + * NOTICE that we use the unused virtual address space at 0x00400000 for + * the inter-CPU virtual communication area. + */ + +# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE) +# define INTERCPU_VADDR (0x00400000) +# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) +# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE) +#endif + #else /* Vectors located at 0xffff:0000 -- this probably does not work */ /* OCRAM Memory Map: * ---------- ---------- --------------------------- * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) - * 0x00004000 0x00030000 Unused + * 0x00004000 0x0002f000 Unused + * 0x0002f000 0x00030000 Inter-CPU communications * 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE) */ @@ -1018,6 +1077,18 @@ # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 +#ifdef CONFIG_SMP +/* Inter-processor communications + * + * NOTICE that we use the unused virtual address space at 0x00400000 for + * the inter-CPU virtual communication area. + */ + +# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE) +# define INTERCPU_VADDR (0x00400000) +# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) +# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE) +#endif #endif /************************************************************************************ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index edfd5304a14..59ccb8ac067 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -224,6 +224,48 @@ static void imx_vectormapping(void) # define imx_vectormapping() #endif +/**************************************************************************** + * Name: imx_intercpu_mapping + * + * Description: + * Setup a special mapping for the non-cached, inter-cpu communications + * area. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +static void imx_intercpu_mapping(void) +{ + uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; + uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK; + uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE; + + DEBUGASSERT(intercpu_vaddr == (uint32_t)&_snocache); + + /* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The + * i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000. + */ + + while (intercpu_paddr < end_paddr) + { + mmu_l2_setentry(INTERCPU_L2_VBASE, intercpu_paddr, intercpu_vaddr, + MMU_L2_INTERCPUFLAGS); + intercpu_paddr += 4096; + intercpu_vaddr += 4096; + } + + /* Now set the level 1 descriptor to refer to the level 2 page table. */ + + mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK, + INTERCPU_VADDR & PMD_PTE_PADDR_MASK, + MMU_L1_INTERCPUFLAGS); +} +#else + /* No inter-cpu communications area */ + +# define imx_intercpu_mapping() +#endif + /**************************************************************************** * Name: imx_copyvectorblock * @@ -388,8 +430,10 @@ static inline void imx_wdtdisable(void) void arm_boot(void) { -#ifdef CONFIG_ARCH_RAMFUNCS +#if defined(CONFIG_ARCH_RAMFUNCS) const uint32_t *src; +#endif +#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) uint32_t *dest; #endif @@ -414,6 +458,15 @@ void arm_boot(void) imx_vectormapping(); imx_lowputc('B'); +#ifdef CONFIG_SMP + /* Provide a special mapping for the OCRAM interrupt vector positioned in + * high memory. + */ + + imx_intercpu_mapping(); + imx_lowputc('C'); +#endif + #ifdef CONFIG_ARCH_RAMFUNCS /* Copy any necessary code sections from FLASH to RAM. The correct * destination in OCRAM is given by _sramfuncs and _eramfuncs. The @@ -426,14 +479,14 @@ void arm_boot(void) *dest++ = *src++; } - imx_lowputc('C'); + imx_lowputc('D'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - imx_lowputc('D'); + imx_lowputc('E'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -441,23 +494,23 @@ void arm_boot(void) */ imx_copyvectorblock(); - imx_lowputc('E'); + imx_lowputc('F'); /* Disable the watchdog timer */ imx_wdtdisable(); - imx_lowputc('F'); + imx_lowputc('G'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - imx_lowputc('G'); + imx_lowputc('H'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - imx_lowputc('H'); + imx_lowputc('I'); #endif /* Perform board-specific initialization, This must include: @@ -471,7 +524,7 @@ void arm_boot(void) */ imx_board_initialize(); - imx_lowputc('I'); + imx_lowputc('J'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -480,7 +533,7 @@ void arm_boot(void) */ imx_remap(); - imx_lowputc('J'); + imx_lowputc('K'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -489,13 +542,24 @@ void arm_boot(void) */ arm_data_initialize(); - imx_lowputc('K'); + imx_lowputc('L'); +#endif + +#ifdef CONFIG_SMP + /* Initialize the uncached, inter-CPU communications area */ + + for (dest = &_snocache; dest < &_enocache; ) + { + *dest++ = 0; + } + + imx_lowputc('M'); #endif /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - imx_lowputc('L'); + imx_lowputc('N'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -503,7 +567,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - imx_lowputc('M'); + imx_lowputc('O'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -512,6 +576,6 @@ void arm_boot(void) */ imx_cpu_enable(); - imx_lowputc('N'); + imx_lowputc('P'); imx_lowputc('\n'); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index f1134bcc926..da35b396aae 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -44,6 +44,7 @@ MEMORY { + nocache (WR) : ORIGIN = 0x00400000, LENGTH = 4K oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M } @@ -122,6 +123,13 @@ SECTIONS _enoinit = ABSOLUTE(.); } > ddr3 + .nocache : + { + _snocache = ABSOLUTE(.); + *(.nocache) + _enocache = ABSOLUTE(.); + } > nocache + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) }