Flesh out m8s12 serial driver

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3306 42af7a65-404d-4744-a932-0658087f49c3

arch/hc/src/m9s12/m9s12_lowputc.S

@@ -132,9 +132,9 @@
 	.globl	up_lowsetup
 	.type	up_lowsetup, function
 up_lowsetup:
-#ifdef CONFIG_HCS12_SERIALMON
+#ifdef HAVE_SERIAL_CONSOLE
-	rts
+#ifndef CONFIG_HCS12_SERIALMON
-#else
+
 	/* Disable the console */
 
 	ldab	#0
@@ -158,9 +158,10 @@ up_lowsetup:
 
 	ldab	#(SCI_CR2_RE|SCI_CR2_TE)
 	stab	(HCS12_CONSOLE_BASE+HCS12_SCI_CR2_OFFSET)
-	rts
 
-#endif
+#endif /* CONFIG_HCS12_SERIALMON */
+#endif /* HAVE_SERIAL_CONSOLE */
+	rts
 	.size	up_lowsetup, . - up_lowsetup
 
 /**************************************************************************
@@ -171,12 +172,13 @@ up_lowsetup:
 	.global	up_lowputc
 	.type	up_lowputc, function
 up_lowputc:
+#ifdef HAVE_SERIAL_CONSOLE
 #ifdef CONFIG_HCS12_SERIALMON
 	jmp		PutChar
 #else
-#  if HCS12_CONSOLE_BITS == 9
+#if HCS12_CONSOLE_BITS == 9
 	staa	1, -sp
-#  endif
+#endif /* HCS12_CONSOLE_BITS == 9 */
 
 	/* Wait for the transmit data register to be available (TRDE==1) */
 
@@ -187,7 +189,7 @@ up_lowputc:
 
 	/* Then write the byte to the transmit data register */
 
-#  if HCS12_CONSOLE_BITS == 9
+#if HCS12_CONSOLE_BITS == 9
 	ldaa	1, sp+
 	bita	#(0x01)
 	bne		.L8bit
@@ -197,9 +199,14 @@ up_lowputc:
 	ldaa	#0
 .Lwrdrh:
 	staa	(HCS12_CONSOLE_BASE+HCS12_SCI_DRH_OFFSET)
-#  endif
+#endif /* HCS12_CONSOLE_BITS == 9 */
+
 	stab	(HCS12_CONSOLE_BASE+HCS12_SCI_DRL_OFFSET)
 	rts
-#endif
+
+#endif /* !CONFIG_HCS12_SERIALMON */
+#else
+	rts
+#endif /* HAVE_SERIAL_CONSOLE */
 	.size	up_lowputc, . - up_lowputc
 	.end

arch/hc/src/m9s12/m9s12_sci.h

@@ -113,8 +113,9 @@
 #define SCI_CR2_TE                (1 << 3)  /* Bit 3:  Transmitter Enable */
 #define SCI_CR2_ILIE              (1 << 4)  /* Bit 4:  Idle Line Interrupt Enable */
 #define SCI_CR2_RIE               (1 << 5)  /* Bit 5:  Receiver Full Interrupt Enable Bit */
-#define SCI_CR2_TCIE              (1 << 6)  /* Bit 6:  Transmission Complete Interrupt En */
+#define SCI_CR2_TCIE              (1 << 6)  /* Bit 6:  Transmission Complete Interrupt Enable */
-#define SCI_CR2_TIE               (1 << 7)  /* Bit 7:  Transmitter Interrupt Ena */
+#define SCI_CR2_TIE               (1 << 7)  /* Bit 7:  Transmitter Interrupt Enable */
+#define SCI_CR2_ALLINTS           0xf0
 
 /* SCI Status Register 1 Bit-Field Definitions */
 

arch/hc/src/m9s12/m9s12_serial.h

@@ -51,22 +51,63 @@
 /* Is there a SCI enabled? */
 
 #if defined(CONFIG_SCI0_DISABLE) && defined(CONFIG_SCI1_DISABLE)
-#  error "No SCIs enabled"
+#  undef HAVE_SERIAL_DEVICE
+#  warning "No SCIs enabled"
+#else
+#  define HAVE_SERIAL_DEVICE 1
 #endif
 
 /* Is there a serial console? */
 
 #if defined(CONFIG_SCI0_SERIAL_CONSOLE) && !defined(CONFIG_SCI0_DISABLE)
 #  undef CONFIG_SCI1_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
+#  define HAVE_SERIAL_CONSOLE 1
 #elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && !defined(CONFIG_SCI1_DISABLE)
 #  undef CONFIG_SCI0_SERIAL_CONSOLE
-#  define HAVE_CONSOLE 1
+#  define HAVE_SERIAL_CONSOLE 1
 #else
 #  warning "No valid CONFIG_SCIn_SERIAL_CONSOLE Setting"
 #  undef CONFIG_SCI0_SERIAL_CONSOLE
 #  undef CONFIG_SCI1_SERIAL_CONSOLE
-#  undef HAVE_CONSOLE
+#  undef HAVE_SERIAL_CONSOLE
+#endif
+
+/* Sanity checking */
+
+#ifndef CONFIG_SCI0_DISABLE
+#  ifndef CONFIG_SCI0_PARITY
+#    warning "CONFIG_SCI0_PARITY not defined -- Assuming none"
+#    define CONFIG_SCI0_PARITY 0 
+#  elif CONFIG_SCI0_PARITY != 0 && CONFIG_SCI0_PARITY != 2 && CONFIG_SCI0_PARITY != 2
+#    error "CONFIG_SCI0_PARITY value not recognized"
+#  endif
+#  ifndef CONFIG_SCI0_BITS
+#    warning "CONFIG_SCI0_BITS not defined -- Assuming 8"
+#    define CONFIG_SCI0_BITS 8
+#  elif CONFIG_SCI0_BITS != 8 && CONFIG_SCI0_BITS != 9
+#    error "CONFIG_SCI0_BITS value not supported"
+#  endif
+#  if defined(CONFIG_SCI0_2STOP) && CONFIG_SCI0_2STOP != 0
+#    error "Only a single stop bit is supported"
+#  endif
+#endif
+
+#ifndef CONFIG_SCI1_DISABLE
+#  ifndef CONFIG_SCI1_PARITY
+#    warning "CONFIG_SCI1_PARITY not defined -- Assuming none"
+#    define CONFIG_SCI1_PARITY 0 
+#  elif CONFIG_SCI1_PARITY != 0 && CONFIG_SCI1_PARITY != 2 && CONFIG_SCI1_PARITY != 2
+#    error "CONFIG_SCI1_PARITY value not recognized"
+#  endif
+#  ifndef CONFIG_SCI1_BITS
+#    warning "CONFIG_SCI1_BITS not defined -- Assuming 8"
+#    define CONFIG_SCI1_BITS 8
+#  elif CONFIG_SCI1_BITS != 8 && CONFIG_SCI1_BITS != 9
+#    error "CONFIG_SCI1_BITS value not supported"
+#  endif
+#  if defined(CONFIG_SCI1_2STOP) && CONFIG_SCI1_2STOP != 0
+#    error "Only a single stop bit is supported"
+#  endif
 #endif
 
 /* BAUD *****************************************************************************/