From b8175f28417b82cc539447602684a1f6517f1bd7 Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Sat, 20 Mar 2021 13:01:22 +0100 Subject: [PATCH] boards: nxstyle fixes nxstyle fixes to pass CI Signed-off-by: Alin Jerpelea --- boards/arm/kinetis/teensy-3.x/src/k20_pwm.c | 4 +- .../arm/stm32/clicker2-stm32/src/stm32_adc.c | 10 +- .../stm32/clicker2-stm32/src/stm32_appinit.c | 4 +- .../stm32/clicker2-stm32/src/stm32_autoleds.c | 8 +- .../arm/stm32/clicker2-stm32/src/stm32_boot.c | 21 +-- .../arm/stm32/clicker2-stm32/src/stm32_can.c | 3 +- .../stm32/clicker2-stm32/src/stm32_mrf24j40.c | 7 +- .../arm/stm32/clicker2-stm32/src/stm32_spi.c | 54 +++--- .../arm/stm32/clicker2-stm32/src/stm32_usb.c | 17 +- boards/arm/stm32/fire-stm32v2/include/board.h | 112 +++++++----- .../stm32/fire-stm32v2/src/stm32_appinit.c | 2 + .../stm32/fire-stm32v2/src/stm32_autoleds.c | 25 ++- .../arm/stm32/fire-stm32v2/src/stm32_boot.c | 15 +- .../stm32/fire-stm32v2/src/stm32_enc28j60.c | 36 ++-- .../arm/stm32/fire-stm32v2/src/stm32_mmcsd.c | 10 +- .../stm32/fire-stm32v2/src/stm32_selectlcd.c | 26 ++- boards/arm/stm32/fire-stm32v2/src/stm32_spi.c | 39 +++-- .../arm/stm32/fire-stm32v2/src/stm32_usbdev.c | 20 ++- .../arm/stm32/fire-stm32v2/src/stm32_usbmsc.c | 3 +- .../stm32/hymini-stm32v/src/stm32_appinit.c | 8 +- .../stm32/hymini-stm32v/src/stm32_usbdev.c | 21 ++- .../stm32/hymini-stm32v/src/stm32_usbmsc.c | 18 +- .../arm/stm32/mikroe-stm32f4/include/board.h | 68 ++++---- .../arm/stm32/mikroe-stm32f4/src/stm32_boot.c | 16 +- .../stm32/mikroe-stm32f4/src/stm32_extmem.c | 21 ++- .../arm/stm32/nucleo-f207zg/src/stm32_boot.c | 24 +-- .../arm/stm32/nucleo-f303re/include/board.h | 9 +- .../arm/stm32/nucleo-f303ze/src/stm32_boot.c | 17 +- .../arm/stm32/nucleo-f410rb/include/board.h | 66 +++++--- .../src/stm32_romfs_initialize.c | 2 +- .../stm32/nucleo-f446re/src/stm32_ajoystick.c | 20 ++- .../arm/stm32/nucleo-f446re/src/stm32_spi.c | 12 +- .../arm/stm32/nucleo-f4x1re/include/board.h | 22 +-- .../nucleo-f4x1re/include/nucleo-f401re.h | 18 +- .../nucleo-f4x1re/include/nucleo-f411re.h | 21 ++- .../arm/stm32/nucleo-f4x1re/src/stm32_adc.c | 21 ++- .../stm32/nucleo-f4x1re/src/stm32_ajoystick.c | 43 +++-- .../arm/stm32/nucleo-f4x1re/src/stm32_spi.c | 8 +- .../stm32/olimex-stm32-e407/src/stm32_adc.c | 18 +- .../olimex-stm32-e407/src/stm32_autoleds.c | 4 +- .../stm32/olimex-stm32-e407/src/stm32_boot.c | 11 +- .../stm32/olimex-stm32-h405/include/board.h | 41 +++-- .../stm32/olimex-stm32-h405/src/stm32_adc.c | 36 ++-- .../olimex-stm32-h405/src/stm32_autoleds.c | 4 +- .../stm32/olimex-stm32-h405/src/stm32_boot.c | 13 +- .../stm32/olimex-stm32-h407/src/stm32_adc.c | 10 +- .../olimex-stm32-h407/src/stm32_autoleds.c | 4 +- .../stm32/olimex-stm32-h407/src/stm32_boot.c | 12 +- .../olimex-stm32-h407/src/stm32_bringup.c | 10 +- .../stm32/olimex-stm32-h407/src/stm32_sdio.c | 1 + .../olimex-stm32-p107/src/stm32_encx24j600.c | 9 +- .../stm32/olimex-stm32-p207/include/board.h | 43 ++--- .../stm32/olimex-stm32-p207/src/stm32_adc.c | 11 +- .../olimex-stm32-p207/src/stm32_appinit.c | 4 +- .../olimex-stm32-p207/src/stm32_autoleds.c | 13 +- .../stm32/olimex-stm32-p207/src/stm32_boot.c | 14 +- .../stm32/olimex-stm32-p407/src/stm32_adc.c | 11 +- .../olimex-stm32-p407/src/stm32_autoleds.c | 13 +- .../stm32/olimex-stm32-p407/src/stm32_sram.c | 106 +++++++----- boards/arm/stm32/photon/src/stm32_spi.c | 48 +++--- boards/arm/stm32/shenzhou/include/board.h | 86 +++++----- boards/arm/stm32/shenzhou/src/stm32_adc.c | 18 +- boards/arm/stm32/shenzhou/src/stm32_appinit.c | 5 +- .../arm/stm32/shenzhou/src/stm32_autoleds.c | 33 ++-- boards/arm/stm32/shenzhou/src/stm32_chipid.c | 4 +- boards/arm/stm32/shenzhou/src/stm32_mmcsd.c | 3 +- boards/arm/stm32/shenzhou/src/stm32_spi.c | 44 ++--- boards/arm/stm32/shenzhou/src/stm32_ssd1289.c | 64 ++++--- .../stm32/shenzhou/src/stm32_touchscreen.c | 11 +- boards/arm/stm32/shenzhou/src/stm32_usbmsc.c | 3 +- .../arm/stm32/stm3210e-eval/src/stm32_adc.c | 10 +- .../arm/stm32/stm3210e-eval/src/stm32_boot.c | 10 +- .../stm32/stm3210e-eval/src/stm32_bringup.c | 29 ++-- .../stm32/stm3210e-eval/src/stm32_composite.c | 26 +-- .../stm32/stm3210e-eval/src/stm32_djoystick.c | 48 +++--- .../arm/stm32/stm3210e-eval/src/stm32_leds.c | 33 ++-- .../stm32/stm3210e-eval/src/stm32_selectlcd.c | 18 +- .../stm32/stm3210e-eval/src/stm32_selectnor.c | 14 +- .../stm3210e-eval/src/stm32_selectsram.c | 17 +- .../arm/stm32/stm3210e-eval/src/stm32_spi.c | 48 +++--- .../stm32/stm3210e-eval/src/stm32_usbdev.c | 19 ++- .../stm32/stm3210e-eval/src/stm32_usbmsc.c | 16 +- .../arm/stm32/stm3220g-eval/include/board.h | 69 +++++--- .../arm/stm32/stm3220g-eval/src/stm32_adc.c | 12 +- .../stm32/stm3220g-eval/src/stm32_appinit.c | 22 +-- .../stm32/stm3220g-eval/src/stm32_autoleds.c | 26 +-- .../arm/stm32/stm3220g-eval/src/stm32_boot.c | 9 +- .../stm32/stm3220g-eval/src/stm32_extmem.c | 21 ++- .../stm3220g-eval/src/stm32_selectsram.c | 5 +- .../arm/stm32/stm3220g-eval/src/stm32_spi.c | 49 +++--- .../stm32/stm3220g-eval/src/stm32_stmpe811.c | 25 ++- .../arm/stm32/stm3240g-eval/include/board.h | 82 +++++---- .../arm/stm32/stm3240g-eval/src/stm32_adc.c | 11 +- .../stm32/stm3240g-eval/src/stm32_autoleds.c | 26 +-- .../arm/stm32/stm3240g-eval/src/stm32_boot.c | 2 +- .../stm32/stm3240g-eval/src/stm32_extmem.c | 21 ++- .../stm3240g-eval/src/stm32_selectsram.c | 70 ++++---- .../arm/stm32/stm3240g-eval/src/stm32_spi.c | 48 +++--- .../stm32/stm3240g-eval/src/stm32_stmpe811.c | 33 ++-- .../stm32/stm32f103-minimum/src/stm32_adc.c | 10 +- .../stm32/stm32f103-minimum/src/stm32_gpio.c | 26 ++- .../stm32/stm32f3discovery/include/board.h | 66 +++++--- .../stm32/stm32f3discovery/src/stm32_boot.c | 3 +- .../stm32/stm32f3discovery/src/stm32_spi.c | 48 +++--- .../stm32f429i-disco/src/stm32_autoleds.c | 24 ++- .../stm32/stm32f429i-disco/src/stm32_boot.c | 8 +- .../stm32f429i-disco/src/stm32_stmpe811.c | 19 ++- .../stm32f4discovery/src/stm32_autoleds.c | 26 +-- .../stm32/stm32f4discovery/src/stm32_boot.c | 10 +- .../stm32f4discovery/src/stm32_ethernet.c | 1 + .../stm32/stm32f4discovery/src/stm32_extmem.c | 21 ++- .../stm32f4discovery/src/stm32_pca9635.c | 7 +- .../stm32/stm32f4discovery/src/stm32_reset.c | 2 +- .../stm32/stm32f4discovery/src/stm32_sdio.c | 1 + .../stm32f4discovery/src/stm32_ssd1289.c | 31 ++-- .../stm32/stm32f4discovery/src/stm32_usbmsc.c | 1 + .../arm/stm32/stm32ldiscovery/src/stm32_lcd.c | 96 +++++++---- .../arm/stm32/stm32ldiscovery/src/stm32_spi.c | 48 +++--- .../include/board-stm32f103vct6.h | 13 +- .../include/board-stm32f107vct6.h | 8 +- .../stm32/viewtool-stm32f107/include/board.h | 35 ++-- .../viewtool-stm32f107/src/stm32_ads7843e.c | 8 +- .../viewtool-stm32f107/src/stm32_ft80x.c | 7 +- .../viewtool-stm32f107/src/stm32_mmcsd.c | 9 +- .../stm32/viewtool-stm32f107/src/stm32_spi.c | 61 ++++--- .../viewtool-stm32f107/src/stm32_ssd1289.c | 159 ++++++++++-------- .../viewtool-stm32f107/src/stm32_usbdev.c | 26 +-- .../stm32f0l0g0/nucleo-f072rb/include/board.h | 25 +-- .../nucleo-f072rb/src/stm32_boot.c | 9 +- .../stm32f0l0g0/nucleo-f091rc/include/board.h | 17 +- .../nucleo-f091rc/src/stm32_boot.c | 2 +- .../stm32f051-discovery/include/board.h | 47 +++--- .../stm32f051-discovery/src/stm32_boot.c | 2 +- .../stm32f072-discovery/include/board.h | 64 +++---- .../stm32f072-discovery/src/stm32_boot.c | 2 +- boards/arm/stm32f7/nucleo-144/src/stm32_adc.c | 18 +- .../arm/stm32f7/nucleo-144/src/stm32_sdio.c | 2 +- .../arm/stm32f7/stm32f746-ws/src/stm32_spi.c | 66 +++++--- .../stm32f746g-disco/src/stm32_autoleds.c | 4 +- .../stm32f7/stm32f746g-disco/src/stm32_boot.c | 15 +- .../stm32f7/stm32f746g-disco/src/stm32_lcd.c | 7 +- .../stm32f7/stm32f746g-disco/src/stm32_spi.c | 60 ++++--- .../stm32f7/stm32f769i-disco/include/board.h | 44 ++--- .../stm32f769i-disco/src/stm32_autoleds.c | 4 +- .../stm32f7/stm32f769i-disco/src/stm32_spi.c | 60 ++++--- .../stm32h7/nucleo-h743zi/src/stm32_boot.c | 4 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_spi.c | 48 +++--- .../stm32h7/stm32h747i-disco/src/stm32_boot.c | 4 +- .../stm32h7/stm32h747i-disco/src/stm32_spi.c | 4 +- .../include/b-l475e-iot01a_clock.h | 109 +++++++----- .../stm32l4/b-l475e-iot01a/src/stm32_spi.c | 45 ++--- .../stm32l4/b-l475e-iot01a/src/stm32_spirit.c | 6 +- .../stm32l4/nucleo-l432kc/src/stm32_gpio.c | 3 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 31 ++-- .../arm/stm32l4/nucleo-l452re/include/board.h | 11 +- .../nucleo-l452re/include/nucleo-l452re.h | 109 +++++++----- .../arm/stm32l4/nucleo-l452re/src/stm32_spi.c | 48 +++--- .../arm/stm32l4/nucleo-l476rg/include/board.h | 19 ++- .../nucleo-l476rg/include/nucleo-l476rg.h | 99 +++++++---- .../arm/stm32l4/nucleo-l476rg/src/stm32_adc.c | 23 ++- .../nucleo-l476rg/src/stm32_ajoystick.c | 40 +++-- .../stm32l4/nucleo-l476rg/src/stm32_gpio.c | 24 ++- .../arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c | 10 +- .../nucleo-l476rg/src/stm32_qencoder.c | 4 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 50 +++--- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 46 +++-- .../stm32l4/nucleo-l496zg/src/stm32_sdio.c | 2 +- .../stm32l476-mdk/src/stm32_autoleds.c | 19 ++- .../arm/stm32l4/stm32l476-mdk/src/stm32_spi.c | 43 +++-- .../stm32l4/stm32l476vg-disco/src/stm32_spi.c | 44 +++-- .../stm32l4/stm32l4r9ai-disco/include/board.h | 32 ++-- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 23 ++- .../stm32l4/stm32l4r9ai-disco/src/stm32_spi.c | 50 +++--- 173 files changed, 2716 insertions(+), 1833 deletions(-) diff --git a/boards/arm/kinetis/teensy-3.x/src/k20_pwm.c b/boards/arm/kinetis/teensy-3.x/src/k20_pwm.c index 5f9d02d9926..6d4b603d28b 100644 --- a/boards/arm/kinetis/teensy-3.x/src/k20_pwm.c +++ b/boards/arm/kinetis/teensy-3.x/src/k20_pwm.c @@ -75,7 +75,9 @@ int kinetis_pwm_setup(void) if (!initialized) { #ifdef CONFIG_KINETIS_FTM0_PWM - /* Call kinetis_pwminitialize() to get an instance of the PWM interface */ + /* Call kinetis_pwminitialize() to get an instance of + * the PWM interface + */ pwm = kinetis_pwminitialize(0); if (!pwm) diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c index 82164f144ca..2f52a773a61 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c @@ -77,11 +77,17 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN10}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c b/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c index e3f8e3c4468..ba9cf752da1 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c @@ -90,8 +90,8 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_CLICKER2_STM32_SYSLOG_FILE - /* Delay some time for the automounter to finish mounting before bringing up - * file syslog. + /* Delay some time for the automounter to finish mounting before + * bringing up file syslog. */ nxsig_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c index 32c899714ac..07a062648a1 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c @@ -145,7 +145,7 @@ static void board_led2_off(int led) return; } - stm32_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); } /**************************************************************************** @@ -158,10 +158,10 @@ static void board_led2_off(int led) void board_autoled_initialize(void) { - /* Configure LED1-2 GPIOs for output */ + /* Configure LED1-2 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c index b7c879e9e1e..cd45aaf69f8 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c @@ -40,17 +40,18 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32_boardinitialize(void) { #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ if (stm32_spidev_initialize) @@ -60,10 +61,10 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usb_configure() has been brought - * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usb_configure() has been + * brought into the build. Presumeably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. */ stm32_usb_configure(); @@ -88,7 +89,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32/clicker2-stm32/src/stm32_can.c index 63bf6ea72b3..a79540222d9 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_can.c @@ -39,7 +39,8 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ********************************************************************/ + +/* Configuration ************************************************************/ #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) # warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c index 25ffa02d661..f4f9931722a 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c @@ -90,7 +90,7 @@ struct stm32_priv_s * varying boards and MCUs. * * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - interrupt + * interrupt * irq_enable - Enable or disable the GPIO interrupt */ @@ -217,7 +217,7 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv) /* Configure the interrupt pin */ - stm32_configgpio(priv->intcfg); + stm32_configgpio(priv->intcfg); /* Initialize the SPI bus and get an instance of the SPI interface */ @@ -269,7 +269,8 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv) ret = mac802154dev_register(mac, 0); if (ret < 0) { - wlerr("ERROR: Failed to register the MAC character driver /dev/ieee%d: %d\n", + wlerr("ERROR:"); + wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", 0, ret); return ret; } diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c index b674d34ff74..003c7cfc578 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c @@ -48,7 +48,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 STM32 board. + * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 + * STM32 board. * ****************************************************************************/ @@ -70,31 +71,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -104,14 +108,17 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); switch (devid) { #ifdef CONFIG_IEEE802154_MRF24J40 case SPIDEV_IEEE802154(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB2_CS, !selected); @@ -119,6 +126,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) #endif #ifdef CONFIG_IEEE802154_XBEE case SPIDEV_IEEE802154(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB2_CS, !selected); @@ -126,6 +134,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) #endif #ifdef CONFIG_MMCSD_SPI case SPIDEV_MMCSD(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB2_CS, !selected); @@ -152,14 +161,17 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); switch (devid) { #ifdef CONFIG_IEEE802154_MRF24J40 case SPIDEV_IEEE802154(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB1_CS, !selected); @@ -167,6 +179,7 @@ void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) #endif #ifdef CONFIG_IEEE802154_XBEE case SPIDEV_IEEE802154(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB1_CS, !selected); @@ -174,6 +187,7 @@ void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) #endif #ifdef CONFIG_MMCSD_SPI case SPIDEV_MMCSD(0): + /* Set the GPIO low to select and high to de-select */ stm32_gpiowrite(GPIO_MB1_CS, !selected); diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c index 43bcab2ec7f..5debd1f2247 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c @@ -53,15 +53,17 @@ * Name: stm32_usb_configure * * Description: - * Called from stm32_boardinitialize very early in inialization to setup USB-related - * GPIO pins for the Olimex STM32 P407 board. + * Called from stm32_boardinitialize very early in inialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. * ****************************************************************************/ void stm32_usb_configure(void) { #ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ /* Configure the OTG FS VBUS sensing GPIO */ @@ -73,10 +75,11 @@ void stm32_usb_configure(void) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/fire-stm32v2/include/board.h b/boards/arm/stm32/fire-stm32v2/include/board.h index e97b4ccc262..669ff268aec 100644 --- a/boards/arm/stm32/fire-stm32v2/include/board.h +++ b/boards/arm/stm32/fire-stm32v2/include/board.h @@ -37,7 +37,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* HSI - 8 MHz RC factory-trimmed * LSI - 40 KHz RC (30-60KHz, uncalibrated) @@ -52,7 +52,10 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, + * PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -102,7 +105,8 @@ /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 */ + * Note: TIM1,8 are on APB2, others on APB1 + */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY @@ -143,12 +147,15 @@ # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* LED definitions ******************************************************************/ -/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. These LEDs are not - * used by the NuttX port unless CONFIG_ARCH_LEDS is defined. In that case, the - * usage by the board port is defined in include/board.h and src/up_autoleds.c. +/* LED definitions **********************************************************/ + +/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. + * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/up_autoleds.c. * The LEDs are used to encode OS-related events as follows: */ + /* LED1 LED2 LED3 */ #define LED_STARTED 0 /* OFF OFF OFF */ #define LED_HEAPALLOCATE 1 /* ON OFF OFF */ @@ -170,12 +177,13 @@ #define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) #define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) -/* Pin Remapping ********************************************************************/ +/* Pin Remapping ************************************************************/ + /* USB 2.0 * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 70 PA11 PA11-USBDM USB2.0 * 71 PA12 PA12-USBDP USB2.0 @@ -184,13 +192,16 @@ /* 2.4" TFT + Touchscreen * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen @@ -227,9 +238,9 @@ /* AT24C02 * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 @@ -241,9 +252,9 @@ /* Potentiometer/ADC * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) * 24 PA1 PC1/ADC123-IN1 @@ -251,14 +262,18 @@ /* USARTs * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * - * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, Requires !CONFIG_STM32_USART1_REMAP - * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, Requires !CONFIG_STM32_USART1_REMAP - * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, Requires !CONFIG_STM32_USART2_REMAP - * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, Requires !CONFIG_STM32_USART2_REMAP + * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP + * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP */ #if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) @@ -271,14 +286,17 @@ /* 2MBit SPI FLASH * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH */ #if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) @@ -287,14 +305,17 @@ /* ENC28J60 * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt */ @@ -305,9 +326,9 @@ /* MP3 * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 48 PB11 PB11-MP3-RST MP3 * 51 PB12 PB12-SPI2-NSS MP3 @@ -320,9 +341,9 @@ /* SD Card * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 65 PC8 PC8-SDIO-D0 SD card, pulled high * 66 PC9 PC9-SDIO-D1 SD card, pulled high @@ -334,9 +355,9 @@ /* CAN * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 95 PB8 PB8-CAN-RX CAN transceiver, Header 2H * 96 PB9 PB9-CAN-TX CAN transceiver, Header 2H @@ -369,10 +390,11 @@ extern "C" * Name: fire_lcdclear * * Description: - * This is a non-standard LCD interface just for the M3 Wildfire board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the M3 Wildfire board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c b/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c index 03e8f148c5b..12d61b6e79c 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_appinit.c @@ -39,6 +39,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* Assume that we support everything until convinced otherwise */ @@ -48,6 +49,7 @@ #define HAVE_W25 1 /* Configuration ************************************************************/ + /* SPI1 connects to the SD CARD (and to the SPI FLASH) */ #define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c index 55084040450..e4bce7e6fbc 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c @@ -135,19 +135,19 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_FLASH_ON_SETBITS | LED_FLASH_ON_CLRBITS | - LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) + LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) }; #ifdef CONFIG_PM @@ -248,35 +248,30 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Restore normal LEDs operation */ - } break; case(PM_IDLE): { /* Entering IDLE mode - Turn leds off */ - } break; case(PM_STANDBY): { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } break; default: { /* Should not get here */ - } break; } @@ -318,11 +313,11 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_ARCH_LEDS void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); } /**************************************************************************** @@ -354,7 +349,7 @@ void up_ledpminitialize(void) int ret = pm_register(&g_ledscb); if (ret != OK) - { + { board_autoled_on(LED_ASSERTION); } } diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c index 03fe3fb1991..97aa97682b0 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c @@ -48,16 +48,17 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32_boardinitialize(void) { - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) @@ -68,8 +69,8 @@ void stm32_boardinitialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c index 80eefab9185..84bd62075ed 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c @@ -20,14 +20,17 @@ /* 2MBit SPI FLASH OR ENC28J60 * - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH */ /**************************************************************************** @@ -57,17 +60,22 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* ENC28J60 * - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt */ @@ -179,17 +187,19 @@ void arm_netinitialize(void) /* Assumptions: * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in boot-up. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. */ spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); if (!spi) { - nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO); + nerr("ERROR: Failed to initialize SPI port %d\n", + ENC28J60_SPI_PORTNO); return; } - /* Take ENC28J60 out of reset (active low)*/ + /* Take ENC28J60 out of reset (active low) */ stm32_gpiowrite(GPIO_ENC28J60_RESET, true); diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c index 20acf5b053c..dc2994d84c7 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c @@ -37,6 +37,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #define HAVE_MMCSD 1 /* Assume that we have SD support */ @@ -89,16 +90,17 @@ int stm32_sdinitialize(int minor) ret = mmcsd_slotinitialize(minor, sdio); if (ret != OK) { - ferr("ERROR: Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + ferr("ERROR:"); + ferr(" Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", STM32_MMCSDSLOTNO, minor); } finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", STM32_MMCSDSLOTNO, minor); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the M3 Wildfire board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the M3 Wildfire board supports a GPIO to + * detect if there is a card in the slot. */ sdio_mediachange(sdio, true); diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c index 69a8b45d7fd..aa3c0ea7e11 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c @@ -58,13 +58,16 @@ /* 2.4" TFT + Touchscreen. FSMC Bank1 * - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen @@ -90,7 +93,9 @@ * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen * - * NOTE: SPI and I2C pin configuration is controlled in the SPI and I2C drivers, respectively. + * NOTE: + * SPI and I2C pin configuration is controlled in the SPI and I2C drivers, + * respectively. */ static const uint16_t g_lcdconfig[NCOMMON_CONFIG] = @@ -159,14 +164,17 @@ void stm32_selectlcd(void) /* Bank1 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| - FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); putreg32(0xffffffff, STM32_FSMC_BWTR4); /* Enable the bank by setting the MBKEN bit */ - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); leave_critical_section(flags); } diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c index 92a72a29357..f2cb850274f 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c @@ -94,31 +94,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #if 0 /* Need to study this */ if (devid == SPIDEV_LCD) @@ -153,9 +156,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_AUDIO) { diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c index 4f2e23fbabd..60971d3ac8a 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c @@ -69,11 +69,12 @@ void stm32_usbinitialize(void) * Name: stm32_usbpullup * * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be - * NULL. + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined + * to be NULL. * ****************************************************************************/ @@ -90,10 +91,11 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c index 762c6adc8f6..c54c06257c2 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c +++ b/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c @@ -57,7 +57,8 @@ int board_usbmsc_initialize(int port) { /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized in board_app_initialize() (see stm32_appinit.c). + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). * In this case, there is nothing further to be done here. */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c b/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c index 045541f04db..4ddc445277f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c @@ -68,8 +68,8 @@ #define NSH_HAVEMMCSD 1 -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support - * is not enabled. +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. */ #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) @@ -193,7 +193,9 @@ int board_app_initialize(uintptr_t arg) ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); if (ret != OK) { - syslog(LOG_ERR, "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); return ret; } diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c index d76dd5b0f2c..3ec2de13fce 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c @@ -61,6 +61,7 @@ void stm32_usbinitialize(void) uinfo("called\n"); /* USB Soft Connect Pullup */ + stm32_configgpio(GPIO_USB_PULLUP); } @@ -68,11 +69,12 @@ void stm32_usbinitialize(void) * Name: stm32_usbpullup * * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be - * NULL. + * If USB is supported and the board supports a pullup via GPIO + * (for USB software connect and disconnect), then the board software must + * provide stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can + * be redefined to be NULL. * ****************************************************************************/ @@ -87,10 +89,11 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c index 1a0fb0815dc..fc5c6d376e4 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c @@ -54,7 +54,8 @@ # undef STM32_MMCSDSLOTNO # define STM32_MMCSDSLOTNO 0 #else - /* Add configuration for new STM32 boards here */ +/* Add configuration for new STM32 boards here */ + # error "Unrecognized STM32 board" #endif @@ -73,7 +74,8 @@ int board_usbmsc_initialize(int port) { /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized in board_app_initialize() (see stm32_appinit.c). + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). * In this case, there is nothing further to be done here. */ @@ -95,7 +97,7 @@ int board_usbmsc_initialize(int port) /* Now bind the SDIO interface to the MMC/SD driver */ - syslog(LOG_INFO,"Bind SDIO to the MMC/SD driver, minor=%d\n", + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", CONFIG_SYSTEM_USBMSC_DEVMINOR1); ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); @@ -109,16 +111,16 @@ int board_usbmsc_initialize(int port) syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the Hy-Mini STM32v board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the Hy-Mini STM32v board supports a GPIO to + * detect if there is a card in the slot. */ - sdio_mediachange(sdio, true); + sdio_mediachange(sdio, true); #endif /* CONFIG_NSH_BUILTIN_APPS */ - return OK; + return OK; } #endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/mikroe-stm32f4/include/board.h b/boards/arm/stm32/mikroe-stm32f4/include/board.h index f357e37ac42..2b39d9fd5fc 100644 --- a/boards/arm/stm32/mikroe-stm32f4/include/board.h +++ b/boards/arm/stm32/mikroe-stm32f4/include/board.h @@ -39,29 +39,30 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ -/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. The main - * clock uses the internal 16Mhz RC oscillator. +/* Clocking *****************************************************************/ + +/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. + * The main clock uses the internal 16Mhz RC oscillator. * * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (STM32_HSI_FREQUENCY) - * PLLM : 16 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock + * System Clock source :PLL (HSE) + * SYSCLK(Hz) :168000000 Determined by PLL configuration + * HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler :1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY) + * PLLM :16 (STM32_PLLCFG_PLLM) + * PLLN :36 (STM32_PLLCFG_PLLN) + * PLLP :2 (STM32_PLLCFG_PLLP) + * PLLQ :7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) :5 + * Prefetch Buffer :OFF + * Instruction cache :ON + * Data cache :ON + * Require 48MHz for USB OTG FS, :Enabled + * SDIO and RNG clock */ /* HSI - 16 MHz RC factory-trimmed @@ -147,9 +148,10 @@ #define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -175,8 +177,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * stm32f4discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, + * then NuttX will control the 4 LEDs on board the stm32f4discovery. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -188,7 +191,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The STM32F4 Discovery supports one button: */ #define BUTTON_USER 0 @@ -199,12 +203,12 @@ #endif /* 0 */ -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* UART2: * - * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out UART2 - * to the expansion header. + * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out + * UART2 to the expansion header. * (See the README.txt file for other options) */ @@ -213,8 +217,8 @@ /* PWM * - * The STM32F4 Discovery has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM4 CH2 on PD13. + * The STM32F4 Discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2 on PD13. */ #define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2 diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c index 18ae0eeebde..0864f570add 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c @@ -56,7 +56,9 @@ void stm32_boardinitialize(void) { - /* First reset the VS1053 since it tends to produce noise out of power on reset */ + /* First reset the VS1053 since it tends to produce noise out of power on + * reset + */ #ifdef CONFIG_AUDIO_VS1053 stm32_configgpio(GPIO_VS1053_RST); @@ -68,8 +70,8 @@ void stm32_boardinitialize(void) stm32_lcdinitialize(); #endif - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) @@ -79,10 +81,10 @@ void stm32_boardinitialize(void) } #endif - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumeably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. */ #ifdef CONFIG_STM32_OTGFS diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c index d3f563243ae..131b7fd82d0 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c @@ -60,18 +60,25 @@ static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = { - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, GPIO_FSMC_A24, GPIO_FSMC_A25 }; static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = { - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 }; /**************************************************************************** diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c index 9043ef5256f..7bfe030de03 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c +++ b/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c @@ -41,9 +41,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -66,12 +67,13 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. * ****************************************************************************/ @@ -79,7 +81,9 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ stm32_bringup(); #endif diff --git a/boards/arm/stm32/nucleo-f303re/include/board.h b/boards/arm/stm32/nucleo-f303re/include/board.h index 315c0917b57..2d76eeb389d 100644 --- a/boards/arm/stm32/nucleo-f303re/include/board.h +++ b/boards/arm/stm32/nucleo-f303re/include/board.h @@ -73,7 +73,10 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, + * PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -140,6 +143,7 @@ #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ + /* The Nucleo F303RE board has three LEDs. Two of these are controlled by * logic on the board and are not available for software control: * @@ -193,6 +197,7 @@ #define LED_PANIC 1 /* Button definitions *******************************************************/ + /* The Nucleo F303RE supports two buttons; only one button is controllable * by software: * @@ -207,6 +212,7 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) /* Alternate function pin selections ****************************************/ + /* CAN */ #define GPIO_CAN1_RX GPIO_CAN_RX_2 @@ -239,6 +245,7 @@ #define GPIO_USART2_TX GPIO_USART2_TX_2 /* DMA channels *************************************************************/ + /* ADC */ #define ADC1_DMA_CHAN DMACHAN_ADC1 diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c index fc423470631..952b914a7d9 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c +++ b/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c @@ -61,12 +61,13 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. * ****************************************************************************/ @@ -74,7 +75,9 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ stm32_bringup(); #endif diff --git a/boards/arm/stm32/nucleo-f410rb/include/board.h b/boards/arm/stm32/nucleo-f410rb/include/board.h index ce9261d8789..3b853883d47 100644 --- a/boards/arm/stm32/nucleo-f410rb/include/board.h +++ b/boards/arm/stm32/nucleo-f410rb/include/board.h @@ -38,26 +38,27 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ -/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). However, as - * shipped, the X3 crystals is not populated. Therefore the Nucleo-F410RB - * will need to run off the 16MHz HSI clock. +/* Clocking *****************************************************************/ + +/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X3 crystals is not populated. + * Therefore the Nucleo-F410RB will need to run off the 16MHz HSI clock. * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 100000000 Determined by PLL configuration - * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 2 (STM32_PLLCFG_PLLM) - * PLLN : 50 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 100000000 Determined by PLL configuration + * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 2 (STM32_PLLCFG_PLLM) + * PLLN : 50 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON */ /* HSI - 16 MHz RC factory-trimmed @@ -74,10 +75,14 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, 50 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 50 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 * * We will configure like this * @@ -113,6 +118,7 @@ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB1 will be twice PCLK1 */ + /* REVISIT */ #define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -124,6 +130,7 @@ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) /* Timers driven from APB2 will be PCLK2 */ + /* REVISIT */ #define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) @@ -134,6 +141,7 @@ * otherwise frequency is 2xAPBx. * Note: TIM1,9,11 are on APB2, others on APB1 */ + /* REVISIT */ #define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN @@ -142,9 +150,10 @@ #define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN #define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN -/* DMA Channel/Stream Selections ****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * is we set aside more DMA channels/streams. +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. */ #define ADC1_DMA_CHAN DMAMAP_ADC1_1 @@ -155,7 +164,7 @@ #define DMACHAN_SPI2_RX DMAMAP_SPI2_RX #define DMACHAN_SPI2_TX DMAMAP_SPI2_TX -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* USART1: * RXD: PA10 CN9 pin 3, CN10 pin 33 @@ -284,7 +293,8 @@ /* Buttons * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 * microcontroller. */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c index 5fdb6a0c0e3..c4e750c7dbc 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c @@ -18,7 +18,7 @@ * ****************************************************************************/ -/* This file provides contents of an optional ROMFS volume, mounted at boot /* +/* This file provides contents of an optional ROMFS volume, mounted at boot */ /**************************************************************************** * Included Files diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c index 3c83c5f0c70..fbe0d88bf77 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c @@ -99,13 +99,16 @@ * Private Function Prototypes ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, FAR struct ajoy_sample_s *sample); -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); -static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, FAR void *arg); +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); +static void +ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, FAR void *arg); static void ajoy_disable(void); static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); @@ -113,6 +116,7 @@ static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data ****************************************************************************/ + /* Pin configuration for each Itead joystick button. Index using AJOY_* * button definitions in include/nuttx/input/ajoystick.h. */ @@ -163,7 +167,8 @@ static FAR void *g_ajoyarg; * ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) { iinfo("Supported: %02x\n", AJOY_SUPPORTED); return (ajoy_buttonset_t)AJOY_SUPPORTED; @@ -278,7 +283,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * ****************************************************************************/ -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) { ajoy_buttonset_t ret = 0; int i; diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c index f8c1e0a83b3..41348fc5def 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c +++ b/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c @@ -20,7 +20,7 @@ /**************************************************************************** * Included Files - ***************************************************************************/ + ****************************************************************************/ #include @@ -43,7 +43,7 @@ /**************************************************************************** * Public Data - ***************************************************************************/ + ****************************************************************************/ /* Global driver instances */ @@ -56,7 +56,7 @@ struct spi_dev_s *g_spi2; /**************************************************************************** * Public Functions - ***************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: stm32_spidev_initialize @@ -65,7 +65,7 @@ struct spi_dev_s *g_spi2; * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and * Nucleo-F411RE boards. * - ***************************************************************************/ + ****************************************************************************/ void weak_function stm32_spidev_initialize(void) { @@ -107,8 +107,8 @@ void weak_function stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to diff --git a/boards/arm/stm32/nucleo-f4x1re/include/board.h b/boards/arm/stm32/nucleo-f4x1re/include/board.h index f93d1c5e5d6..ef11d9ad520 100644 --- a/boards/arm/stm32/nucleo-f4x1re/include/board.h +++ b/boards/arm/stm32/nucleo-f4x1re/include/board.h @@ -30,11 +30,7 @@ # include #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32F401RE) # include @@ -42,9 +38,14 @@ # include #endif -/* DMA Channel/Stream Selections ****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * is we set aside more DMA channels/streams. +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. * * SDIO DMA *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA @@ -60,7 +61,7 @@ #define DMACHAN_SPI2_RX DMAMAP_SPI2_RX #define DMACHAN_SPI2_TX DMAMAP_SPI2_TX -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* USART1: * RXD: PA10 CN9 pin 3, CN10 pin 33 @@ -190,7 +191,8 @@ /* Buttons * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 * microcontroller. */ diff --git a/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h b/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h index 33ff67bd580..d4f17d3a12c 100644 --- a/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h +++ b/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h @@ -74,10 +74,14 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 * * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. * Some possible solutions include: @@ -123,6 +127,7 @@ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB1 will be twice PCLK1 */ + /* REVISIT */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -141,6 +146,7 @@ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ + /* REVISIT */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -153,6 +159,7 @@ * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ + /* REVISIT */ #define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) @@ -171,6 +178,7 @@ * * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */ + /* REVISIT */ #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) @@ -178,6 +186,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA @@ -189,6 +198,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA diff --git a/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f411re.h b/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f411re.h index 9d378c44988..4057b59c0d9 100644 --- a/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f411re.h +++ b/boards/arm/stm32/nucleo-f4x1re/include/nucleo-f411re.h @@ -74,14 +74,19 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 * * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=104MHz and we must have the USB clock= 48MHz. + * so we would like to have SYSYCLK=104MHz and we must have + * the USB clock= 48MHz. * * PLLQ = 13 PLLP = 6 PLLN=390 PLLM=10 * @@ -119,6 +124,7 @@ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB1 will be twice PCLK1 */ + /* REVISIT */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -137,6 +143,7 @@ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ + /* REVISIT */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -149,6 +156,7 @@ * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ + /* REVISIT */ #define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) @@ -167,6 +175,7 @@ * * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */ + /* REVISIT */ #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) @@ -174,6 +183,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA @@ -185,6 +195,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_adc.c index 26e380d959c..3bb66a25696 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_adc.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_adc.c @@ -55,28 +55,41 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* Identifying number of each ADC channel. */ #ifdef CONFIG_AJOYSTICK #ifdef CONFIG_ADC_DMA /* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = {0, 1}; +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0, GPIO_ADC1_IN0}; +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, GPIO_ADC1_IN0 +}; #else /* Without DMA, only a single channel can be supported */ /* The Itead analog joystick gets input on ADC_IN0 */ -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = {0}; +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0}; +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0 +}; #endif /* CONFIG_ADC_DMA */ #endif /* CONFIG_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c index 7097e47431b..aac34e81f88 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c @@ -42,6 +42,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Check for pre-requisites and pin conflicts */ #ifdef CONFIG_AJOYSTICK @@ -98,10 +99,12 @@ * Private Function Prototypes ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, FAR struct ajoy_sample_s *sample); -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, ajoy_buttonset_t press, ajoy_buttonset_t release, ajoy_handler_t handler, FAR void *arg); @@ -112,6 +115,7 @@ static int ajoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data ****************************************************************************/ + /* Pin configuration for each Itead joystick button. Index using AJOY_* * button definitions in include/nuttx/input/ajoystick.h. */ @@ -162,7 +166,8 @@ static FAR void *g_ajoyarg; * ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) { iinfo("Supported: %02x\n", AJOY_SUPPORTED); return (ajoy_buttonset_t)AJOY_SUPPORTED; @@ -277,7 +282,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * ****************************************************************************/ -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) { ajoy_buttonset_t ret = 0; int i; @@ -343,26 +349,26 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, for (i = 0; i < AJOY_NGPIOS; i++) { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); - iinfo("GPIO %d: rising: %d falling: %d\n", + iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32_gpiosetevent(g_joygpio[i], rising, falling, + stm32_gpiosetevent(g_joygpio[i], rising, falling, true, ajoy_interrupt, NULL); - } + } } } @@ -439,6 +445,7 @@ int board_ajoy_initialize(void) iinfo("Initialize ADC driver: /dev/adc0\n"); /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ + /* Open the ADC driver for reading. */ ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_spi.c index e150a41e1a1..d3bce1159b6 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_spi.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_spi.c @@ -108,12 +108,12 @@ void weak_function stm32_spidev_initialize(void) * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in - * your board-specific logic. These functions will perform chip + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c index 566b0e01fbb..089a54729e5 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c @@ -80,16 +80,24 @@ */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; /* Configurations of pins used byte each ADC channels * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, - * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, - * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c index b908a4955cd..a80212ebb3c 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c @@ -49,9 +49,9 @@ void board_autoled_initialize(void) { - /* Configure LED_STATUS GPIO for output */ + /* Configure LED_STATUS GPIO for output */ - stm32_configgpio(GPIO_LED_STATUS); + stm32_configgpio(GPIO_LED_STATUS); } /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c index 724cf6f377b..b72b9683895 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c @@ -39,7 +39,7 @@ /**************************************************************************** * Public Functions - ***************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: stm32_boardinitialize @@ -55,9 +55,10 @@ void stm32_boardinitialize(void) { #if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV is also selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumeably either CONFIG_USBDEV is also + * selected. */ if (stm32_usbinitialize) @@ -85,7 +86,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/olimex-stm32-h405/include/board.h b/boards/arm/stm32/olimex-stm32-h405/include/board.h index 9bd62008b59..d287abee6b9 100644 --- a/boards/arm/stm32/olimex-stm32-h405/include/board.h +++ b/boards/arm/stm32/olimex-stm32-h405/include/board.h @@ -84,7 +84,7 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) -/* Timers driven from APB1 will be twice PCLK1 (60Mhz)*/ +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -101,7 +101,7 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* Timers driven from APB2 will be twice PCLK2 (120Mhz)*/ +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -123,9 +123,11 @@ #define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status LED in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -137,8 +139,9 @@ #define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of the - * Olimex STM32-H405. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-H405. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED_STATUS on */ @@ -150,7 +153,8 @@ #define LED_ASSERTION 6 /* LED_STATUS off */ #define LED_PANIC 7 /* LED_STATUS blinking */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The Olimex STM32-H405 supports one buttons: */ #define BUTTON_BUT 0 @@ -158,19 +162,20 @@ #define BUTTON_BUT_BIT (1 << BUTTON_BUT) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ -//USART3: -#define GPIO_USART3_RX GPIO_USART3_RX_1 //PB11 -#define GPIO_USART3_TX GPIO_USART3_TX_1 //PB10 -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 //PB13 -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 //PB14 +/* USART3: */ + +#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */ +#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ /* CAN: */ -#define GPIO_CAN1_RX GPIO_CAN1_RX_2 //PB8 -#define GPIO_CAN1_TX GPIO_CAN1_TX_2 //PB9 -#define GPIO_CAN2_RX GPIO_CAN1_RX_2 //PB5 -#define GPIO_CAN2_TX GPIO_CAN1_TX_2 //PB6 +#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ +#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */ +#define GPIO_CAN2_RX GPIO_CAN1_RX_2 /* PB5 */ +#define GPIO_CAN2_TX GPIO_CAN1_TX_2 /* PB6 */ #endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c index 068912bd16f..cceafebb95e 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c +++ b/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c @@ -41,7 +41,8 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ + /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 @@ -68,6 +69,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 * ADC123_IN10 */ @@ -75,19 +77,31 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1};/*, 2, 3, - 4, 5, 6, - 7, 8, 9, - 10, 11, 12, - 13, 15};*/ +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; +/* , 2, 3, + * 4, 5, 6, + * 7, 8, 9, + * 10, 11, 12, + * 13, 15 + * }; + */ /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1};/*, GPIO_ADC1_IN2, GPIO_ADC1_IN3, - GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, - GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, - GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - GPIO_ADC1_IN13, GPIO_ADC1_IN15};*/ +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; +/* , GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15 + * }; + */ #endif /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c index 9e65ce35c27..c18bbd341ea 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c +++ b/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c @@ -46,9 +46,9 @@ void board_autoled_initialize(void) { - /* Configure LED_STATUS GPIO for output */ + /* Configure LED_STATUS GPIO for output */ - stm32_configgpio(GPIO_LED_STATUS); + stm32_configgpio(GPIO_LED_STATUS); } /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c index d045c5284dc..f7b2ea7d2df 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c @@ -49,9 +49,10 @@ void stm32_boardinitialize(void) { - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV is also selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumeably either CONFIG_USBDEV is also + * selected. */ #ifdef CONFIG_STM32_OTGFS @@ -80,7 +81,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_intitialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. @@ -91,8 +92,8 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. + * alternative NSH initialization is necessary when NSH is ran in + * user-space but the initialization function must run in kernel space. */ #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c index 6a27e6eea3b..d5ed9753f4c 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c @@ -80,7 +80,10 @@ */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; /* Configurations of pins used byte each ADC channels * @@ -90,7 +93,10 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c index 7b1f316b6ac..526a68c0462 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c @@ -49,9 +49,9 @@ void board_autoled_initialize(void) { - /* Configure LED_STATUS GPIO for output */ + /* Configure LED_STATUS GPIO for output */ - stm32_configgpio(GPIO_LED_STATUS); + stm32_configgpio(GPIO_LED_STATUS); } /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c index 6ef90cc10c0..2efa47e4ec1 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c @@ -52,9 +52,10 @@ void stm32_boardinitialize(void) { #if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumeably either CONFIG_USBDEV is also selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumeably either CONFIG_USBDEV is also selected. */ if (stm32_usbinitialize) @@ -82,7 +83,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_intitialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. @@ -93,7 +94,8 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { #ifndef CONFIG_LIB_BOARDCTL - /* Perform NSH initialization here instead of from the board_app_initialize. + /* Perform NSH initialization here instead of from the + * board_app_initialize. * If CONFIG_LIB_BOARDCTL=y we assume that come application will perform * the initialization by calling board_app_initialize indirectly through * boardctl(). diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c index b223284bcab..7cc5dc6455c 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c @@ -42,8 +42,9 @@ #include "stm32.h" #include "olimex-stm32-h407.h" -/* Conditional logic in olimex-stm32-h407.h will determine if certain features - * are supported. Tests for these features need to be made after including +/* Conditional logic in olimex-stm32-h407.h will determine if certain + * features are supported. + * Tests for these features need to be made after including * olimex-stm32-h407.h. */ @@ -114,8 +115,9 @@ int stm32_bringup(void) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor for USB + * connection and disconnection events. */ ret = stm32_usbhost_initialize(); diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c index 4d407761419..757705717a5 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c +++ b/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c @@ -119,6 +119,7 @@ int stm32_sdio_initialize(void) #endif /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c index 4e8cdc52ddf..984b21720eb 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c @@ -170,14 +170,17 @@ void arm_netinitialize(void) int ret; /* Assumptions: - * 1) ENCX24J600 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in boot-up. + * 1) ENCX24J600 pins were configured in up_spi.c early in the boot-up + * phase. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. */ spi = stm32_spibus_initialize(ENCX24J600_SPI_PORTNO); if (!spi) { - nerr("ERROR: Failed to initialize SPI port %d\n", ENCX24J600_SPI_PORTNO); + nerr("ERROR: Failed to initialize SPI port %d\n", + ENCX24J600_SPI_PORTNO); return; } diff --git a/boards/arm/stm32/olimex-stm32-p207/include/board.h b/boards/arm/stm32/olimex-stm32-p207/include/board.h index 8d87b2dcb4b..af8c80838a7 100644 --- a/boards/arm/stm32/olimex-stm32-p207/include/board.h +++ b/boards/arm/stm32/olimex-stm32-p207/include/board.h @@ -84,7 +84,7 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) -/* Timers driven from APB1 will be twice PCLK1 (60Mhz)*/ +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -101,7 +101,7 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* Timers driven from APB2 will be twice PCLK2 (120Mhz)*/ +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -123,9 +123,10 @@ #define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -148,8 +149,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * Olimex STM32-P207. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the Olimex STM32-P207. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -161,7 +163,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The Olimex STM32-P207 supports seven buttons: */ #define BUTTON_TAMPER 0 @@ -182,21 +185,21 @@ #define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) #define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ -//USART3: -#define GPIO_USART3_RX GPIO_USART3_RX_3 //PD9 -#define GPIO_USART3_TX GPIO_USART3_TX_3 //PD8 -#define GPIO_USART3_CTS GPIO_USART3_CTS_2 //PD11 -#define GPIO_USART3_RTS GPIO_USART3_RTS_2 //PD12 +/* USART3: */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ -//CAN: -#define GPIO_CAN1_RX GPIO_CAN1_RX_2 //PB8 -#define GPIO_CAN1_TX GPIO_CAN1_TX_2 //PB9 +/* CAN: */ +#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ +#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */ -//Ethernet: -/* - * - PA2 is ETH_MDIO +/* Ethernet: */ + +/* - PA2 is ETH_MDIO * - PC1 is ETH_MDC * - PB5 is ETH_PPS_OUT - NC (not connected) * - PA0 is ETH_MII_CRS - NC diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c index de813491548..5b3cd215f4e 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c +++ b/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c @@ -69,6 +69,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* The Olimex STM32-P207 has a 10 Kohm potentiometer AN_TR connected to PC0 * ADC123_IN10 */ @@ -76,11 +77,17 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN10}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_appinit.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_appinit.c index cdf124845e8..374dee33b6e 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_appinit.c +++ b/boards/arm/stm32/olimex-stm32-p207/src/stm32_appinit.c @@ -141,8 +141,8 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. */ ret = stm32_usbhost_initialize(); diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c index d0ef244b062..7a49f539fd6 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c +++ b/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c @@ -127,12 +127,12 @@ static inline void led_setbits(unsigned int setbits) void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -141,7 +141,8 @@ void board_autoled_initialize(void) void board_autoled_on(int led) { - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); led_setbits(g_ledbits[led]); } diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c index b5ed3dd6e9e..3e228ed4ec2 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c +++ b/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c @@ -49,10 +49,10 @@ void stm32_boardinitialize(void) { - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ #ifdef CONFIG_STM32_OTGFS @@ -81,7 +81,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. @@ -92,8 +92,8 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. + * alternative NSH initialization is necessary when NSH is ran in + * user-space but the initialization function must run in kernel space. */ #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c index cda8b2bf983..ca5d8e57d5f 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c +++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c @@ -69,6 +69,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 * ADC123_IN10 */ @@ -76,11 +77,17 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN10}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c index 6289f319820..36508b22df9 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c +++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c @@ -127,12 +127,12 @@ static inline void led_setbits(unsigned int setbits) void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -141,7 +141,8 @@ void board_autoled_initialize(void) void board_autoled_on(int led) { - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); led_setbits(g_ledbits[led]); } diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c index 2f987038d9a..1c35905b54c 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c +++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c @@ -48,7 +48,8 @@ #endif /* SRAM Timing - * REVIST: These were ported from the STM3240G-EVAL and have not been verified on + * REVIST: + * These were ported from the STM3240G-EVAL and have not been verified on * this platform. */ @@ -67,27 +68,27 @@ * Private Data ****************************************************************************/ -/* GPIOs Configuration ************************************************************** - *---------------------+------------------+------------------+-----------------+ - * GPIO FSMC NOTE |GPIO FSMC NOTE|GPIO FSMC NOTE|GPIO FSMC NOTE| - *---------------------+------------------+------------------+-----------------+ - * PD0 FSMC_D2 |PE0 FSMC_NBL0 |PF0 FSMC_A0 |PG0 FSMC_A10 | - * PD1 FSMC_D3 |PE1 FSMC_NBL1 |PF1 FSMC_A1 |PG1 FSMC_A11 | - * | |PF2 FSMC_A2 |PG2 FSMC_A12 | - * | |PF3 FSMC_A3 |PG3 FSMC_A13 | - * PD4 FSMC_NOE 2 | |PF4 FSMC_A4 |PG4 FSMC_A14 | - * PD5 FSMC_NWE | |PF5 FSMC_A5 |PG5 FSMC_A15 | - * | | | | - * PD7 FSMC_NE1/NCE2 |PE7 FSMC_D4 | | | - * PD8 FSMC_D13 1 |PE8 FSMC_D5 | | | - * PD9 FSMC_D14 1 |PE9 FSMC_D6 | | | - * PD10 FSMC_D15 1 |PE10 FSMC_D7 | | | - * PD11 FSMC_A16 1 |PE11 FSMC_D8 | | | - * PD12 FSMC_A17 |PE12 FSMC_D9 |PF12 FSMC_A6 | | - * |PE13 FSMC_D10 |PF13 FSMC_A7 | | - * PD14 FSMC_D0 |PE14 FSMC_D11 |PF14 FSMC_A8 | | - * PD15 FSMC_D1 |PE15 FSMC_D12 |PF15 FSMC_A9 | | - *---------------------+------------------+------------------+-----------------+ +/* GPIOs Configuration ****************************************************** + *---------------------+------------------+----------------+----------------+ + * GPIO FSMC NOTE |GPIO FSMC NOTE|GPIO FSMC NOTE|GPIO FSMC NOTE| + *---------------------+------------------+----------------+----------------+ + * PD0 FSMC_D2 |PE0 FSMC_NBL0 |PF0 FSMC_A0 |PG0 FSMC_A10 | + * PD1 FSMC_D3 |PE1 FSMC_NBL1 |PF1 FSMC_A1 |PG1 FSMC_A11 | + * | |PF2 FSMC_A2 |PG2 FSMC_A12 | + * | |PF3 FSMC_A3 |PG3 FSMC_A13 | + * PD4 FSMC_NOE 2 | |PF4 FSMC_A4 |PG4 FSMC_A14 | + * PD5 FSMC_NWE | |PF5 FSMC_A5 |PG5 FSMC_A15 | + * | | | | + * PD7 FSMC_NE1/NCE2 |PE7 FSMC_D4 | | | + * PD8 FSMC_D13 1 |PE8 FSMC_D5 | | | + * PD9 FSMC_D14 1 |PE9 FSMC_D6 | | | + * PD10 FSMC_D15 1 |PE10 FSMC_D7 | | | + * PD11 FSMC_A16 1 |PE11 FSMC_D8 | | | + * PD12 FSMC_A17 |PE12 FSMC_D9 |PF12 FSMC_A6 | | + * |PE13 FSMC_D10 |PF13 FSMC_A7 | | + * PD14 FSMC_D0 |PE14 FSMC_D11 |PF14 FSMC_A8 | | + * PD15 FSMC_D1 |PE15 FSMC_D12 |PF15 FSMC_A9 | | + *---------------------+------------------+----------------+----------------+ * * NOTES: * (1) Shared with USART3: PD8=USART3_TX PD9=USART3_RX PD11=USART3_CTS @@ -101,15 +102,21 @@ static const uint32_t g_sramconfig[] = { /* Address configuration: FSMC_A0-FSMC_A17 */ - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, /* Data Configuration: FSMC_D0-FSMC_D15 */ - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 /* Control Signals: * @@ -120,7 +127,8 @@ static const uint32_t g_sramconfig[] = * /BHL = PE1, PSMC_NBL1 */ - GPIO_FSMC_NE1, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1 + GPIO_FSMC_NE1, GPIO_FSMC_NOE, GPIO_FSMC_NWE, + GPIO_FSMC_NBL0, GPIO_FSMC_NBL1 }; #define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) @@ -156,25 +164,26 @@ static void stm32_sramgpios(void) * Name: stm32_stram_configure * * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank - * NOR/SRAM2 base address (0x64000000) + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) * - * General transaction rules. The requested AHB transaction data size can be 8-, - * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple - * transaction rules must be followed: + * General transaction rules. + * The requested AHB transaction data size can be 8-, 16- or 32-bit wide + * whereas the SRAM has a fixed 16-bit data width. Some simple transaction + * rules must be followed: * * Case 1: AHB transaction width and SRAM data width are equal * There is no issue in this case. * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller consecutive - * memory accesses in order to meet the external data width. + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. * Case 3: AHB transaction size is smaller than the memory size. * SRAM supports the byte select feature. * a) FSMC allows write transactions accessing the right data through its * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire memory - * word and uses the needed byte only). The NBL[1:0] are always kept low - * during read transactions. + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. * ****************************************************************************/ @@ -206,23 +215,30 @@ void stm32_stram_configure(void) * Write burst : Disabled */ - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); /* Bank1 NOR/SRAM timing register configuration */ - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | FSMC_BTR_ACCMODA), STM32_FSMC_BTR2); - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ /* Enable the bank */ - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/photon/src/stm32_spi.c b/boards/arm/stm32/photon/src/stm32_spi.c index 8bcb281ff03..e2486c6a7eb 100644 --- a/boards/arm/stm32/photon/src/stm32_spi.c +++ b/boards/arm/stm32/photon/src/stm32_spi.c @@ -55,39 +55,40 @@ void weak_function stm32_spidev_initialize(void) { - - } /**************************************************************************** * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -97,9 +98,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -109,16 +112,17 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) { switch (devid) { - default: break; } diff --git a/boards/arm/stm32/shenzhou/include/board.h b/boards/arm/stm32/shenzhou/include/board.h index 54cab0d0ff7..dce12c0aeac 100644 --- a/boards/arm/stm32/shenzhou/include/board.h +++ b/boards/arm/stm32/shenzhou/include/board.h @@ -94,7 +94,8 @@ #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: +/* MCO output driven by PLL3. + * From above, we already have PLL3 input frequency as: * * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz */ @@ -104,9 +105,10 @@ # define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ #endif -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -124,8 +126,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * STM3240G-EVAL. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -137,7 +140,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The STM3240G-EVAL supports three buttons: */ #define BUTTON_KEY1 0 /* Name printed on board */ @@ -165,16 +169,17 @@ #define NUM_RELAYS 2 -/* Pin selections ******************************************************************/ +/* Pin selections ***********************************************************/ + /* Ethernet * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of these - * RMII_REF_CLK Ethernet PHY signals, the DM916AEP is actually configured - * 25 PA2 MII_MDIO Ethernet PHY to work in RMII mode. - * 48 PB11 MII_TX_EN Ethernet PHY + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in RMII + * 48 PB11 MII_TX_EN Ethernet PHY mode. * 51 PB12 MII_TXD0 Ethernet PHY * 52 PB13 MII_TXD1 Ethernet PHY * 16 PC1 MII_MDC Ethernet PHY @@ -204,9 +209,9 @@ /* USB * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 68 PA9 USB_VBUS MINI-USB-AB. JP3 * 69 PA10 USB_ID MINI-USB-AB. JP5 * 70 PA11 USB_DM MINI-USB-AB @@ -216,9 +221,9 @@ /* UARTS/USARTS * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP @@ -237,20 +242,23 @@ /* SPI * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. */ @@ -264,18 +272,18 @@ /* DAC * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 29 PA4 DAC_OUT1 To CON5(CN14) * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 */ /* ADC * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 @@ -283,9 +291,9 @@ /* CAN * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 91 PB5 CAN2_RX Requires CONFIG_STM32_CAN2_REMAP. * 92 PB6 CAN2_TX Requires CONFIG_STM32_CAN2_REMAP. See also JP11 * 81 PD0 CAN1_RX Requires CONFIG_STM32_CAN1_REMAP2. @@ -302,9 +310,9 @@ /* I2C * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 92 PB6 I2C1_SCL Requires !CONFIG_STM32_I2C1_REMAP * 93 PB7 I2C1_SDA */ @@ -315,9 +323,9 @@ /* I2S * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 51 PB12 I2S_WS GPIO_I2S2_WS. Audio DAC * 52 PB13 I2S_CK GPIO_I2S2_CK. Audio DAC * 54 PB15 I2S_DIN ??? Audio DAC data in. @@ -333,7 +341,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif @@ -346,10 +355,11 @@ extern "C" { * Name: stm32_lcdclear * * Description: - * This is a non-standard LCD interface just for the Shenzhou board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ diff --git a/boards/arm/stm32/shenzhou/src/stm32_adc.c b/boards/arm/stm32/shenzhou/src/stm32_adc.c index 3950b6eebd2..4073e6e6372 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_adc.c +++ b/boards/arm/stm32/shenzhou/src/stm32_adc.c @@ -72,8 +72,8 @@ * Private Data ****************************************************************************/ -/* Identifying number of each ADC channel. The only internal signal for ADC testing - * is the potentiometer input: +/* Identifying number of each ADC channel. + * The only internal signal for ADC testing is the potentiometer input: * * ADC1_IN10(PC0) Potentiometer * @@ -84,11 +84,21 @@ */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; //{10, 8, 9}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* {10, 8, 9}; */ /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_IN10}; //{GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ #endif /**************************************************************************** diff --git a/boards/arm/stm32/shenzhou/src/stm32_appinit.c b/boards/arm/stm32/shenzhou/src/stm32_appinit.c index da21d4307b9..13d49d539e3 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_appinit.c +++ b/boards/arm/stm32/shenzhou/src/stm32_appinit.c @@ -179,8 +179,9 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor + * for USB connection and disconnection events. */ ret = stm32_usbhost_initialize(); diff --git a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32/shenzhou/src/stm32_autoleds.c index a4fbb948edf..2de01b40ae5 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c +++ b/boards/arm/stm32/shenzhou/src/stm32_autoleds.c @@ -130,28 +130,28 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; #ifdef CONFIG_PM @@ -264,35 +264,30 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Restore normal LEDs operation */ - } break; case(PM_IDLE): { /* Entering IDLE mode - Turn leds off */ - } break; case(PM_STANDBY): { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } break; default: { /* Should not get here */ - } break; } @@ -334,12 +329,12 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_ARCH_LEDS void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -371,7 +366,7 @@ void up_ledpminitialize(void) int ret = pm_register(&g_ledscb); if (ret != OK) - { + { board_autoled_on(LED_ASSERTION); } } diff --git a/boards/arm/stm32/shenzhou/src/stm32_chipid.c b/boards/arm/stm32/shenzhou/src/stm32_chipid.c index 0409eb66e39..ac232a96f94 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_chipid.c +++ b/boards/arm/stm32/shenzhou/src/stm32_chipid.c @@ -49,7 +49,7 @@ const char *stm32_getchipid(void) for (i = 0; i < 12; i++) { - cpuid[i] = getreg8(0x1ffff7e8+i); + cpuid[i] = getreg8(0x1ffff7e8 + i); } return cpuid; @@ -63,7 +63,7 @@ const char *stm32_getchipid_string(void) for (i = 0, c = 0; i < 12; i++) { - sprintf(&cpuid[c], "%02X", getreg8(0x1ffff7e8+11-i)); + sprintf(&cpuid[c], "%02X", getreg8(0x1ffff7e8 + 11 - i)); c += 2; if (i % 4 == 3) { diff --git a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c index b12bfcbfff7..eb061fc8f91 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c +++ b/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c @@ -87,7 +87,8 @@ int stm32_sdinitialize(int minor) spi = stm32_spibus_initialize(STM32_MMCSDSPIPORTNO); if (!spi) { - ferr("ERROR: Failed to initialize SPI port %d\n", STM32_MMCSDSPIPORTNO); + ferr("ERROR: Failed to initialize SPI port %d\n", + STM32_MMCSDSPIPORTNO); return -ENODEV; } diff --git a/boards/arm/stm32/shenzhou/src/stm32_spi.c b/boards/arm/stm32/shenzhou/src/stm32_spi.c index fa4086252c3..7673a66cdf7 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_spi.c +++ b/boards/arm/stm32/shenzhou/src/stm32_spi.c @@ -80,31 +80,35 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including stm32_spibus_initialize()) are provided by + * common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); /* SPI1 connects to the SD CARD and to the SPI FLASH */ @@ -124,8 +128,8 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) { - /* The card detect pin is pulled up so that we detect the presence of a card - * by see a low value on the input pin. + /* The card detect pin is pulled up so that we detect the presence of a + * card by see a low value on the input pin. */ if (stm32_gpioread(GPIO_SD_CD)) @@ -138,9 +142,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); /* SPI3 connects to TFT LCD (for touchscreen and SD) and the RF24L01 2.4G * wireless module. diff --git a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c index 68a72e289f5..3e2accf363c 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c +++ b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c @@ -70,10 +70,12 @@ struct stm32_lower_s /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Helpers */ #ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg); +static void stm32_lcdshow(FAR struct stm32_lower_s *priv, + FAR const char *msg); #else # define stm32_lcdshow(p,m) #endif @@ -104,22 +106,26 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ + /* TFT LCD * * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES * -- ---- -------------- --------------------------------------------------- * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) - * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and to the W25X16 SPI FLASH + * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and + * to the W25X16 SPI FLASH * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) - * 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32) + * 58 PD11 SD_CS Active low: Pulled high + * (See also TFT LCD CN13, pin 32) * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) - * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14. + * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). + * Schematic is wrong LCD_WR is PB14. * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) * 97 PE0 DB00 To TFT LCD (CN13, pin 3) * 98 PE1 DB01 To TFT LCD (CN13, pin 4) @@ -138,7 +144,8 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv); * 45 PE14 DB14 To TFT LCD (CN13, pin 17) * 46 PE15 DB15 To TFT LCD (CN13, pin 18) * - * NOTE: The backlight signl NC_BL (CN13, pin 24) is pulled high and not under + * NOTE: + * The backlight signl NC_BL (CN13, pin 24) is pulled high and not under * software control * * On LCD module: @@ -182,24 +189,33 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv); #ifndef CONFIG_LCD_FASTCONFIG static const uint32_t g_lcdout[16] = { - GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, - GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, - GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, - GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, GPIO_LCD_D14OUT, GPIO_LCD_D15OUT + GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, + GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, + GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, + GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, + GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, + GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, + GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, + GPIO_LCD_D14OUT, GPIO_LCD_D15OUT }; static const uint32_t g_lcdin[16] = { - GPIO_LCD_D0IN, GPIO_LCD_D1IN, GPIO_LCD_D2IN, GPIO_LCD_D3IN, - GPIO_LCD_D4IN, GPIO_LCD_D5IN, GPIO_LCD_D6IN, GPIO_LCD_D7IN, - GPIO_LCD_D8IN, GPIO_LCD_D9IN, GPIO_LCD_D10IN, GPIO_LCD_D11IN, - GPIO_LCD_D12IN, GPIO_LCD_D13IN, GPIO_LCD_D14IN, GPIO_LCD_D15IN + GPIO_LCD_D0IN, GPIO_LCD_D1IN, + GPIO_LCD_D2IN, GPIO_LCD_D3IN, + GPIO_LCD_D4IN, GPIO_LCD_D5IN, + GPIO_LCD_D6IN, GPIO_LCD_D7IN, + GPIO_LCD_D8IN, GPIO_LCD_D9IN, + GPIO_LCD_D10IN, GPIO_LCD_D11IN, + GPIO_LCD_D12IN, GPIO_LCD_D13IN, + GPIO_LCD_D14IN, GPIO_LCD_D15IN }; #endif static const uint32_t g_lcdconfig[] = { - GPIO_LCD_RS, GPIO_LCD_CS, GPIO_LCD_RD, GPIO_LCD_WR, + GPIO_LCD_RS, GPIO_LCD_CS, + GPIO_LCD_RD, GPIO_LCD_WR, GPIO_LCD_LE, }; #define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) @@ -235,7 +251,8 @@ static struct stm32_lower_s g_lcdlower = ****************************************************************************/ #ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg) +static void stm32_lcdshow(FAR struct stm32_lower_s *priv, + FAR const char *msg) { _info("%s:\n", msg); _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", @@ -298,7 +315,9 @@ static inline uint16_t stm32_rddata(FAR struct stm32_lower_s *priv) putreg32(1, LCD_RD_CLEAR); - /* Data should appear 250ns after RD. Total RD pulse width should be 500nS */ + /* Data should appear 250ns after RD. + * Total RD pulse width should be 500nS + */ __asm__ __volatile__(" nop\n nop\n nop\n nop\n"); regval = (uint16_t)getreg32(LCD_IDR); @@ -445,6 +464,7 @@ static void stm32_lcdinput(FAR struct stm32_lower_s *priv) stm32_configgpio(g_lcdin[i]); } #endif + /* No longer configured for output */ priv->output = false; @@ -481,6 +501,7 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv) stm32_configgpio(g_lcdout[i]); } #endif + /* Now we are configured for output */ priv->output = true; @@ -495,9 +516,10 @@ static void stm32_lcdoutput(FAR struct stm32_lower_s *priv) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). * ****************************************************************************/ @@ -540,8 +562,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows - * support for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c index d30bb5e4a9e..1927e1523df 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c +++ b/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c @@ -249,17 +249,22 @@ int stm32_tsc_setup(int minor) dev = stm32_spibus_initialize(CONFIG_ADS7843E_SPIDEV); if (!dev) { - ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV); + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); return -ENODEV; } /* Initialize and register the SPI touschscreen device */ - ret = ads7843e_register(dev, &g_tscinfo.dev, CONFIG_ADS7843E_DEVMINOR); + ret = ads7843e_register(dev, &g_tscinfo.dev, + CONFIG_ADS7843E_DEVMINOR); if (ret < 0) { - ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_ADS7843E_SPIDEV); + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); + /* up_spiuninitialize(dev); */ + return -ENODEV; } diff --git a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c index 737eeb3a643..12b3e315a97 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c +++ b/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c @@ -59,7 +59,8 @@ int board_usbmsc_initialize(int port) { /* If system/usbmsc is built as an NSH command, then SD slot should * already have been initialized in board_app_initialize() (see - * stm32_appinit.c). In this case, there is nothing further to be done here. + * stm32_appinit.c). + * In this case, there is nothing further to be done here. */ #ifndef CONFIG_NSH_BUILTIN_APPS diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c index ba8a765c897..bc98b8c2326 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c @@ -75,11 +75,17 @@ /* Identifying number of each ADC channel: Variable Resistor */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {14}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 14 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN14}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN14 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c index 5c6cf188cb9..3c8b577e0fa 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c @@ -63,8 +63,8 @@ void stm32_boardinitialize(void) stm32_selectsram(); #endif - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) @@ -75,8 +75,8 @@ void stm32_boardinitialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) @@ -99,7 +99,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c index 82a8c2c74a5..8234b86bd81 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c @@ -73,7 +73,9 @@ # define CONFIG_NSH_MMCSDSLOTNO 0 # endif #else - /* Add configuration for new STM32 boards here */ + +/* Add configuration for new STM32 boards here */ + # error "Unrecognized STM32 board" # undef NSH_HAVEUSBDEV # undef NSH_HAVEMMCSD @@ -85,8 +87,8 @@ # undef NSH_HAVEUSBDEV #endif -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support - * is not enabled. +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. */ #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) @@ -212,15 +214,18 @@ int stm32_bringup(void) mtd = m25p_initialize(spi); if (!mtd) { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); return -ENODEV; } - syslog(LOG_INFO, "Successfully bound SPI port 0 to the SPI FLASH driver\n"); + syslog(LOG_INFO, + "Successfully bound SPI port 0 to the SPI FLASH driver\n"); #warning "Now what are we going to do with this SPI FLASH driver?" #endif /* Create the SPI FLASH MTD instance */ + /* The M25Pxx is not a give media to implement a file system.. * its block sizes are too large */ @@ -249,18 +254,19 @@ int stm32_bringup(void) ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); if (ret != OK) { - syslog(LOG_ERR, "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); return ret; } syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the STM3210E-EVAL board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO + * to detect if there is a card in the slot. */ - sdio_mediachange(sdio, true); + sdio_mediachange(sdio, true); #endif #ifdef CONFIG_ADC @@ -299,7 +305,8 @@ int stm32_bringup(void) ret = stm32_djoy_initialization(); if (ret != OK) { - syslog(LOG_ERR, "ERROR: Failed to register the joystick driver: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", ret); return ret; } diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c index 8d20064302a..667ead198a5 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c @@ -56,7 +56,8 @@ # undef STM32_MMCSDSLOTNO # define STM32_MMCSDSLOTNO 0 #else - /* Add configuration for new STM32 boards here */ +/* Add configuration for new STM32 boards here */ + # error "Unrecognized STM32 board" #endif @@ -147,9 +148,9 @@ static int board_mscclassobject(int minor, * Name: board_mscuninitialize * * Description: - * Un-initialize the USB storage class driver. This is just an application- - * specific wrapper aboutn usbmsc_unitialize() that is called form the - * composite device logic. + * Un-initialize the USB storage class driver. + * This is just an application- specific wrapper about usbmsc_unitialize() + * that is called form the composite device logic. * * Input Parameters: * classdev - The class driver instrance previously give to the composite @@ -206,6 +207,7 @@ static FAR void *board_composite0_connect(int port) cdcacm_get_composite_devdesc(&dev[0]); /* Overwrite and correct some values... */ + /* The callback functions for the CDC/ACM class */ dev[0].classobject = cdcacm_classobject; @@ -232,6 +234,7 @@ static FAR void *board_composite0_connect(int port) strbase += dev[0].devinfo.nstrings; /* Configure the mass storage device device */ + /* Ask the usbmsc driver to fill in the constants we didn't * know here. */ @@ -239,6 +242,7 @@ static FAR void *board_composite0_connect(int port) usbmsc_get_composite_devdesc(&dev[1]); /* Overwrite and correct some values... */ + /* The callback functions for the USBMSC class */ dev[1].classobject = board_mscclassobject; @@ -305,6 +309,7 @@ static FAR void *board_composite1_connect(int port) cdcacm_get_composite_devdesc(&dev[i]); /* Overwrite and correct some values... */ + /* The callback functions for the CDC/ACM class */ dev[i].classobject = cdcacm_classobject; @@ -352,7 +357,8 @@ int board_composite_initialize(int port) { /* If system/composite is built as an NSH command, then SD slot should * already have been initialized in board_app_initialize() (see - * stm32_appinit.c). In this case, there is nothing further to be done here. + * stm32_appinit.c). + * In this case, there is nothing further to be done here. * * NOTE: CONFIG_NSH_BUILTIN_APPS is not a fool-proof indication that NSH * was built. @@ -389,16 +395,16 @@ int board_composite_initialize(int port) syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the STM3210E-EVAL board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3210E-EVAL board supports a GPIO to detect if + * there is a card in the slot. */ - sdio_mediachange(sdio, true); + sdio_mediachange(sdio, true); #endif /* CONFIG_NSH_BUILTIN_APPS */ - return OK; + return OK; } /**************************************************************************** diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c index b3a0d9ad3a2..b0829634da8 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c @@ -57,8 +57,10 @@ * Private Function Prototypes ****************************************************************************/ -static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t +djoy_supported(FAR const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t +djoy_sample(FAR const struct djoy_lowerhalf_s *lower); static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, djoy_buttonset_t press, djoy_buttonset_t release, djoy_interrupt_t handler, FAR void *arg); @@ -69,6 +71,7 @@ static int djoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data ****************************************************************************/ + /* Pin configuration for each STM3210E-EVAL joystick "button." Index using * DJOY_* definitions in include/nuttx/input/djoystick.h. */ @@ -104,7 +107,8 @@ static const struct djoy_lowerhalf_s g_djoylower = * ****************************************************************************/ -static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower) +static djoy_buttonset_t +djoy_supported(FAR const struct djoy_lowerhalf_s *lower) { iinfo("Supported: %02x\n", DJOY_SUPPORTED); return (djoy_buttonset_t)DJOY_SUPPORTED; @@ -127,11 +131,11 @@ static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower) for (i = 0; i < DJOY_NGPIOS; i++) { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } } iinfo("Retuning: %02x\n", DJOY_SUPPORTED); @@ -181,26 +185,26 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, for (i = 0; i < DJOY_NGPIOS; i++) { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); - iinfo("GPIO %d: rising: %d falling: %d\n", + iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32_gpiosetevent(g_joygpio[i], rising, falling, + stm32_gpiosetevent(g_joygpio[i], rising, falling, true, djoy_interrupt, NULL); - } + } } } diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c index 64ab804913a..8c22472a8cd 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c @@ -130,28 +130,28 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; #ifdef CONFIG_PM @@ -260,35 +260,30 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Restore normal LEDs operation */ - } break; case(PM_IDLE): { /* Entering IDLE mode - Turn leds off */ - } break; case(PM_STANDBY): { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } break; default: { /* Should not get here */ - } break; } @@ -330,12 +325,12 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_ARCH_LEDS void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -367,7 +362,7 @@ void stm32_ledpminitialize(void) int ret = pm_register(&g_ledscb); if (ret != OK) - { + { board_autoled_on(LED_ASSERTION); } } diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c index edac36e0fb1..140dd949039 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c @@ -51,9 +51,9 @@ * Private Data ****************************************************************************/ -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit - * accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM, - * respectively. +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. * * Pin Usage (per schematic) * FLASH SRAM NAND LCD @@ -111,18 +111,22 @@ void stm32_selectlcd(void) /* Bank4 NOR/SRAM control register configuration */ - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR4); /* Bank4 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| - FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); putreg32(0xffffffff, STM32_FSMC_BWTR4); /* Enable the bank by setting the MBKEN bit */ - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c index f641b695599..6e34834c7f4 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c @@ -108,17 +108,23 @@ void stm32_selectnor(void) /* Bank1 NOR/SRAM control register configuration */ - putreg32(FSMC_BCR_NOR|FSMC_BCR_FACCEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR2); + putreg32(FSMC_BCR_NOR | FSMC_BCR_FACCEN | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, + STM32_FSMC_BCR2); /* Bank1 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTURN(1)| - FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODB, STM32_FSMC_BTR2); + putreg32(FSMC_BTR_ADDSET(3) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(6) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODB, STM32_FSMC_BTR2); putreg32(0x0fffffff, STM32_FSMC_BWTR2); /* Enable the bank */ - putreg32(FSMC_BCR_MBKEN|FSMC_BCR_NOR|FSMC_BCR_FACCEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR2); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_NOR | + FSMC_BCR_FACCEN | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR2); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c index d855b0cede9..b86cac8f917 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c @@ -51,9 +51,9 @@ * Private Data ****************************************************************************/ -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit - * accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM, - * respectively. +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. * * Pin Usage (per schematic) * FLASH SRAM NAND LCD @@ -111,18 +111,21 @@ void stm32_selectsram(void) /* Bank1 NOR/SRAM control register configuration */ - putreg32(FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3); + putreg32(FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); /* Bank1 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTURN(1)| - FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(3) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3); /* Enable the bank */ - putreg32(FSMC_BCR_MBKEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR3); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c index 40ada79e337..b3642294621 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c @@ -46,7 +46,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL board. + * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL + * board. * ****************************************************************************/ @@ -69,31 +70,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); if (devid == SPIDEV_FLASH(0)) { @@ -110,9 +114,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -122,9 +128,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c index 6f8e37375cc..563575fe0a2 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c @@ -67,11 +67,12 @@ void stm32_usbinitialize(void) * Name: stm32_usbpullup * * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be - * NULL. + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can be + * redefined to be NULL. * ****************************************************************************/ @@ -86,10 +87,10 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c index 505c8cf49eb..b49064ecb15 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c @@ -54,7 +54,8 @@ # undef STM32_MMCSDSLOTNO # define STM32_MMCSDSLOTNO 0 #else - /* Add configuration for new STM32 boards here */ +/* Add configuration for new STM32 boards here */ + # error "Unrecognized STM32 board" #endif @@ -90,7 +91,8 @@ int stm32_bringup(void); int board_usbmsc_initialize(int port) { /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized in board_app_initialize() (see stm32_appinit.c). + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). * In this case, there is nothing further to be done here. */ @@ -126,16 +128,16 @@ int board_usbmsc_initialize(int port) syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the STM3210E-EVAL board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO to + * detect if there is a card in the slot. */ - sdio_mediachange(sdio, true); + sdio_mediachange(sdio, true); #endif /* CONFIG_NSH_BUILTIN_APPS */ - return OK; + return OK; } #endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/stm3220g-eval/include/board.h b/boards/arm/stm32/stm3220g-eval/include/board.h index b61767d0ded..0e1422a4042 100644 --- a/boards/arm/stm32/stm3220g-eval/include/board.h +++ b/boards/arm/stm32/stm3220g-eval/include/board.h @@ -39,20 +39,23 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ + /* Four clock sources are available on STM3220G-EVAL evaluation board for * STM32F207IGH6 and RTC embedded: * - * X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is - * provided by MCO pin of the MCU + * X1, 25 MHz crystal for ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU * X2, 26 MHz crystal for USB OTG HS PHY * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller (It can be removed - * from socket when internal RC clock is used.) + * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) * - * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL configuration + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) @@ -62,7 +65,8 @@ * PLLN : 240 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK * Flash Latency(WS) : 5 * Prefetch Buffer : OFF * Instruction cache : ON @@ -116,7 +120,7 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) -/* Timers driven from APB1 will be twice PCLK1 (60Mhz)*/ +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -133,7 +137,7 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* Timers driven from APB2 will be twice PCLK2 (120Mhz)*/ +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) @@ -185,7 +189,8 @@ # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* Ethernet *************************************************************************/ +/* Ethernet *****************************************************************/ + /* We need to provide clocking to the MII PHY via MCO1 (PA8) */ #if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) @@ -204,9 +209,10 @@ # endif #endif -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -224,8 +230,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * STM3220G-EVAL. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3220G-EVAL. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -237,7 +244,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The STM3220G-EVAL supports three buttons: */ #define BUTTON_WAKEUP 0 @@ -250,7 +258,7 @@ #define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* UART3: * @@ -307,7 +315,8 @@ * If FSMC is not used: * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. * * TIM1 CH1OUT: PE9 FSMC_D6 * Daughterboard Extension Connector, CN2, pin 24 @@ -381,7 +390,8 @@ /* CAN * - * Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2. + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. * * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver @@ -405,7 +415,8 @@ #define GPIO_CAN2_RX GPIO_CAN2_RX_2 #define GPIO_CAN2_TX GPIO_CAN2_TX_1 -/* I2C. Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are +/* I2C. + * Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are * available on the following pins: * * - PB6 is I2C1_SCL @@ -415,9 +426,10 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 -/* DMA Channel/Stream Selections *****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * is we set aside more DMA channels/streams. +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3 @@ -449,10 +461,11 @@ extern "C" * Name: stm3220g_lcdclear * * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c index 15435fed6f3..9c3b9a98fa0 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c @@ -44,6 +44,7 @@ ****************************************************************************/ /* Configuration ************************************************************/ + /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 @@ -70,6 +71,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* The STM3220G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of * STM32F207IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 */ @@ -77,11 +79,17 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = {7}; +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC3_NCHANNELS] = {GPIO_ADC3_IN7}; +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c b/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c index 3131b95d30d..e00b4b2c5c6 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_appinit.c @@ -75,8 +75,8 @@ # define CONFIG_NSH_MMCSDSLOTNO 0 #endif -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO support - * is not enabled. +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. */ #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) @@ -227,7 +227,8 @@ int board_app_initialize(uintptr_t arg) mtd = m25p_initialize(spi); if (!mtd) { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); return -ENODEV; } @@ -252,20 +253,21 @@ int board_app_initialize(uintptr_t arg) ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); if (ret != OK) { - syslog(LOG_ERR, "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); return ret; } - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the STM3220G-EVAL board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3220G-EVAL board supports a GPIO to detect if + * there is a card in the slot. */ - sdio_mediachange(sdio, true); + sdio_mediachange(sdio, true); #endif - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. */ #ifdef HAVE_USBHOST diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c index b571b54518a..1cde39c7394 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c @@ -112,28 +112,28 @@ static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; /**************************************************************************** @@ -202,12 +202,12 @@ static void led_setonoff(unsigned int bits) void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c index 3bddd54f92f..82b0f2bbfab 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c @@ -57,8 +57,8 @@ void stm32_boardinitialize(void) { - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) @@ -74,8 +74,9 @@ void stm32_boardinitialize(void) stm32_selectsram(); #endif - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * the weak function stm32_usbinitialize() has been brought into the build. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) the weak function stm32_usbinitialize() has been brought into the + * build. * Presumeably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c index 9e7b91b6656..6bb427b23b7 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c @@ -60,18 +60,25 @@ static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = { - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, GPIO_FSMC_A24, GPIO_FSMC_A25 }; static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = { - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 }; /**************************************************************************** diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c index 07b106b65a1..2b621a4f201 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c @@ -65,7 +65,7 @@ * Private Data ****************************************************************************/ -/* GPIOs Configuration ******************************************************* +/* GPIOs Configuration ****************************************************** * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 @@ -155,7 +155,8 @@ void stm32_selectsram(void) * Write burst : Disabled */ - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); /* Bank1 NOR/SRAM timing register configuration */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c index a05aa893c85..c9bc107df4a 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c @@ -46,7 +46,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL board. + * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL + * board. * ****************************************************************************/ @@ -59,31 +60,35 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -93,9 +98,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -105,9 +112,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c index acbf9cd0c07..ff53b5f66ac 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c @@ -79,8 +79,9 @@ #endif /* Board definitions ********************************************************/ -/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both connected - * to the STM32 via I2C1. They share a common interrupt line: PI2. + +/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. * * STMPE811 U24, I2C address 0x41 (7-bit) * ------ ---- ---------------- -------------------------------------------- @@ -142,7 +143,8 @@ struct stm32_stmpe811config_s static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg); -static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); +static void stmpe811_enable(FAR struct stmpe811_config_s *state, + bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); /**************************************************************************** @@ -200,7 +202,8 @@ static struct stm32_stmpe811config_s g_stmpe811config = static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg) { - FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; + FAR struct stm32_stmpe811config_s *priv = + (FAR struct stm32_stmpe811config_s *)state; iinfo("Saving handler %p\n", isr); DEBUGASSERT(priv); @@ -214,7 +217,8 @@ static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable) { - FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; + FAR struct stm32_stmpe811config_s *priv = + (FAR struct stm32_stmpe811config_s *)state; irqstate_t flags; /* Attach and enable, or detach and disable. Enabling and disabling GPIO @@ -291,14 +295,16 @@ int stm32_tsc_setup(int minor) dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); if (!dev) { - ierr("ERROR: Failed to initialize I2C bus %d\n", CONFIG_STMPE811_I2CDEV); + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); return -ENODEV; } /* Instantiate the STMPE811 driver */ g_stmpe811config.handle = - stmpe811_instantiate(dev, (FAR struct stmpe811_config_s *)&g_stmpe811config); + stmpe811_instantiate(dev, + (FAR struct stmpe811_config_s *)&g_stmpe811config); if (!g_stmpe811config.handle) { ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); @@ -307,11 +313,14 @@ int stm32_tsc_setup(int minor) /* Initialize and register the I2C touchscreen device */ - ret = stmpe811_register(g_stmpe811config.handle, CONFIG_STMPE811_DEVMINOR); + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); if (ret < 0) { ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + /* stm32_i2cbus_uninitialize(dev); */ + return -ENODEV; } } diff --git a/boards/arm/stm32/stm3240g-eval/include/board.h b/boards/arm/stm32/stm3240g-eval/include/board.h index 25a83c65545..68d48a898c6 100644 --- a/boards/arm/stm32/stm3240g-eval/include/board.h +++ b/boards/arm/stm32/stm3240g-eval/include/board.h @@ -32,29 +32,32 @@ #endif /* Logic in arch/arm/src and boards/ may need to include these file prior to - * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be included - * here because board.h is used in other contexts where the STM32 internal header - * files are not available. + * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be + * included here because board.h is used in other contexts where the STM32 + * internal header files are not available. */ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ + /* Four clock sources are available on STM3240G-EVAL evaluation board for * STM32F407IGH6 and RTC embedded: * - * X1, 25 MHz crystal for Ethernet PHY with socket. It can be removed when clock is - * provided by MCO pin of the MCU + * X1, 25 MHz crystal for Ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU * X2, 26 MHz crystal for USB OTG HS PHY * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed - * from socket when internal RC clock is used.) + * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) * - * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c: + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) @@ -64,7 +67,8 @@ * PLLN : 336 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK * Flash Latency(WS) : 5 * Prefetch Buffer : OFF * Instruction cache : ON @@ -193,7 +197,8 @@ # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* Ethernet *************************************************************************/ +/* Ethernet *****************************************************************/ + /* We need to provide clocking to the MII PHY via MCO1 (PA8) */ #if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) @@ -212,9 +217,10 @@ # endif #endif -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -232,8 +238,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * STM3240G-EVAL. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -245,7 +252,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The STM3240G-EVAL supports three buttons: */ #define BUTTON_WAKEUP 0 @@ -258,15 +266,16 @@ #define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* SRAM definitions *****************************************************************/ -/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares the same - * I/Os with the CAN1 bus. Jumper settings: +/* SRAM definitions *********************************************************/ + +/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares + * the same I/Os with the CAN1 bus. Jumper settings: * * JP1: Connect PE4 to SRAM as A20 * JP2: onnect PE3 to SRAM as A19 * - * JP3 and JP10 must not be fitted for SRAM and LCD application. JP3 and JP10 - * select CAN1 or CAN2 if fitted; neither if not fitted. + * JP3 and JP10 must not be fitted for SRAM and LCD application. + * JP3 and JP10 select CAN1 or CAN2 if fitted; neither if not fitted. */ #if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) @@ -280,7 +289,7 @@ #define BOARD_SRAM_BASE 0x64000000 #define BOARD_SRAM_SIZE (2*1024*1024) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* UART3: * @@ -335,7 +344,8 @@ * If FSMC is not used: * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14. + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. * * TIM1 CH1OUT: PE9 FSMC_D6 * Daughterboard Extension Connector, CN2, pin 24 @@ -409,7 +419,8 @@ /* CAN * - * Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2. + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. * * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver @@ -433,7 +444,8 @@ #define GPIO_CAN2_RX GPIO_CAN2_RX_2 #define GPIO_CAN2_TX GPIO_CAN2_TX_1 -/* I2C. Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are +/* I2C. + * Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are * available on the following pins: * * - PB6 is I2C1_SCL @@ -443,9 +455,10 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 -/* DMA Channel/Stream Selections *****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3 @@ -477,10 +490,11 @@ extern "C" * Name: stm3240g_lcdclear * * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c index 8719a42e6a2..d06892de12f 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c @@ -71,6 +71,7 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* The STM3240G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of * STM32F407IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 */ @@ -78,11 +79,17 @@ /* Identifying number of each ADC channel: Variable Resistor. */ #ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = {7}; +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC3_NCHANNELS] = {GPIO_ADC3_IN7}; +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c index 404d5dfc142..e11bd264039 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c @@ -112,28 +112,28 @@ static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; /**************************************************************************** @@ -202,12 +202,12 @@ static void led_setonoff(unsigned int bits) void stm32_led_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c index 0009e9e475d..7f0766c6974 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c @@ -96,7 +96,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c index 1c829d15cf5..a1c2076e882 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c @@ -60,18 +60,25 @@ static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = { - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, GPIO_FSMC_A24, GPIO_FSMC_A25 }; static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = { - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 }; /**************************************************************************** diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c index 588299ab003..362177c6121 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c @@ -64,20 +64,21 @@ /**************************************************************************** * Private Data ****************************************************************************/ -/* GPIOs Configuration ************************************************************** - * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 - * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 - * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 - * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 - * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 - * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 - * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 - * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 - * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 - * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 - * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 - * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 - * PE15 <-> FSMC_D12 + +/* GPIOs Configuration ****************************************************** + * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 + * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 + * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 + * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 + * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 + * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 + * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 + * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 + * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 + * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 + * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 + * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 + * PE15 <-> FSMC_D12 */ /* GPIO configurations unique to SRAM */ @@ -102,25 +103,25 @@ static const uint32_t g_sramconfig[] = * Name: stm32_selectsram * * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC Bank - * NOR/SRAM2 base address (0x64000000) + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) * - * General transaction rules. The requested AHB transaction data size can be 8-, - * 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data width. Some simple - * transaction rules must be followed: + * General transaction rules. The requested AHB transaction data size can + * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data + * width. Some simple transaction rules must be followed: * * Case 1: AHB transaction width and SRAM data width are equal * There is no issue in this case. * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller consecutive - * memory accesses in order to meet the external data width. + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. * Case 3: AHB transaction size is smaller than the memory size. * SRAM supports the byte select feature. * a) FSMC allows write transactions accessing the right data through its * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire memory - * word and uses the needed byte only). The NBL[1:0] are always kept low - * during read transactions. + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. * ****************************************************************************/ @@ -154,23 +155,30 @@ void stm32_selectsram(void) * Write burst : Disabled */ - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); /* Bank1 NOR/SRAM timing register configuration */ - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | FSMC_BTR_ACCMODA), - STM32_FSMC_BTR2); + STM32_FSMC_BTR2); - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ /* Enable the bank */ - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c index f73b8e77b82..f89bad12cb5 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c @@ -46,7 +46,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL board. + * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL + * board. * ****************************************************************************/ @@ -59,31 +60,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -93,9 +97,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -105,9 +111,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c index 44910114df3..534e3ccfa09 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c @@ -79,8 +79,10 @@ #endif /* Board definitions ********************************************************/ -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both connected - * to the STM32 via I2C1. They share a common interrupt line: PI2. + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. + * They share a common interrupt line: PI2. * * STMPE811 U24, I2C address 0x41 (7-bit) * ------ ---- ---------------- -------------------------------------------- @@ -132,7 +134,8 @@ struct stm32_stmpe811config_s /* IRQ/GPIO access callbacks. These operations all hidden behind callbacks * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and loss-of-contact events can be detected. + * interrupt handling by varying boards and MCUs.* so that contact and + * loss-of-contact events can be detected. * * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt * enable - Enable or disable the GPIO interrupt @@ -141,7 +144,8 @@ struct stm32_stmpe811config_s static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg); -static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); +static void stmpe811_enable(FAR struct stmpe811_config_s *state, + bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); /**************************************************************************** @@ -199,12 +203,15 @@ static struct stm32_stmpe811config_s g_stmpe811config = static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg) { - FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; + FAR struct stm32_stmpe811config_s *priv = + (FAR struct stm32_stmpe811config_s *)state; iinfo("Saving handler %p\n", isr); DEBUGASSERT(priv); - /* Just save the handler. We will use it when EXTI interruptsare enabled */ + /* Just save the handler. + * We will use it when EXTI interruptsare enabled + */ priv->handler = isr; priv->arg = arg; @@ -213,7 +220,8 @@ static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable) { - FAR struct stm32_stmpe811config_s *priv = (FAR struct stm32_stmpe811config_s *)state; + FAR struct stm32_stmpe811config_s *priv = + (FAR struct stm32_stmpe811config_s *)state; irqstate_t flags; /* Attach and enable, or detach and disable. Enabling and disabling GPIO @@ -290,14 +298,16 @@ int stm32_tsc_setup(int minor) dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); if (!dev) { - ierr("ERROR: Failed to initialize I2C bus %d\n", CONFIG_STMPE811_I2CDEV); + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); return -ENODEV; } /* Instantiate the STMPE811 driver */ g_stmpe811config.handle = - stmpe811_instantiate(dev, (FAR struct stmpe811_config_s *)&g_stmpe811config); + stmpe811_instantiate(dev, + (FAR struct stmpe811_config_s *)&g_stmpe811config); if (!g_stmpe811config.handle) { ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); @@ -306,11 +316,14 @@ int stm32_tsc_setup(int minor) /* Initialize and register the I2C touchscreen device */ - ret = stmpe811_register(g_stmpe811config.handle, CONFIG_STMPE811_DEVMINOR); + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); if (ret < 0) { ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + /* stm32_i2cbus_uninitialize(dev); */ + return -ENODEV; } } diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c index dc803d0d922..c75d3a00dad 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c @@ -71,11 +71,17 @@ */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {0}; /* ADC12_IN0 */ +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; /* ADC12_IN0 */ /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_IN0}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN0 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c index 86313157235..b448ce5d1c5 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c @@ -135,18 +135,21 @@ static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; static int stm32gpio_interrupt(int irq, void *context, void *arg) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)arg; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)arg; DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, stm32gpint->stm32gpio.id); + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); return OK; } static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL && value != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); @@ -158,7 +161,8 @@ static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL && value != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); @@ -170,7 +174,8 @@ static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpout_write(FAR struct gpio_dev_s *dev, bool value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); @@ -182,7 +187,8 @@ static int gpout_write(FAR struct gpio_dev_s *dev, bool value) static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; DEBUGASSERT(stm32gpint != NULL && value != NULL); DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); @@ -195,7 +201,8 @@ static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpint_attach(FAR struct gpio_dev_s *dev, pin_interrupt_t callback) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; gpioinfo("Attaching the callback\n"); @@ -211,7 +218,8 @@ static int gpint_attach(FAR struct gpio_dev_s *dev, static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; if (enable) { @@ -224,7 +232,6 @@ static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); - } } else @@ -283,6 +290,7 @@ int stm32_gpio_initialize(void) gpio_pin_register(&g_gpout[i].gpio, pincount); /* Configure the pin that will be used as output */ + stm32_gpiowrite(g_gpiooutputs[i], 0); stm32_configgpio(g_gpiooutputs[i]); diff --git a/boards/arm/stm32/stm32f3discovery/include/board.h b/boards/arm/stm32/stm32f3discovery/include/board.h index 9361561696d..f41b4b70ce2 100644 --- a/boards/arm/stm32/stm32f3discovery/include/board.h +++ b/boards/arm/stm32/stm32f3discovery/include/board.h @@ -38,7 +38,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* HSI - Internal 8 MHz RC Oscillator * LSI - 32 KHz RC @@ -53,7 +53,10 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, + * PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -105,7 +108,6 @@ #define STM32_CFGR_USBPRE 0 - /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 @@ -120,27 +122,30 @@ #define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* LED definitions ******************************************************************/ -/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by logic on - * the board and are not available for software control: +/* LED definitions **********************************************************/ + +/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by + * logic on the board and are not available for software control: * * LD1 PWR: red LED indicates that the board is powered. * LD2 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the ST-LINK/V2. + * communications are in progress between the PC and the + * ST-LINK/V2. * * And eight can be controlled by software: * - * User LD3: red LED is a user LED connected to the I/O PE9 of the STM32F303VCT6. - * User LD4: blue LED is a user LED connected to the I/O PE8 of the STM32F303VCT6. - * User LD5: orange LED is a user LED connected to the I/O PE10 of the STM32F303VCT6. - * User LD6: green LED is a user LED connected to the I/O PE15 of the STM32F303VCT6. - * User LD7: green LED is a user LED connected to the I/O PE11 of the STM32F303VCT6. - * User LD8: orange LED is a user LED connected to the I/O PE14 of the STM32F303VCT6. - * User LD9: blue LED is a user LED connected to the I/O PE12 of the STM32F303VCT6. - * User LD10: red LED is a user LED connected to the I/O PE13 of the STM32F303VCT6. + * User LEDs connected to the I/O of the STM32F303VCT6. + * User LD3: red LED is a user LED connected to the PE9 I/O. + * User LD4: blue LED is a user LED connected to the PE8 I/O. + * User LD5: orange LED is a user LED connected to the PE10 I/O. + * User LD6: green LED is a user LED connected to the PE15 I/O. + * User LD7: green LED is a user LED connected to the PE11 I/O. + * User LD8: orange LED is a user LED connected to the PE14 I/O. + * User LD9: blue LED is a user LED connected to the PE12 I/O. + * User LD10: red LED is a user LED connected to the PE13 I/O. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -166,8 +171,9 @@ #define BOARD_LED7_BIT (1 << BOARD_LED7) #define BOARD_LED8_BIT (1 << BOARD_LED8) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the - * stm32f3discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the stm32f3discovery. + * The following definitions describe how NuttX controls the LEDs: * * SYMBOL Meaning LED state * Initially all LEDs are OFF @@ -178,7 +184,8 @@ * LED_STACKCREATED Idle stack created LD6 ON * LED_INIRQ In an interrupt LD7 should glow * LED_SIGNAL In a signal handler LD8 might glow - * LED_ASSERTION An assertion failed LD9 ON while handling the assertion + * LED_ASSERTION An assertion failed LD9 ON while handling + * the assertion * LED_PANIC The system has crashed LD10 Blinking at 2Hz * LED_IDLE STM32 is is sleep mode (Optional, not used) */ @@ -192,12 +199,16 @@ #define LED_ASSERTION 6 #define LED_PANIC 7 -/* Button definitions ***************************************************************/ -/* The STM32F3Discovery supports two buttons; only one button is controllable by - * software: +/* Button definitions *******************************************************/ + +/* The STM32F3Discovery supports two buttons; only one button is controllable + * by software: * - * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F303VCT6. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32F303VCT6. + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the + * STM32F303VCT6. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F303VCT6. */ #define BUTTON_USER 0 @@ -206,7 +217,7 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* USART * @@ -214,7 +225,8 @@ * RX (PC5) * TX (PC4) * - * USART2: Connect to an external UART<->RS232 transceiver for use as console. + * USART2: + * Connect to an external UART<->RS232 transceiver for use as console. * RX (PA3) * TX (PA2) */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c index f812592c7f6..7a05058196c 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c @@ -80,14 +80,13 @@ void stm32_boardinitialize(void) #endif } - /**************************************************************************** * Name: board_late_initialize * * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c index 061195770ec..1463096443a 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c +++ b/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c @@ -47,7 +47,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f3discovery board. + * Called to configure SPI chip select GPIO pins for the stm32f3discovery + * board. * ****************************************************************************/ @@ -64,31 +65,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); stm32_gpiowrite(GPIO_MEMS_CS, !selected); } @@ -100,9 +104,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -112,9 +118,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c index 157ccbc3c8d..6a63ef599c2 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c @@ -110,28 +110,28 @@ static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; /**************************************************************************** @@ -149,7 +149,6 @@ static inline void led_clrbits(unsigned int clrbits) { stm32_gpiowrite(GPIO_LED2, false); } - } static inline void led_setbits(unsigned int setbits) @@ -163,7 +162,6 @@ static inline void led_setbits(unsigned int setbits) { stm32_gpiowrite(GPIO_LED2, true); } - } static void led_setonoff(unsigned int bits) @@ -182,10 +180,10 @@ static void led_setonoff(unsigned int bits) void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c index 6b67219340a..cdc620f15fb 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c @@ -65,10 +65,10 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the 1) OTG HS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the 1) OTG HS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. */ if (stm32_usbinitialize) diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c index ca56e353832..5d2bcf6ecf5 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c @@ -79,8 +79,9 @@ #endif /* Board definitions ********************************************************/ -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both connected - * to the STM32 via I2C1. They share a common interrupt line: PI2. + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. * * STMPE811 U24, I2C address 0x41 (7-bit) * ------ ---- ---------------- -------------------------------------------- @@ -142,7 +143,8 @@ struct stm32_stmpe811config_s static int stmpe811_attach(FAR struct stmpe811_config_s *state, xcpt_t isr, FAR void *arg); -static void stmpe811_enable(FAR struct stmpe811_config_s *state, bool enable); +static void stmpe811_enable(FAR struct stmpe811_config_s *state, + bool enable); static void stmpe811_clear(FAR struct stmpe811_config_s *state); /**************************************************************************** @@ -293,14 +295,16 @@ int stm32_tsc_setup(int minor) dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); if (!dev) { - ierr("ERROR: Failed to initialize I2C bus %d\n", CONFIG_STMPE811_I2CDEV); + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); return -ENODEV; } /* Instantiate the STMPE811 driver */ g_stmpe811config.handle = - stmpe811_instantiate(dev, (FAR struct stmpe811_config_s *)&g_stmpe811config); + stmpe811_instantiate(dev, + (FAR struct stmpe811_config_s *)&g_stmpe811config); if (!g_stmpe811config.handle) { ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); @@ -309,11 +313,14 @@ int stm32_tsc_setup(int minor) /* Initialize and register the I2C touchscreen device */ - ret = stmpe811_register(g_stmpe811config.handle, CONFIG_STMPE811_DEVMINOR); + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); if (ret < 0) { ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + /* stm32_i2cbus_uninitialize(dev); */ + return -ENODEV; } } diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c index 904aee49d67..95b18d47549 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c @@ -112,28 +112,28 @@ static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; /**************************************************************************** @@ -202,12 +202,12 @@ static void led_setonoff(unsigned int bits) void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c index 846d34d2ad1..42a29580487 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c @@ -78,10 +78,10 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. */ if (stm32_usbinitialize) @@ -112,7 +112,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c index f8296603293..d4e00dd6fb0 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c @@ -59,6 +59,7 @@ #define AT24XX_MACADDR_OFFSET 0x9a /* Debug ********************************************************************/ + /* Extra, in-depth debug output that is only available if * CONFIG_NETDEV_PHY_DEBUG us defined. */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c index b9607dd8cc0..73ff11c134b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c @@ -59,18 +59,25 @@ static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = { - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, GPIO_FSMC_A24, GPIO_FSMC_A25 }; static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = { - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15 + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 }; /**************************************************************************** diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c index 2e55fb1f128..f6f16416a68 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c @@ -62,11 +62,12 @@ int stm32_pca9635_initialize(void) { - FAR struct i2c_master_s *i2c; int ret; - /* Get the I2C driver that interfaces with the pca9635 (PCA9635_I2CBUS)*/ + /* Get the I2C driver that interfaces with the pca9635 + * (PCA9635_I2CBUS) + */ i2c = stm32_i2cbus_initialize(PCA9635_I2CBUS); if (!i2c) @@ -79,7 +80,7 @@ int stm32_pca9635_initialize(void) if (ret < 0) { snerr("ERROR: Failed to register PCA9635 driver: %d\n", ret); - return ret; + return ret; } return OK; diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c index 54520bd5109..495b70dcb5b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c @@ -30,7 +30,7 @@ #ifdef CONFIG_BOARDCTL_RESET /**************************************************************************** - * Public functions + * Public Functions ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c index 2a7c6377b5e..09dc57006e0 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c @@ -119,6 +119,7 @@ int stm32_sdio_initialize(void) #endif /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c index e04150c9519..750d2a97493 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c @@ -95,6 +95,7 @@ static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power); /**************************************************************************** * Private Data ****************************************************************************/ + /* LCD pin mapping (see boards/arm/stm32/stm324discovery/README.txt * MAPPING TO STM32 F4: * @@ -126,9 +127,10 @@ static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power); * * 1 Used for the RED LED * 2 Used for the BLUE LED - * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to use - * for the parallel interface if PC0 is held high (or floating). PC0 enables - * the STMPS2141STR IC power switch that drives the OTG FS host VBUS. + * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to + * use for the parallel interface if PC0 is held high (or floating). + * PC0 enables the STMPS2141STR IC power switch that drives the OTG FS + * host VBUS. * 4 Also the reset pin for the CS43L22 audio Codec. */ @@ -145,7 +147,9 @@ static const uint32_t g_lcdconfig[] = }; #define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) -/* This is the driver state structure (there is no retained state information) */ +/* This is the driver state structure + * (there is no retained state information) + */ static struct ssd1289_lcd_s g_ssd1289 = { @@ -282,14 +286,17 @@ void stm32_selectlcd(void) /* Bank1 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | - FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); putreg32(0xffffffff, STM32_FSMC_BWTR1); /* Enable the bank by setting the MBKEN bit */ - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); } /**************************************************************************** @@ -300,9 +307,9 @@ void stm32_selectlcd(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. The initial state of the LCD is fully + * initialized, display memory cleared, and the LCD ready to use, but with + * the power setting at 0 (full off). * ****************************************************************************/ @@ -351,8 +358,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c index 7d06e46a552..a209fc1c79f 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c @@ -35,6 +35,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c index edec340f422..19ad107f0e3 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c @@ -126,35 +126,73 @@ /* These definitions support the logic of slcd_writemem() * - * ---------- ----- ----- ----- ----- ------- ------ ------ ------ ------ ------- ------- ----------------------------- - * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS - * 3210 3210 3210 3210 32 10 32 10 - * ---------- ----- ----- ----- ----- ------- ------ ------ ------ ------ -- --- -- --- ----------------------------- - * LCD SEG0 1N 1P 1D 1E Bit 0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG1 1DP 1COL 1C 1M Bit 1 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG2 2N 2P 2D 2E Bit 2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG3 2DP 2COL 2C 2M Bit 7 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG4 3N 3P 3D 3E Bit 8 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG5 3DP 3COL 3C 3M Bit 9 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG6 4N 4P 4D 4E Bit 10 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG7 4DP 4COL 4C 4M Bit 11 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG8 5N 5P 5D 5E Bit 12 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/0xfff3efff - * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/0xfff3efff - * LCD SEG10 6N 6P 6D 6E Bit 14 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/0xfffcbfff - * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/0xfffcbfff - * LCD SEG12 6J 6K 6A 6B Bit 16 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/0xfffcbfff - * LCD SEG13 6H 6Q 6F 6G Bit 17 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/0xfffcbfff - * LCD SEG14 5J 5K 5A 5B Bit 18 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/0xfff3efff - * LCD SEG15 5H 5Q 5F 5G Bit 19 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/0xfff3efff - * LCD SEG16 4J 4K 4A 4B Bit 20 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG17 4H 4Q 4F 4G Bit 21 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG18 3J 3K 3A 3B Bit 24 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG19 3H 3Q 3F 3G Bit 25 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG20 2J 2K 2A 2B Bit 26 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG21 2H 2Q 2F 2G Bit 27 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG22 1J 1K 1A 1B Bit 28 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG23 1H 1Q 1F 1G Bit 29 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * ---------- ----- ----- ----- ----- ------- ------ ------ ------ ------ ------- ------- ----------------------------- + * ---------- ----- ----- ----- ----- ------- + * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT + * + * ---------- ----- ----- ----- ----- ------- + * LCD SEG0 1N 1P 1D 1E Bit 0 + * LCD SEG1 1DP 1COL 1C 1M Bit 1 + * LCD SEG2 2N 2P 2D 2E Bit 2 + * LCD SEG3 2DP 2COL 2C 2M Bit 7 + * LCD SEG4 3N 3P 3D 3E Bit 8 + * LCD SEG5 3DP 3COL 3C 3M Bit 9 + * LCD SEG6 4N 4P 4D 4E Bit 10 + * LCD SEG7 4DP 4COL 4C 4M Bit 11 + * LCD SEG8 5N 5P 5D 5E Bit 12 + * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 + * LCD SEG10 6N 6P 6D 6E Bit 14 + * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 + * LCD SEG12 6J 6K 6A 6B Bit 16 + * LCD SEG13 6H 6Q 6F 6G Bit 17 + * LCD SEG14 5J 5K 5A 5B Bit 18 + * LCD SEG15 5H 5Q 5F 5G Bit 19 + * LCD SEG16 4J 4K 4A 4B Bit 20 + * LCD SEG17 4H 4Q 4F 4G Bit 21 + * LCD SEG18 3J 3K 3A 3B Bit 24 + * LCD SEG19 3H 3Q 3F 3G Bit 25 + * LCD SEG20 2J 2K 2A 2B Bit 26 + * LCD SEG21 2H 2Q 2F 2G Bit 27 + * LCD SEG22 1J 1K 1A 1B Bit 28 + * LCD SEG23 1H 1Q 1F 1G Bit 29 + * ---------- ----- ----- ----- ----- -------- + + * ---------------- ------ ------ ------ ------- ------- -------------------- + * LCD CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS + * SIGNAL 3210 3210 3210 3210 32 10 32 10 + * --------- ------ ------ ------ ------ -- --- -- --- -------------------- + * LCD SEG0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG1 0 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG3 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG4 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG5 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG6 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG7 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG8 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG9 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG10 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG11 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG12 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG13 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG14 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG15 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG16 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG17 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG18 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG19 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG20 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG21 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG22 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG23 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * --------- ------ ------ ------ ------- ------- --------------------------- */ /* SLCD_CHAR1_MASK COM0-3 0xcffffffc ..11 .... .... .... .... .... .... ..11 diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c index 6c1445f26bb..1bf7e1c6f23 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c +++ b/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c @@ -47,7 +47,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32ldiscovery board. + * Called to configure SPI chip select GPIO pins for the stm32ldiscovery + * board. * ****************************************************************************/ @@ -64,31 +65,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); stm32_gpiowrite(GPIO_MEMS_CS, !selected); } @@ -100,9 +104,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -112,9 +118,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h index eaca5586f82..03264859e54 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -37,13 +37,16 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* On-board crystal frequency is 8MHz (HSE) */ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, + * PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -96,7 +99,8 @@ /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 */ + * Note: TIM1,8 are on APB2, others on APB1 + */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY @@ -116,7 +120,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h index 91c9e660384..a3fee35407d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -37,7 +37,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* HSI - 8 MHz RC factory-trimmed * LSI - 40 KHz RC (30-60KHz, uncalibrated) @@ -98,7 +98,8 @@ #define STM32_CFGR_OTGFSPRE 0 -/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: +/* MCO output driven by PLL3. + * From above, we already have PLL3 input frequency as: * * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz * @@ -120,7 +121,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board.h b/boards/arm/stm32/viewtool-stm32f107/include/board.h index 130a319ea0c..197ff65d998 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board.h +++ b/boards/arm/stm32/viewtool-stm32f107/include/board.h @@ -35,11 +35,7 @@ #include "stm32_sdio.h" #include "stm32.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32F107VC) # include @@ -49,10 +45,15 @@ # error Unrecognized STM32 chip #endif -/* LED definitions ******************************************************************/ -/* There are four LEDs on the ViewTool STM32F103/F107 board that can be controlled - * by software: LED1 through LED4. All pulled high and can be illuminated by - * driving the output to low +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* There are four LEDs on the ViewTool STM32F103/F107 board that can be + * controlled by software: LED1 through LED4. All pulled high and can be + * illuminated by driving the output to low * * LED1 PA6 * LED2 PA7 @@ -77,12 +78,13 @@ /* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is * defined. In that case, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related - * events as follows: + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: * * SYMBOL Val Meaning LED state * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- */ + * ----------------- --- ----------------------- ---- ---- ---- ---- + */ #define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ #define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ #define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF OFF */ @@ -93,12 +95,13 @@ #define LED_PANIC 4 /* The system has crashed N/C N/C N/C FLASH */ #undef LED_IDLE /* MCU is is sleep mode Not used */ -/* After booting, LED1-3 are not longer used by the system and can be used for - * other purposes by the application (Of course, all LEDs are available to the - * application if CONFIG_ARCH_LEDS is not defined. +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. */ -/* Buttons **************************************************************************/ +/* Buttons ******************************************************************/ + /* All pulled high and will be sensed low when depressed. * * SW2 PC11 Needs J42 closed diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c index e0ab4ddf189..8fa533e06b5 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c @@ -151,7 +151,8 @@ static struct viewtool_tscinfo_s g_tscinfo = static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) { - FAR struct viewtool_tscinfo_s *priv = (FAR struct viewtool_tscinfo_s *)state; + FAR struct viewtool_tscinfo_s *priv = + (FAR struct viewtool_tscinfo_s *)state; if (isr) { @@ -174,7 +175,8 @@ static int tsc_attach(FAR struct ads7843e_config_s *state, xcpt_t isr) static void tsc_enable(FAR struct ads7843e_config_s *state, bool enable) { - FAR struct viewtool_tscinfo_s *priv = (FAR struct viewtool_tscinfo_s *)state; + FAR struct viewtool_tscinfo_s *priv = + (FAR struct viewtool_tscinfo_s *)state; irqstate_t flags; /* Attach and enable, or detach and disable. Enabling and disabling GPIO @@ -272,7 +274,9 @@ int stm32_tsc_setup(int minor) if (ret < 0) { ierr("ERROR: Failed to register touchscreen device\n"); + /* up_spiuninitialize(dev); */ + return -ENODEV; } diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c index bd28e02671c..a23a9815d3b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c @@ -80,8 +80,9 @@ struct viewtool_ft80xlower_s */ static int ft80x_attach(FAR const struct ft80x_config_s *lower, xcpt_t isr, - FAR void *arg); -static void ft80x_enable(FAR const struct ft80x_config_s *lower, bool enable); + FAR void *arg); +static void ft80x_enable(FAR const struct ft80x_config_s *lower, + bool enable); static void ft80x_clear(FAR const struct ft80x_config_s *lower); static void ft80x_pwrdown(FAR const struct ft80x_config_s *lower, @@ -285,7 +286,9 @@ int stm32_ft80x_setup(void) if (ret < 0) { lcderr("ERROR: Failed to register touchscreen device\n"); + /* up_spiuninitialize(spi); */ + return -ENODEV; } diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c index 76f39755a58..6ca6fa33677 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c @@ -97,16 +97,17 @@ int stm32_sdinitialize(int minor) ret = mmcsd_slotinitialize(minor, sdio); if (ret != OK) { - ferr("ERROR: Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + ferr("ERROR:"); + ferr("Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", STM32_MMCSDSLOTNO, minor); } finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", STM32_MMCSDSLOTNO, minor); - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the M3 Wildfire board supports a GPIO to detect if there is a card in - * the slot. + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the M3 Wildfire board supports a GPIO to detect if there + * is a card in the slot. */ #warning REVISIT: Need to read the current state of the card-detect pin #warning REVISIT: Need to support interrupts from the card-detect pin diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c index 8d62848144c..ee00f5c0c30 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c @@ -88,31 +88,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef CONFIG_VIEWTOOL_FT80X_SPI1 /* Select/de-select the FT80x */ @@ -132,9 +135,9 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) } else #endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -144,9 +147,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef CONFIG_INPUT_ADS7843E /* Select/de-select the touchscreen */ @@ -175,9 +180,9 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) } else #endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -187,9 +192,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c index cccd656faa3..68cd63e3d0d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c @@ -18,6 +18,10 @@ * ****************************************************************************/ +/**************************************************************************** + * Included Files + ****************************************************************************/ + #include #include @@ -67,7 +71,10 @@ #define LCD_BL_TIMER_PERIOD 8999 -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip select signal */ +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip + * select signal + */ + /* RS <==> A16 */ #define LCD_INDEX 0x60000000 /* RS = 0 */ @@ -76,6 +83,7 @@ /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Low Level LCD access */ static void stm32_select(FAR struct ssd1289_lcd_s *dev); @@ -92,75 +100,78 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); /**************************************************************************** * Private Data ****************************************************************************/ + /* LCD * - * An LCD may be connected via J11. Only the STM32F103 supports the FSMC signals - * needed to drive the LCD. + * An LCD may be connected via J11. Only the STM32F103 supports the FSMC + * signals needed to drive the LCD. * - * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, and (a) - * a XPT2046 touch screen controller. + * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, + * and (a) a XPT2046 touch screen controller. * * LCD Connector * ------------- * - * ----------------------------- ------------------------ -------------------------------- - * Connector J11 GPIO CONFIGURATION(s) - * PIN SIGNAL LEGEND (F103 only) LCD Module - * --- ------------- ----------- ------------------------ -------------------------------- - * 1 VDD_5 NC N/A 5V --- - * 2 GND GND N/A GND --- - * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D - * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D - * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D - * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D - * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D - * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D - * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D - * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D - * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D - * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D - * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D - * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D - * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D - * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D - * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D - * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D - * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D - * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D - * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D - * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D - * 23 PB1 LCD_RESET (GPIO) RESET HY32D - * 24 N/C NC N/A TE (unused?) - * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 (Drives LCD backlight) - * 26 GND BL_GND N/A BLGND CA6219 - * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 - * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 - * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 - * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 - * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 - * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 - * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- - * 34 GND GND N/A GND --- - * --- ------------- ----------- ------------------------ -------------------------------- + * ------------------------- --------------------- --------------- + * Connector J11 GPIO CONFIGURATION(s) + * PIN SIGNAL LEGEND (F103 only) LCD Module + * --- --------- ----------- --------------------- --------------- + * 1 VDD_5 NC N/A 5V --- + * 2 GND GND N/A GND --- + * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D + * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D + * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D + * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D + * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D + * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D + * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D + * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D + * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D + * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D + * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D + * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D + * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D + * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D + * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D + * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D + * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D + * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D + * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D + * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D + * 23 PB1 LCD_RESET (GPIO) RESET HY32D + * 24 N/C NC N/A TE (unused?) + * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 + * (Drives LCD backlight) + * 26 GND BL_GND N/A BLGND CA6219 + * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 + * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 + * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 + * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 + * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 + * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 + * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- + * 34 GND GND N/A GND --- + * --- --------- ----------- --------------------- --------------- * * NOTES: * 1) Only the F103 version of the board supports the FSMC * 2) No remap * 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately): * - * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input (active LOW) - * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input - * So will chip enable to either LCD_CS or - * Flash_CS. - * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output - * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output + * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input + * (active LOW) + * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input + * So will chip enable to either LCD_CS or + * Flash_CS. + * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output + * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output * - * Truth Table: - * 1E\ 1A0 1A1 1Y0 1Y1 - * --- --- --- --- --- - * HI N/A N/A HI HI - * LO LO LO LO HI - * LO HI LO HI LO + * Truth Table: + * 1E\ 1A0 1A1 1Y0 1Y1 + * --- --- --- --- --- + * HI N/A N/A HI HI + * LO LO LO LO HI + * LO HI LO HI LO */ const uint16_t fsmc_gpios[] = @@ -277,7 +288,8 @@ static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data) * Name: stm32_backlight * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). * Used here to set pwm duty on timer used for backlight. * ****************************************************************************/ @@ -297,7 +309,8 @@ static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power) * maximum power setting. */ - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / CONFIG_LCD_MAXPOWER; + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * + (uint32_t)power) / CONFIG_LCD_MAXPOWER; if (duty >= LCD_BL_TIMER_PERIOD) { duty = LCD_BL_TIMER_PERIOD - 1; @@ -363,7 +376,7 @@ static void init_lcd_backlight(void) ccer &= !ATIM_CCER_CC2P; - /* Enable channel 2*/ + /* Enable channel 2 */ ccer |= ATIM_CCER_CC2E; @@ -376,7 +389,7 @@ static void init_lcd_backlight(void) modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - /* Enable Backlight Timer !!!!*/ + /* Enable Backlight Timer !!!! */ modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); @@ -429,7 +442,10 @@ static void stm32_selectlcd(void) /* Bank1 NOR/SRAM timing register configuration */ putreg32( - FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)| FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, + FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); /* As ext mode is not active the write timing is ignored!! */ @@ -441,7 +457,9 @@ static void stm32_selectlcd(void) putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - /* Configure the LCD RESET\ pin. Initial value will take the LCD out of reset */ + /* Configure the LCD RESET pin. + * Initial value will take the LCD out of reset + */ stm32_configgpio(GPIO_LCD_RESET); } @@ -461,9 +479,9 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) /* Configure GPIOs */ for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } + { + stm32_configgpio(gpios[i]); + } } /**************************************************************************** @@ -474,9 +492,10 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). * ****************************************************************************/ @@ -517,8 +536,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c index a5d5673881e..751047ac5e8 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c +++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c @@ -55,14 +55,16 @@ * Name: stm32_usbdev_initialize * * Description: - * Called from stm32_boardinitialize very early in initialization to setup USB- - * related GPIO pins for the Viewtool STM32F107 board. + * Called from stm32_boardinitialize very early in initialization to setup + * USB related GPIO pins for the Viewtool STM32F107 board. * ****************************************************************************/ void stm32_usbdev_initialize(void) { - /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ #ifdef CONFIG_ARCH_CHIP_STM32F103VC stm32_configgpio(GPIO_USB_PULLUP); @@ -73,11 +75,11 @@ void stm32_usbdev_initialize(void) * Name: stm32_usbpullup * * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be - * NULL. + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional + * description of this method. Alternatively, if no pull-up GPIO the + * following EXTERN can be redefined to be NULL. * ****************************************************************************/ @@ -94,10 +96,10 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h index 17809726711..8119a800843 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h @@ -35,20 +35,21 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ -/* Four different clock sources can be used to drive the system clock (SYSCLK): +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): * * - HSI high-speed internal oscillator clock * Generated from an internal 8 MHz RC oscillator * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is not - * fitted on the Nucleo-F072RB board. + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the Nucleo-F072RB board. * - PLL clock * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven frequency - * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, - * 2.097 MHz (default value) and 4.194 MHz. + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. * * The devices have the following two secondary clock sources * - LSI low-speed internal RC clock @@ -108,8 +109,8 @@ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ @@ -149,7 +150,7 @@ #define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ /* LEDs * @@ -201,7 +202,7 @@ #define LED_ASSERTION 2 #define LED_PANIC 1 -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ /* Buttons * @@ -214,7 +215,7 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate Pin Functions **********************************************************/ +/* Alternate Pin Functions **************************************************/ /* USART 1 */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c index a5c7537ec75..55df4ad1b15 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c @@ -40,9 +40,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -61,7 +62,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h index 034d5a8c23a..ed300bb1a4f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h @@ -37,18 +37,19 @@ /* Clocking *****************************************************************/ -/* Four different clock sources can be used to drive the system clock (SYSCLK): +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): * * - HSI high-speed internal oscillator clock * Generated from an internal 8 MHz RC oscillator * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is not - * fitted on the Nucleo-F091RC board. + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the Nucleo-F091RC board. * - PLL clock * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven frequency - * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, - * 2.097 MHz (default value) and 4.194 MHz. + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. * * The devices have the following two secondary clock sources * - LSI low-speed internal RC clock @@ -108,8 +109,8 @@ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c index 8f84305dcc1..5eacdb4f497 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c @@ -68,7 +68,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h index ec76bcbba1b..be77183d9ef 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h @@ -37,18 +37,19 @@ /* Clocking *****************************************************************/ -/* Four different clock sources can be used to drive the system clock (SYSCLK): +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): * * - HSI high-speed internal oscillator clock * Generated from an internal 8 MHz RC oscillator * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is not - * fitted on the STM32F0-Discovery board. + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32F0-Discovery board. * - PLL clock * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven frequency - * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, - * 2.097 MHz (default value) and 4.194 MHz. + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. * * The devices have the following two secondary clock sources * - LSI low-speed internal RC clock @@ -108,8 +109,8 @@ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ @@ -155,18 +156,19 @@ * logic on the board and are not available for software control: * * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the ST-LINK/V2. + * communications are in progress between the PC and the + * ST-LINK/V2. * LD2 PWR: Red LED indicates that the board is powered. * * And two LEDs can be controlled by software: * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the STM32F051R8 - * MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the STM32F051R8 - * MCU. + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32F051R8 MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32F051R8 MCU. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -180,8 +182,9 @@ #define BOARD_LED1_BIT (1 << BOARD_LED1) #define BOARD_LED2_BIT (1 << BOARD_LED2) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the - * STM32F0-Discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the STM32F0-Discovery. + * The following definitions describe how NuttX controls the LEDs: * * SYMBOL Meaning LED state * LED1 LED2 @@ -208,11 +211,13 @@ /* Button definitions *******************************************************/ -/* The STM32F0-Discovery supports two buttons; only one button is controllable by - * software: +/* The STM32F0-Discovery supports two buttons; only one button is + * controllable by software: * - * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F051R8. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32F051R8. + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the STM32F051R8. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F051R8. */ #define BUTTON_USER 0 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c index 783a2f88fac..c580fd6bf03 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c @@ -62,7 +62,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h index 8fdda4fb09c..a8f2d988c84 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h @@ -37,18 +37,19 @@ /* Clocking *****************************************************************/ -/* Four different clock sources can be used to drive the system clock (SYSCLK): +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): * * - HSI high-speed internal oscillator clock * Generated from an internal 8 MHz RC oscillator * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is not - * fitted on the STM32F0-Discovery board. + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32F0-Discovery board. * - PLL clock * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. Seven frequency - * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, - * 2.097 MHz (default value) and 4.194 MHz. + * The MSI clock signal is generated from an internal RC oscillator. Seven + * frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, + * 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. * * The devices have the following two secondary clock sources * - LSI low-speed internal RC clock @@ -97,32 +98,32 @@ */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ -#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ #ifdef CONFIG_STM32F0L0G0_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #else # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +# define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ #endif -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output - * frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). */ -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL #ifdef CONFIG_STM32F0L0G0_USB -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else -# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +# define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #endif #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK (48MHz) */ @@ -155,18 +156,20 @@ * logic on the board and are not available for software control: * * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the ST-LINK/V2. + * communications are in progress between the PC and the + * ST-LINK/V2. * LD2 PWR: Red LED indicates that the board is powered. * * And two LEDs can be controlled by software: * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the STM32F072RB - * MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the STM32F072RB - * MCU. + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32F072RB MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32F072RB MCU. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -184,8 +187,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the - * STM32F0-Discovery. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the STM32F0-Discovery. + * The following definitions describe how NuttX controls the LEDs: * * SYMBOL Meaning LED state * LED1 LED2 @@ -212,11 +216,13 @@ /* Button definitions *******************************************************/ -/* The STM32F0-Discovery supports two buttons; only one button is controllable by - * software: +/* The STM32F0-Discovery supports two buttons; only one button is + * controllable by software: * - * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F072RB. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32F072RB. + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the STM32F072RB. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F072RB. */ #define BUTTON_USER 0 @@ -224,7 +230,7 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/* Alternate Pin Functions **********************************************************/ +/* Alternate Pin Functions **************************************************/ /* USART 1 */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c index a6f9826a6fb..42f246abc6a 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c @@ -62,7 +62,7 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be + * function called board_late_initialize(). board_late_initialize() will be * called immediately after up_initialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c index 6c93b2f1936..9e5b82230fd 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_adc.c @@ -77,16 +77,24 @@ */ #ifdef CONFIG_STM32F7_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {3}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 3 +}; /* Configurations of pins used byte each ADC channels * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, - * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, - * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN3}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN3 +}; #endif /**************************************************************************** diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c b/boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c index c1027ba8763..3526cba0673 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c @@ -39,7 +39,6 @@ #ifdef CONFIG_MMCSD - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -122,6 +121,7 @@ int stm32_sdio_initialize(void) #endif /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c index 44c5e23b138..c278d2fa523 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c @@ -50,7 +50,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board. + * Called to configure SPI chip select GPIO pins for the stm32f746g-disco + * board. * ****************************************************************************/ @@ -62,31 +63,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1-6 select and stm32_spi1-6 status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32F7_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -96,9 +100,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -108,9 +114,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -120,9 +128,11 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI4 -void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -132,9 +142,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI5 -void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -144,9 +156,11 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI6 -void stm32_spi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi6select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_autoleds.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_autoleds.c index 5ce0e920a98..59021b10d05 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_autoleds.c @@ -72,11 +72,11 @@ void board_autoled_on(int led) case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ - ledstate = true; /* Set ledstate == false to turn ON */ + ledstate = true; /* Set ledstate == false to turn ON */ break; } - stm32_gpiowrite(GPIO_LD1, ledstate); + stm32_gpiowrite(GPIO_LD1, ledstate); } /**************************************************************************** diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 4fefd9b1df6..73bc92567cf 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -64,7 +64,8 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_SPORADIC_INSTRUMENTATION - /* This configuration has been used for evaluating the NuttX sporadic scheduler. + /* This configuration has been used for evaluating the NuttX sporadic + * scheduler. * The following caqll initializes the sporadic scheduler monitor. */ @@ -86,12 +87,12 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c index 13904198525..99f0f61ee8b 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c @@ -39,6 +39,10 @@ #include "stm32_ltdc.h" #ifdef CONFIG_STM32F7_LTDC +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: up_fbinitialize * @@ -73,7 +77,8 @@ int up_fbinitialize(int display) * * Description: * Return a a reference to the framebuffer object for the specified video - * plane of the specified plane. Many OSDs support multiple planes of video. + * plane of the specified plane. + * Many OSDs support multiple planes of video. * * Input Parameters: * display - In the case of hardware with multiple displays, this diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c index d017ac165a8..67842d62da5 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c @@ -50,7 +50,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f746g-disco board. + * Called to configure SPI chip select GPIO pins for the stm32f746g-disco + * board. * ****************************************************************************/ @@ -62,31 +63,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32F7_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -96,9 +100,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -108,9 +114,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -120,9 +128,11 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI4 -void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -132,9 +142,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI5 -void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 6ade1f7b608..8bbffedb6af 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -41,7 +41,8 @@ /* The STM32F7 Discovery board provides the following clock sources: * - * X2: 25 MHz oscillator for STM32F769NIH6 microcontroller and Ethernet PHY. + * X2: 25 MHz oscillator for STM32F769NIH6 microcontroller + * and Ethernet PHY. * X1: 32.768 KHz crystal for STM32F769NIH6 embedded RTC * * So we have these clock source available within the STM32 @@ -161,8 +162,6 @@ #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 - - /* Configure factors for PLLI2S clock */ #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) @@ -249,15 +248,17 @@ /* LED definitions **********************************************************/ -/* The STM32F769I-DISCO board has numerous LEDs but only one, LD1 located near the - * reset button, that can be controlled by software (LD2 is a power indicator, LD3-6 - * indicate USB status, LD7 is controlled by the ST-Link). +/* The STM32F769I-DISCO board has numerous LEDs but only one, LD1 located + * near the reset button, that can be controlled by software + * (LD2 is a power indicator, LD3-6 indicate USB status, LD7 is controlled + * by the ST-Link). * - * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface. - * One end of LD1 is grounded so a high output on PI1 will illuminate the LED. + * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino + * interface. One end of LD1 is grounded so a high output on PI1 will + * illuminate the LED. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. - * The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -272,8 +273,8 @@ #define BOARD_LED1_BIT (1 << BOARD_LED1) /* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related - * events as follows: + * include/board.h and src/stm32_leds.c. + * The LEDs are used to encode OS-related events as follows: * * SYMBOL Meaning LD1 * ------------------- ----------------------- ------ @@ -302,8 +303,9 @@ /* Button definitions *******************************************************/ -/* The STM32F7 Discovery supports one button: Pushbutton B1, labelled "User", is - * connected to GPIO PA0. A high value will be sensed when the button is depressed. +/* The STM32F7 Discovery supports one button: + * Pushbutton B1, labelled "User", is connected to GPIO PA0. + * A high value will be sensed when the button is depressed. */ #define BUTTON_USER 0 @@ -314,8 +316,8 @@ /* USART6: * - * These configurations assume that you are using a standard Arduio RS-232 shield - * with the serial interface with RX on pin D0 and TX on pin D1: + * These configurations assume that you are using a standard Arduio RS-232 + * shield with the serial interface with RX on pin D0 and TX on pin D1: * * -------- --------------- * STM32F7 @@ -347,8 +349,8 @@ /* PWM * - * The STM32F7 Discovery has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM1 CH4 on PA11. + * The STM32F7 Discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM1 CH4 on PA11. */ #define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 @@ -392,8 +394,8 @@ /* SDMMC */ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 @@ -403,7 +405,7 @@ * DMAMAP_SDMMC2_2 = Channel 11, Stream 5 */ -// #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 +/* #define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 */ #define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 /* SDIO dividers. Note that slower clocking is required when DMA is disabled diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_autoleds.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_autoleds.c index 48f0f70bddc..be6699172ea 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_autoleds.c @@ -72,11 +72,11 @@ void board_autoled_on(int led) case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */ case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */ - ledstate = true; /* Set ledstate == false to turn ON */ + ledstate = true; /* Set ledstate == false to turn ON */ break; } - stm32_gpiowrite(GPIO_LD3, ledstate); + stm32_gpiowrite(GPIO_LD3, ledstate); } /**************************************************************************** diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c index 0dfe72ad5e7..199371c3e6d 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c @@ -50,7 +50,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f769i-disco board. + * Called to configure SPI chip select GPIO pins for the stm32f769i-disco + * board. * ****************************************************************************/ @@ -62,31 +63,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32F7_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -96,9 +100,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -108,9 +114,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -120,9 +128,11 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI4 -void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -132,9 +142,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32F7_SPI5 -void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c index 40fcc6f4c96..ff12e3be2a1 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c @@ -87,7 +87,9 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ stm32_bringup(); #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c index 7e17d20069d..15eddcbd02e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c @@ -77,29 +77,31 @@ void stm32_spidev_initialize(void) * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32H7_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, selected ? "assert" : "de-assert"); @@ -112,7 +114,8 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32H7_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, selected ? "assert" : "de-assert"); @@ -125,13 +128,15 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32H7_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { switch (devid) { #ifdef CONFIG_WL_NRF24L01 case SPIDEV_WIRELESS(0): - spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted"); + spiinfo("nRF24L01 device %s\n", + selected ? "asserted" : "de-asserted"); /* Set the GPIO low to select and high to de-select */ @@ -162,7 +167,8 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32H7_SPI4 -void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, selected ? "assert" : "de-assert"); @@ -175,7 +181,8 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32H7_SPI5 -void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, selected ? "assert" : "de-assert"); @@ -188,7 +195,8 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32H7_SPI6 -void stm32_spi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi6select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, selected ? "assert" : "de-assert"); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c index c9fe7aceafc..19d57c21bb6 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c @@ -87,7 +87,9 @@ void stm32_boardinitialize(void) void board_late_initialize(void) { #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ (void)stm32_bringup(); #endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c index bf624fe04a7..a720cc30315 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c @@ -80,8 +80,8 @@ void stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 9e0edcfc096..2d26e27ac01 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -34,7 +34,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ #if 1 # define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */ @@ -47,27 +47,32 @@ #endif #if defined(HSI_CLOCK_CONFIG) -/* The STMicro IoT board supports both HSE and LSE crystals. As shipped, the HSE - * crystal (X1) is not populated. Therefore the STMicro IoT board will need to run off the - * 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal. +/* The STMicro IoT board supports both HSE and LSE crystals. As shipped, the + * HSE crystal (X1) is not populated. Therefore the STMicro IoT board will + * need to run off the 16MHz HSI clock, or the 32khz-synced MSI, unless you + * install the HSE xtal. * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) - * PLLSAI1N : 12 - * PLLSAI1Q : 4 - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * 48MHz for USB SDMMC OTG FS, : Doable if required using PLLSAI1 or MSI + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 80000000 Determined by PLL configuration + * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * (Max 80 MHz) + * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * (Max 80 MHz) + * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * (Max 80 MHz) + * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * (Max 80 MHz) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 1 (STM32L4_PLLCFG_PLLM) + * PLLN : 10 (STM32L4_PLLCFG_PLLN) + * PLLP : 0 (STM32L4_PLLCFG_PLLP) + * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) + * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLSAI1N : 12 + * PLLSAI1Q : 4 + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * 48MHz for USB SDMMC OTG FS, : Doable if required using PLLSAI1 or MSI * SDIO and RNG clock */ @@ -96,11 +101,19 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8 - * VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz - * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable - * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable - * PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable + * VCO input frequency = PLL input clock frequency / PLLM, + * 1 <= PLLM <= 8 + * VCO output frequency = VCO input frequency × PLLN, + * 8 <= PLLN <= 86, + * frequency range 64 to 344 MHz + * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, + * PLLP = 7, or 17, or 0 to disable + * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * PLL output R (CLK) clock frequency = VCO frequency / PLLR, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * PLL output P is used for SAI * PLL output Q is used for OTG FS, SDMMC, RNG @@ -137,10 +150,18 @@ * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency - * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable - * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable - * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -155,9 +176,15 @@ * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency - * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable - * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -165,11 +192,14 @@ * * ---------------------------------------- * - * TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime. + * TODO: + * The STM32L is a low power peripheral and all these clocks should be + * configurable at runtime. * * ---------------------------------------- * - * TODO These clock sources can be configured in Kconfig (this is not a board feature) + * TODO These clock sources can be configured in Kconfig + * (this is not a board feature) * USART1 * USART2 * USART3 @@ -190,16 +220,17 @@ */ /* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly - as per comment above HSI) */ + * as per comment above HSI) + */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: currently the main PLL is implicitly turned on and is + * implicitly the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index e36b153107b..ee064f7c5e7 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -124,31 +124,34 @@ void weak_function stm32l4_spidev_initialize(void) * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32l4_spi1/2/3select and + * stm32l4_spi1/2/3status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including up_spiinitialize()) are provided by + * common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. + * 1. Provide logic in stm32l4_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -158,9 +161,11 @@ uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -170,9 +175,11 @@ uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef HAVE_SPSGRF if (devid == SPIDEV_WIRELESS(0)) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c index e36411052b7..d39d4422f01 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c @@ -77,7 +77,7 @@ struct stm32l4_priv_s * * stm32l4_reset - Reset the Spirit part. * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO - interrupt + * interrupt * stm32l4_enable_irq - Enable or disable the GPIO interrupt */ @@ -214,8 +214,8 @@ static int stm32l4_spirit_devsetup(FAR struct stm32l4_priv_s *priv) * powers down the Spirit. */ - stm32l4_configgpio(priv->intcfg); - stm32l4_configgpio(priv->sdncfg); + stm32l4_configgpio(priv->intcfg); + stm32l4_configgpio(priv->sdncfg); /* Initialize the SPI bus and get an instance of the SPI interface */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c index c4dcecbab3a..e70a30971b1 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c @@ -189,7 +189,8 @@ static int stm32gpio_interrupt(int irq, void *context, void *arg) DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, stm32gpint->stm32gpio.id); + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index 6e754b43871..7c4fae073e8 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -61,7 +61,8 @@ struct spi_dev_s *g_spi2; * Name: stm32l4_spiinitialize * * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-L432KC board. + * Called to configure SPI chip select GPIO pins for the Nucleo-L432KC + * board. * ****************************************************************************/ @@ -108,22 +109,23 @@ void stm32l4_spiinitialize(void) * Name: stm32l4_spi1/2select and stm32l4_spi1/2status * * Description: - * The external functions, stm32l4_spi1/2select and stm32l4_spi1/2status must - * be provided by board-specific logic. They are implementations of the - * select and status methods of the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods (including - * up_spiinitialize()) are provided by common STM32 logic. To use this common - * SPI logic on your board: + * The external functions, stm32l4_spi1/2select and stm32l4_spi1/2status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * up_spiinitialize()) are provided by common STM32 logic. To use this + * common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip select - * pins. - * 2. Provide stm32l4_spi1/2select() and stm32l4_spi1/2status() functions in - * your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. + * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * select pins. + * 2. Provide stm32l4_spi1/2select() and stm32l4_spi1/2status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -156,7 +158,6 @@ void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - } uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32l4/nucleo-l452re/include/board.h b/boards/arm/stm32l4/nucleo-l452re/include/board.h index 4e436e432e5..1e1f852168b 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/board.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/board.h @@ -30,16 +30,16 @@ # include #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* Clocking *****************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32L452RE) # include #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* DMA Channel/Stream Selections ********************************************/ /* Stream selections are arbitrary for now but might become important in @@ -187,7 +187,8 @@ /* Buttons * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 * microcontroller. */ diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 9265b75a2b8..7babdcfaf7b 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -34,30 +34,30 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ -/* The NUCLEOL452RE supports both HSE and LSE crystals (X2 and X3). However, as - * shipped, the X3 crystal is not populated. Therefore the Nucleo-L452RE +/* The NUCLEOL452RE supports both HSE and LSE crystals (X2 and X3). However, + * as shipped, the X3 crystal is not populated. Therefore the Nucleo-L452RE * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI. * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) - * PLLSAI1N : 12 - * PLLSAI1Q : 4 - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI - * SDIO and RNG clock + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 80000000 Determined by PLL configuration + * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 1 (STM32L4_PLLCFG_PLLM) + * PLLN : 10 (STM32L4_PLLCFG_PLLN) + * PLLP : 0 (STM32L4_PLLCFG_PLLP) + * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) + * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLSAI1N : 12 + * PLLSAI1Q : 4 + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI + * SDIO and RNG clock */ /* HSI - 16 MHz RC factory-trimmed @@ -95,11 +95,20 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8 - * VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz - * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable - * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable - * PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable + * VCO input frequency = PLL input clock frequency / PLLM, + * 1 <= PLLM <= 8 + * VCO output frequency = VCO input frequency × PLLN, + * 8 <= PLLN <= 86, + * frequency range 64 to 344 MHz + * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, + * PLLP = 7, or 17, + * or 0 to disable + * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * PLL output R (CLK) clock frequency = VCO frequency / PLLR, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * PLL output P is used for SAI * PLL output Q is used for OTG FS, SDMMC, RNG @@ -136,10 +145,18 @@ * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency - * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable - * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable - * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -154,9 +171,15 @@ * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency - * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable - * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -164,11 +187,15 @@ * * ---------------------------------------- * - * TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime. + * TODO: + * The STM32L is a low power peripheral and all these clocks should be + * configurable at runtime. * * ---------------------------------------- * - * TODO These clock sources can be configured in Kconfig (this is not a board feature) + * TODO + * These clock sources can be configured in Kconfig + * (this is not a board feature) * USART1 * USART2 * USART3 @@ -189,15 +216,17 @@ */ /* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly - as per comment above HSI) */ + * as per comment above HSI) + */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly the + * system clock; this should be configurable since not all applications may * want things done this way. */ @@ -454,8 +483,8 @@ #endif /* The timer clock frequencies are automatically defined by hardware. - * If the APB prescaler equals 1, the timer clock frequencies are set to the same - * frequency as that of the APB domain. Otherwise they are set to twice. + * If the APB prescaler equals 1, the timer clock frequencies are set to the + * same frequency as that of the APB domain. Otherwise they are set to twice. * Note: TIM1,15,16 are on APB2, others on APB1 */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index 6e10eea68fd..b79b47bde6f 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -44,6 +44,7 @@ /**************************************************************************** * Public Data ****************************************************************************/ + /* Global driver instances */ #ifdef CONFIG_STM32L4_SPI1 @@ -96,31 +97,34 @@ void weak_function stm32l4_spiinitialize(void) * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32l4_spi1/2/3select and + * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including up_spiinitialize()) are provided by common + * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip select - * pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. + * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * select pins. + * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) @@ -137,9 +141,11 @@ uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -149,9 +155,11 @@ uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +void stm32l4_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/board.h b/boards/arm/stm32l4/nucleo-l476rg/include/board.h index c779cbffb90..714427de0c4 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/board.h @@ -30,22 +30,22 @@ # include #endif -/* Do not include STM32 L4 header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* Clocking *****************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32L476RG) # include #endif +/* Do not include STM32 L4 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* DMA Channel/Stream Selections ********************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * is we set aside more DMA channels/streams. +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. */ /* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h */ @@ -212,7 +212,8 @@ /* Buttons * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32 + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 * microcontroller. */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index ba3ca919308..4f5ec43f465 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -47,27 +47,27 @@ /* Clocking *****************************************************************/ #if defined(HSI_CLOCK_CONFIG) -/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However, as - * shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG +/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However, + * as shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI. * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) - * PLLSAI1N : 12 - * PLLSAI1Q : 4 - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 80000000 Determined by PLL configuration + * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 1 (STM32L4_PLLCFG_PLLM) + * PLLN : 10 (STM32L4_PLLCFG_PLLN) + * PLLP : 0 (STM32L4_PLLCFG_PLLP) + * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) + * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLSAI1N : 12 + * PLLSAI1Q : 4 + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI * SDIO and RNG clock */ @@ -94,11 +94,20 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8 - * VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz - * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable - * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable - * PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable + * VCO input frequency = PLL input clock frequency / PLLM, + * 1 <= PLLM <= 8 + * VCO output frequency = VCO input frequency × PLLN, + * 8 <= PLLN <= 86, + * frequency range 64 to 344 MHz + * PLL output P (SAI3) clock frequency = VCO frequency / PLLP, + * PLLP = 7, or 17, + * or 0 to disable + * PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * PLL output R (CLK) clock frequency = VCO frequency / PLLR, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * PLL output P is used for SAI * PLL output Q is used for OTG FS, SDMMC, RNG @@ -135,10 +144,18 @@ * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency - * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable - * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable - * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, + * PLLQ = 2, 4, 6, or 8, + * or 0 to disable + * SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -153,9 +170,15 @@ * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency - * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz - * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable - * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable + * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, + * 8 <= PLLSAI1N <= 86, + * frequency range 64 to 344 MHz + * SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, + * PLLP = 7, or 17, + * or 0 to disable + * SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, + * PLLR = 2, 4, 6, or 8, + * or 0 to disable * * We will configure like this * @@ -163,11 +186,14 @@ * * ---------------------------------------- * - * TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime. + * TODO: + * The STM32L is a low power peripheral and all these clocks should be + * configurable at runtime. * * ---------------------------------------- * - * TODO These clock sources can be configured in Kconfig (this is not a board feature) + * TODO These clock sources can be configured in Kconfig + * (this is not a board feature) * USART1 * USART2 * USART3 @@ -196,9 +222,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 13b24832602..9cee00c5707 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -54,28 +54,43 @@ /**************************************************************************** * Private Data ****************************************************************************/ + /* Identifying number of each ADC channel. */ #ifdef CONFIG_AJOYSTICK #ifdef CONFIG_ADC_DMA /* The Itead analog joystick gets inputs on ADC_IN1 and ADC_IN2 */ -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = {1, 2}; +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 1, + 2 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1, GPIO_ADC1_IN2}; +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1, + GPIO_ADC1_IN2 +}; #else /* Without DMA, only a single channel can be supported */ /* The Itead analog joystick gets input on ADC_IN1 */ -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = {1}; +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; /* Configurations of pins used byte each ADC channels */ -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; #endif /* CONFIG_ADC_DMA */ #endif /* CONFIG_AJOYSTICK */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index c51295f4e7b..2ba712137e9 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -98,10 +98,12 @@ * Private Function Prototypes ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower); static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, FAR struct ajoy_sample_s *sample); -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower); static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, ajoy_buttonset_t press, ajoy_buttonset_t release, ajoy_handler_t handler, FAR void *arg); @@ -163,7 +165,8 @@ static FAR void *g_ajoyarg; * ****************************************************************************/ -static ajoy_buttonset_t ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_supported(FAR const struct ajoy_lowerhalf_s *lower) { iinfo("Supported: %02x\n", AJOY_SUPPORTED); return (ajoy_buttonset_t)AJOY_SUPPORTED; @@ -278,7 +281,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * ****************************************************************************/ -static ajoy_buttonset_t ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) +static ajoy_buttonset_t +ajoy_buttons(FAR const struct ajoy_lowerhalf_s *lower) { ajoy_buttonset_t ret = 0; int i; @@ -344,26 +348,26 @@ static void ajoy_enable(FAR const struct ajoy_lowerhalf_s *lower, for (i = 0; i < AJOY_NGPIOS; i++) { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); - iinfo("GPIO %d: rising: %d falling: %d\n", + iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32l4_gpiosetevent(g_joygpio[i], rising, falling, + stm32l4_gpiosetevent(g_joygpio[i], rising, falling, true, ajoy_interrupt, NULL); - } + } } } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c index 192fef924d1..a08d1e86511 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c @@ -138,18 +138,21 @@ static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; static int stm32gpio_interrupt(int irq, void *context, void *arg) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)arg; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)arg; DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, tm32gpint->stm32gpio.id); + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + tm32gpint->stm32gpio.id); return OK; } static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL && value != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); @@ -161,7 +164,8 @@ static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL && value != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); @@ -173,7 +177,8 @@ static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpout_write(FAR struct gpio_dev_s *dev, bool value) { - FAR struct stm32gpio_dev_s *stm32gpio = (FAR struct stm32gpio_dev_s *)dev; + FAR struct stm32gpio_dev_s *stm32gpio = + (FAR struct stm32gpio_dev_s *)dev; DEBUGASSERT(stm32gpio != NULL); DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); @@ -185,7 +190,8 @@ static int gpout_write(FAR struct gpio_dev_s *dev, bool value) static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; DEBUGASSERT(stm32gpint != NULL && value != NULL); DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); @@ -198,7 +204,8 @@ static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value) static int gpint_attach(FAR struct gpio_dev_s *dev, pin_interrupt_t callback) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; gpioinfo("Attaching the callback\n"); @@ -214,7 +221,8 @@ static int gpint_attach(FAR struct gpio_dev_s *dev, static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable) { - FAR struct stm32gpint_dev_s *stm32gpint = (FAR struct stm32gpint_dev_s *)dev; + FAR struct stm32gpint_dev_s *stm32gpint = + (FAR struct stm32gpint_dev_s *)dev; if (enable) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index 958de95d372..8d17daa9b77 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -75,13 +75,15 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM interface */ + /* Call stm32l4_pwminitialize() to get an instance of the PWM + * interface + */ /* PWM * - * The Nucleo-l476rg has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM1 or 8, or others (see board.h). - * Let's figure out which the user has configured. + * The Nucleo-l476rg has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM1 or 8, or others + * (see board.h). Let's figure out which the user has configured. */ #if defined(CONFIG_STM32L4_TIM1_PWM) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c index b88d6903e28..5cba9604719 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c @@ -43,8 +43,8 @@ * Name: qe_devinit * * Description: - * All STM32L4 architectures must provide the following interface to work with - * examples/qencoder. + * All STM32L4 architectures must provide the following interface to work + * with examples/qencoder. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index f39dfe53bdc..da027fa6703 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -44,6 +44,7 @@ /**************************************************************************** * Public Data ****************************************************************************/ + /* Global driver instances */ #ifdef CONFIG_STM32L4_SPI1 @@ -61,7 +62,8 @@ struct spi_dev_s *g_spi2; * Name: stm32l4_spiinitialize * * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG board. + * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG + * board. * ****************************************************************************/ @@ -105,31 +107,35 @@ void weak_function stm32l4_spiinitialize(void) * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your + * The external functions, stm32l4_spi1/2/3select and + * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including up_spiinitialize()) are provided by common + * STM32 logic. To use this common SPI logic on your * board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip select - * pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. + * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * select pins. + * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef HAVE_MMCSD_SPI if (devid == SPIDEV_MMCSD(0)) @@ -162,9 +168,11 @@ uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef CONFIG_WL_CC1101 if (devid == SPIDEV_WIRELESS(5)) @@ -181,9 +189,11 @@ uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +void stm32l4_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index e7780799d7a..4b14b49f1a7 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -76,26 +76,50 @@ */ #ifdef CONFIG_STM32L4_ADC1 -static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] = {3}; +static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] = +{ + 3 +}; /* Configurations of pins used by each ADC channels * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, - * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, - * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; */ -static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] = {GPIO_ADC1_IN3}; +static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN3 +}; #endif #ifdef CONFIG_STM32L4_ADC2 -static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] = {4,17,18}; /* IN4, DAC1 and DAC2 */ -static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] = {GPIO_ADC1_IN4, 0, 0}; +static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] = +{ + 4, + 17, + 18 +}; /* IN4, DAC1 and DAC2 */ +static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] = +{ + GPIO_ADC1_IN4, 0, 0 +}; #endif #ifdef CONFIG_STM32L4_ADC3 -static const uint8_t g_chanlist_adc3[ADC3_NCHANNELS] = {17,18}; /* TS and VBAT/3 */ -static const uint32_t g_pinlist_adc3[ADC3_NCHANNELS] = {0,0}; +static const uint8_t g_chanlist_adc3[ADC3_NCHANNELS] = +{ + 17, + 18 +}; /* TS and VBAT/3 */ +static const uint32_t g_pinlist_adc3[ADC3_NCHANNELS] = +{ + 0, + 0 +}; #endif /**************************************************************************** @@ -157,7 +181,9 @@ int stm32_adc_setup(void) } #endif - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32l4_adc_initialize() to get an instance of the ADC + * interface + */ #ifdef CONFIG_STM32L4_ADC1 adc = stm32l4_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c index e794105b4b9..b8aa41f57fa 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c @@ -39,7 +39,6 @@ #ifdef CONFIG_MMCSD - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -122,6 +121,7 @@ int stm32l4_sdio_initialize(void) #endif /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c index f0864200fb4..df790255e68 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c @@ -29,13 +29,13 @@ * When the I/O is HIGH value, the LED is OFF. * When the I/O is LOW, the LED is ON. * - * Following this convention, only the white LED is made available even though - * they all could be user-application controlled if desired. + * Following this convention, only the white LED is made available even + * though they all could be user-application controlled if desired. * - * None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is defined. - * In that case, the white LED (only) will be controlled. Usage by the board port - * is defined in include/board.h and src/stm32_autoleds.c. The white LED will be - * used to encode OS-related events as follows: + * None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the white LED (only) will be controlled. Usage + * by the board port is defined in include/board.h and src/stm32_autoleds.c. + * The white LED will be used to encode OS-related events as follows: * * ------------------ ------------------------ ------ * SYMBOL Meaning LED @@ -51,9 +51,10 @@ * LED_PANIC The system has crashed FLASH * LED_IDLE MCU is is sleep mode Not used * - * Thus if the white LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If white LED is flashing at approximately 2Hz, - * then a fatal error has been detected and the system has halted. + * Thus if the white LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If white LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system has + * halted. */ /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c index 361624aa7dd..01cbd8a5afe 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c @@ -90,31 +90,34 @@ void weak_function stm32_spiinitialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including up_spiinitialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -124,9 +127,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -136,9 +141,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c index ec10ec80543..b2eabea83fe 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c @@ -43,6 +43,7 @@ /**************************************************************************** * Public Data ****************************************************************************/ + /* Global driver instances */ #ifdef CONFIG_STM32_SPI1 @@ -112,31 +113,34 @@ void weak_function stm32_spiinitialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including up_spiinitialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including up_spiinitialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. * 3. Add a calls to up_spiinitialize() in your low level application * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 4. The handle returned by up_spiinitialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) @@ -153,9 +157,11 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -165,9 +171,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h index 5b7b9636194..69bb60848be 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h @@ -32,14 +32,14 @@ /* Do not include STM32 L4 header files here */ -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /* Clocking *****************************************************************/ #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* DMA Channel/Stream Selections ********************************************/ /* Stream selections are arbitrary for now but might become important in the @@ -52,10 +52,10 @@ #if 0 -#define DMACHAN_SDMMC DMACHAN_SDMMC_1 /* 2 choices * / +#define DMACHAN_SDMMC DMACHAN_SDMMC_1 /* 2 choices */ -#define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 /* 2 choices * / -#define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 /* 2 choices * / +#define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 /* 2 choices */ +#define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 /* 2 choices */ /* UART RX DMA configurations */ @@ -106,7 +106,6 @@ #define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */ #define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */ - /* I2C * * The optional GPIO configurations allow the I2C driver to manually @@ -129,7 +128,9 @@ /* XXX Is I2C2 used on Disco? */ -/* I2C3 connects to Arduino Uno V3 connector pins D15 (I2C3_SCL) and D14 (I2C3_SDA). */ +/* I2C3 connects to Arduino Uno V3 connector pins + * D15 (I2C3_SCL) and D14 (I2C3_SDA). + */ #define GPIO_I2C3_SCL (GPIO_I2C3_SCL_2|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET) #define GPIO_I2C3_SDA (GPIO_I2C3_SDA_2|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET) @@ -180,7 +181,8 @@ /* LEDs * - * The STM32L4R9AI-DISCO board provides two user LEDs, LD1 (orange) and LD2 (green). + * The STM32L4R9AI-DISCO board provides two user LEDs, + * LD1 (orange) and LD2 (green). * * PB0 is LD1 (orange) * PH4 is LD2 (green) @@ -204,8 +206,8 @@ * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode * OS-related events as follows when the red and green LEDs are available: * - * SYMBOL Meaning BOARD_LED_GRN BOARD_LED_RED - * ------------------- ----------------------- ----------- ------------ + * SYMBOL Meaning BOARD_LED_GRN BOARD_LED_RED + * ------------------- --------------------- ----------- ------------ * LED_STARTED NuttX has been started * LED_HEAPALLOCATE Heap has been allocated * LED_IRQSENABLED Interrupts enabled @@ -216,9 +218,9 @@ * LED_PANIC The system has crashed Blinking * LED_IDLE MCU is is sleep mode ON * - * Thus if BOARD_LED_GRN, NuttX has successfully booted and is, apparently, running - * normally. If BOARD_LED_RED is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. + * Thus if BOARD_LED_GRN, NuttX has successfully booted and is, apparently, + * running normally. If BOARD_LED_RED is flashing at approximately 2Hz, then + * a fatal error has been detected and the system has halted. */ #define LED_STARTED 0 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index cb96d40d2a5..d7ba2a308ce 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -40,12 +40,13 @@ * Name: stm32_board_clockconfig * * Description: - * I provided this module when I was doing some debugging of a problem I had with - * clocking (it was helpful to do A/B tests). I'm leaving it here in the config - * partially because I expect to have similar problems again as I develop more of - * the various peripheral support, but also because it may become necessary in the - * end for certain project configurations which have specialized clock configurations - * that aren't appropriate to expose in the 'arch' default code. + * I provided this module when I was doing some debugging of a problem I + * had with clocking (it was helpful to do A/B tests). I'm leaving it here + * in the config partially because I expect to have similar problems again + * as I develop more of the various peripheral support, but also because it + * may become necessary in the end for certain project configurations which + * have specialized clock configurations that aren't appropriate to expose + * in the 'arch' default code. * ****************************************************************************/ @@ -92,6 +93,7 @@ void stm32l4_board_clockconfig(void) regval = getreg32(STM32L4_RCC_PLLCFG); /* Configure Main PLL */ + /* Set the PLL dividers and multipliers to configure the main PLL */ regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP @@ -167,7 +169,9 @@ void stm32l4_board_clockconfig(void) { } - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Enable FLASH prefetch, instruction cache, + * data cache, and 5 wait states + */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | @@ -186,7 +190,8 @@ void stm32l4_board_clockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -194,7 +199,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32l4_rcc_enablelsi(); #endif #if defined(STM32L4_USE_LSE) diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index d38fe7827db..8ce4c1bff24 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -79,6 +79,7 @@ void weak_function stm32_spiinitialize(void) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); } + #ifdef CONFIG_SPI_DRIVER spi_register(g_spi1, 1); #endif @@ -96,6 +97,7 @@ void weak_function stm32_spiinitialize(void) { spierr("ERROR: [boot] FAILED to initialize SPI port 2\n"); } + #ifdef CONFIG_SPI_DRIVER spi_register(g_spi2, 2); #endif @@ -111,6 +113,7 @@ void weak_function stm32_spiinitialize(void) { spierr("ERROR: [boot] FAILED to initialize SPI port 3\n"); } + #ifdef CONFIG_SPI_DRIVER spi_register(g_spi3, 3); #endif @@ -123,31 +126,34 @@ void weak_function stm32_spiinitialize(void) * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32l4_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32l4_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) @@ -164,9 +170,11 @@ uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32l4_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -176,9 +184,11 @@ uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +void stm32l4_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32l4_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)