Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-07 09:18:00 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix nxstyle issue

Browse Source 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
2020-05-05 01:34:04 +08:00
committed by patacongo
parent de33f86ae3
commit b7d922960f
35 changed files with 622 additions and 584 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/lcd/ft80x.c
+2 -2
View File
@@ -417,7 +417,7 @@ static int ft80x_interrupt(int irq, FAR void *context, FAR void *arg)
DEBUGASSERT(priv != NULL);
/* Schedule to perform the interrupt work on the high priority work queue. */
/* Perform the interrupt work on the high priority work queue. */
work_queue(HPWORK, &priv->intwork, ft80x_interrupt_work, priv, 0);
@@ -1455,7 +1455,7 @@ static int ft80x_initialize(FAR struct ft80x_dev_s *priv)
/* 7. Enable back light control for display */
#warning Missing logic
/* 8. Write FT80X_REG_PCLK, video output begins with the first display list */
/* 8. Write FT80X_REG_PCLK, video output with the first display list */
#if defined(CONFIG_LCD_FT80X_WQVGA)
ft80x_write_byte(priv, FT80X_REG_PCLK, 5);
drivers/mmcsd/mmcsd_sdio.c
+4 -4
View File
@@ -1786,7 +1786,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv,
if ((priv->caps & SDIO_CAPS_DMABEFOREWRITE) == 0)
{
/* Send CMD24, WRITE_BLOCK, and verify that good R1 status is returned */
/* Send CMD24, WRITE_BLOCK, and verify good R1 status is returned */
mmcsd_sendcmdpoll(priv, MMCSD_CMD24, offset);
ret = mmsd_recv_r1(priv, MMCSD_CMD24);
@@ -1823,7 +1823,7 @@ static ssize_t mmcsd_writesingle(FAR struct mmcsd_state_s *priv,
if ((priv->caps & SDIO_CAPS_DMABEFOREWRITE) != 0)
{
/* Send CMD24, WRITE_BLOCK, and verify that good R1 status is returned */
/* Send CMD24, WRITE_BLOCK, and verify good R1 status is returned */
mmcsd_sendcmdpoll(priv, MMCSD_CMD24, offset);
ret = mmsd_recv_r1(priv, MMCSD_CMD24);
@@ -3276,7 +3276,7 @@ static int mmcsd_cardidentify(FAR struct mmcsd_state_s *priv)
priv->type |= MMCSD_CARDTYPE_BLOCK;
}
/* And break out of the loop with an SD card identified */
/* And break out of the loop with an card identified */
break;
}
@@ -3432,7 +3432,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv)
}
else
{
/* Then initialize the driver according to the identified card type */
/* Then initialize the driver according to the card type */
switch (priv->type)
{
drivers/mtd/sst39vf.c
+80 -93
View File
@@ -91,17 +91,8 @@
struct sst39vf_chip_s
{
#if 0 /* Not used */
bool top; /* Top protect SST39VF1602/3202 */
#endif
uint16_t chipid; /* ID of the chip */
#if 0 /* Not used */
uint16_t nblocks; /* Number of erase blocks */
#endif
uint16_t nsectors; /* Number of erase-ablesectors */
#if 0 /* Not used */
uint32_t blocksize; /* Size of one erase block */
#endif
uint32_t sectorsize; /* Size of one sector */
};
@@ -130,7 +121,8 @@ struct sst39vf_dev_s
/* Low Level Helpers */
static inline void sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo);
static inline void
sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo);
static inline uint16_t sst39vf_flashread(uintptr_t address);
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo,
int nseq);
@@ -159,41 +151,29 @@ static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd,
static const struct sst39vf_chip_s g_sst39vf1601 =
{
/* false, top - Bottom hardware block protection */
0x234b, /* chipid */
/* 32, nblocks */
512, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf1602 =
{
/* true, top - Top hardware block protection */
0x234a, /* chipid */
/* 32, nblocks */
512, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf3201 =
{
/* false, top - Bottom hardware block protection */
0x235b, /* chipid */
/* 64, nblocks */
1024, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
static const struct sst39vf_chip_s g_sst39vf3202 =
{
/* true, top - Top hardware block protection */
0x235a, /* chipid */
/* 64, nblocks */
1024, /* nsectors */
/* 64 * 1024, blocksize */
4 * 1024 /* sectorsize */
};
@@ -219,80 +199,84 @@ static struct sst39vf_dev_s g_sst39vf =
static const struct sst39vf_wrinfo_s g_wordprogram[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00a0} /* , {address, data} */
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x00a0
}
};
static const struct sst39vf_wrinfo_s g_sectorerase[5] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
{0x5555, 0x00aa}, {0x2aaa, 0x0055} /* , {sector, 0x0030} */
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0080
},
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_blockerase[5] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x80},
{0x5555, 0x00aa}, {0x2aaa, 0x0055} /* , {block, 0x0050} */
};
#endif
static const struct sst39vf_wrinfo_s g_chiperase[6] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0010}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0080
},
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0010
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_erasesuspend[1] =
{
{0x5555, 0x00aa}
};
static const struct sst39vf_wrinfo_s g_eraseresume[1] =
{
{0x5555, 0x00aa}
};
static const struct sst39vf_wrinfo_s g_querysecid[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0088}
};
static const struct sst39vf_wrinfo_s g_securityid_wordprogram[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00a5}, /* {address, data} */
};
static const struct sst39vf_wrinfo_s g_securityid_lockout[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0085} /* {0xXX, 0x0000} */
};
#endif
static const struct sst39vf_wrinfo_s g_swid_entry[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0090}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x0090
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_cfiquery[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x0080},
};
#endif
static const struct sst39vf_wrinfo_s g_swid_exit[3] =
{
{0x5555, 0x00aa}, {0x2aaa, 0x0055}, {0x5555, 0x00f0}
{
0x5555, 0x00aa
},
{
0x2aaa, 0x0055
},
{
0x5555, 0x00f0
}
};
#if 0 /* Not used */
static const struct sst39vf_wrinfo_s g_swid_exit2[1] =
{
{0x0000, 0x00f0},
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -305,7 +289,8 @@ static const struct sst39vf_wrinfo_s g_swid_exit2[1] =
*
****************************************************************************/
static inline void sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo)
static inline void
sst39vf_flashwrite(FAR const struct sst39vf_wrinfo_s *wrinfo)
{
volatile uint16_t *addr = SST39VF_ADDR(wrinfo->address);
*addr = wrinfo->data;
@@ -332,7 +317,8 @@ static inline uint16_t sst39vf_flashread(uintptr_t address)
*
****************************************************************************/
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo, int nseq)
static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo,
int nseq)
{
while (nseq--)
{
@@ -361,8 +347,8 @@ static void sst39vf_writeseq(FAR const struct sst39vf_wrinfo_s *wrinfo, int nseq
* "An additional Toggle Bit is available on DQ2, which can be used in
* conjunction with DQ6 to check whether a particular sector is being
* actively erased or erase-suspended. ... The Toggle Bit (DQ2) is valid
* after the rising edge of the last WE# (or CE#) pulse of Write operation.
* ..."
* after the rising edge of the last WE# (or CE#) pulse of Write
* operation."
*
****************************************************************************/
@@ -406,12 +392,12 @@ static int sst39vf_waittoggle(FAR const struct sst39vf_wrinfo_s *wrinfo,
* Erase the entire chip
*
* "The SST39VF160x/320x provide a Chip-Erase operation, which allows the
* user to erase the entire memory array to the “1” state. This is useful
* when the entire device must be quickly erased. The Chip-Erase operation
* is initiated by executing a six-byte command sequence with Chip-Erase
* command (10H) at address 5555H in the last byte sequence. The Erase
* operation begins with the rising edge of the sixth WE# or CE#,
* whichever occurs first. During the Erase operation, the only valid
* user to erase the entire memory array to the “1” state. This is
* useful when the entire device must be quickly erased. The Chip-Erase
* operation is initiated by executing a six-byte command sequence with
* Chip-Erase command (10H) at address 5555H in the last byte sequence.
* The Erase operation begins with the rising edge of the sixth WE# or
* CE#, whichever occurs first. During the Erase operation, the only valid
* read is Toggle Bit or Data# Polling... Any commands issued during the
* Chip-Erase operation are ignored. When WP# is low, any attempt to
* Chip-Erase will be ignored. During the command sequence, WP# should
@@ -557,8 +543,8 @@ static int sst39vf_sectorerase(FAR struct sst39vf_dev_s *priv,
* programming, the sector where the word exists must be fully erased. The
* rogram operation is accomplished in three steps. The first step is the
* three-byte load sequence for Software Data Protection. The second step
* is to load word address and word data. During the Word-Program operation,
* the addresses are latched on the falling edge of either CE# or WE#,
* is to load word address and word data. During the Word-Program operation
* , the addresses are latched on the falling edge of either CE# or WE#,
* whichever occurs last. The data is latched on the rising edge of either
* CE# or WE#, whichever occurs first. The third step is the internal
* Program operation which is initiated after the rising edge of the
@@ -725,7 +711,8 @@ static ssize_t sst39vf_read(FAR struct mtd_dev_s *dev, off_t offset,
* Name: sst39vf_ioctl
****************************************************************************/
static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
static int sst39vf_ioctl(FAR struct mtd_dev_s *dev,
int cmd, unsigned long arg)
{
FAR struct sst39vf_dev_s *priv = (FAR struct sst39vf_dev_s *)dev;
int ret = -ENOTTY;
@@ -739,8 +726,8 @@ static int sst39vf_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)arg;
if (geo)
{
/* Populate the geometry structure with information need to know
* the capacity and how to access the device.
/* Populate the geometry structure with information need to
* know the capacity and how to access the device.
*/
geo->blocksize = priv->chip->sectorsize;
drivers/net/enc28j60.c
+38 -35
View File
@@ -130,7 +130,7 @@
#define ENCWORK LPWORK
/* CONFIG_ENC28J60_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_ENC28J60_DUMPPACKET will dump the contents of each packet. */
#ifdef CONFIG_ENC28J60_DUMPPACKET
# define enc_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
@@ -146,7 +146,7 @@
/* Timing *******************************************************************/
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll deley = 1 seconds. CLK_TCK is the number of ticks per second */
#define ENC_WDDELAY (1*CLK_TCK)
@@ -192,7 +192,7 @@
#define enc_bfsgreg(priv,ctrlreg,setbits) \
enc_wrgreg2(priv, ENC_BFS | GETADDR(ctrlreg), setbits)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
@@ -404,8 +404,8 @@ static inline void enc_configspi(FAR struct spi_dev_s *spi)
static void enc_lock(FAR struct enc_driver_s *priv)
{
/* Lock the SPI bus in case there are multiple devices competing for the SPI
* bus.
/* Lock the SPI bus in case there are multiple devices competing for the
* SPI bus.
*/
SPI_LOCK(priv->spi, true);
@@ -475,7 +475,7 @@ static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd)
* 16-clocks: 8 to clock out the cmd + 8 to clock in the data.
*/
SPI_SEND(priv->spi, cmd); /* Clock out the command */
SPI_SEND(priv->spi, cmd); /* Clock out the command */
rddata = SPI_SEND(priv->spi, 0); /* Clock in the data */
/* De-select ENC28J60 chip */
@@ -988,7 +988,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
/* "To read from a PHY register:
*
* 1. Write the address of the PHY register to read from into the MIREGADR
* 1. Write the address of the PHY register to read from into MIREGADR
* register.
*/
@@ -1059,8 +1059,8 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
enc_wrbreg(priv, ENC_MIWRL, phydata);
/* 3. Write the upper 8 bits of data to write into the MIWRH register.
* Writing to this register automatically begins the MIIM transaction,
/* 3. Write the upper 8 bits of data to write into MIWRH register.
* Writing to this register automatically begins MIIM transaction,
* so it must be written to after MIWRL. The MISTAT.BUSY bit becomes
* set.
*/
@@ -1068,7 +1068,7 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
enc_wrbreg(priv, ENC_MIWRH, phydata >> 8);
/* The PHY register will be written after the MIIM operation completes,
* which takes 10.24 µs. When the write operation has completed, the BUSY
* which takes 10.24 µs. When the write operation has completed, BUSY
* bit will clear itself.
*
* The host controller should not start any MIISCAN or MIIRD operations
@@ -1232,8 +1232,8 @@ static int enc_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return OK;
@@ -1306,7 +1306,7 @@ static void enc_txif(FAR struct enc_driver_s *priv)
* Name: enc_txerif
*
* Description:
* An TXERIF interrupt was received indicating that a TX abort has occurred.
* An TXERIF interrupt was received indicating that TX abort has occurred.
*
* Input Parameters:
* priv - Reference to the driver state structure
@@ -1349,8 +1349,8 @@ static void enc_txerif(FAR struct enc_driver_s *priv)
* Name: enc_rxerif
*
* Description:
* An RXERIF interrupt was received indicating that the last TX packet(s) is
* done
* An RXERIF interrupt was received indicating that the last TX packet(s)
* is done
*
* Input Parameters:
* priv - Reference to the driver state structure
@@ -1637,11 +1637,11 @@ static void enc_irqworker(FAR void *arg)
/* Disable further interrupts by clearing the global interrupt enable bit.
* "After an interrupt occurs, the host controller should clear the global
* enable bit for the interrupt pin before servicing the interrupt. Clearing
* the enable bit will cause the interrupt pin to return to the non-asserted
* state (high). Doing so will prevent the host controller from missing a
* falling edge should another interrupt occur while the immediate interrupt
* is being serviced."
* enable bit for the interrupt pin before servicing the interrupt.
* Clearing the enable bit will cause the interrupt pin to return to the
* non-asserted state (high). Doing so will prevent the host controller
* from missing a falling edge should another interrupt occur while the
* immediate interrupt is being serviced."
*/
enc_bfcgreg(priv, ENC_EIE, EIE_INTIE);
@@ -1660,10 +1660,10 @@ static void enc_irqworker(FAR void *arg)
ninfo("EIR: %02x\n", eir);
/* DMAIF: The DMA interrupt indicates that the DMA module has completed
* its memory copy or checksum calculation. Additionally, this interrupt
* will be caused if the host controller cancels a DMA operation by
* manually clearing the DMAST bit. Once set, DMAIF can only be cleared
* by the host controller or by a Reset condition.
* its memory copy or checksum calculation. Additionally, this
* interrupt will be caused if the host controller cancels a DMA
* operation by manually clearing the DMAST bit. Once set, DMAIF can
* only be cleared by the host controller or by a Reset condition.
*/
if ((eir & EIR_DMAIF) != 0) /* DMA interrupt */
@@ -1745,9 +1745,9 @@ static void enc_irqworker(FAR void *arg)
* In Full-Duplex mode, condition 5 is the only one that should cause
* this interrupt. Collisions and other problems related to sharing
* the network are not possible on full-duplex networks. The conditions
* which cause the transmit error interrupt meet the requirements of the
* transmit interrupt. As a result, when this interrupt occurs, TXIF
* will also be simultaneously set.
* which cause the transmit error interrupt meet the requirements of
* the transmit interrupt. As a result, when this interrupt occurs,
* TXIF will also be simultaneously set.
*/
if ((eir & EIR_TXERIF) != 0) /* Transmit Error Interrupts */
@@ -1761,12 +1761,13 @@ static void enc_irqworker(FAR void *arg)
* buffer and to provide a notification means for the arrival of new
* packets. When the receive buffer has at least one packet in it,
* EIR.PKTIF will be set. In other words, this interrupt flag will be
* set anytime the Ethernet Packet Count register (EPKTCNT) is non-zero.
* set anytime the Ethernet Packet Count register (EPKTCNT) is
* non-zero.
*
* The PKTIF bit can only be cleared by the host controller or by a
* Reset condition. In order to clear PKTIF, the EPKTCNT register must
* be decremented to 0. If the last data packet in the receive buffer is
* processed, EPKTCNT will become zero and the PKTIF bit will
* be decremented to 0. If the last data packet in the receive buffer
* is processed, EPKTCNT will become zero and the PKTIF bit will
* automatically be cleared.
*/
@@ -1959,7 +1960,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...)
* can occur until we restart the Tx timeout watchdog.
*/
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0);
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, priv, 0);
DEBUGASSERT(ret == OK);
UNUSED(ret);
}
@@ -2220,14 +2221,16 @@ static int enc_txavail(struct net_driver_s *dev)
if (priv->ifstate == ENCSTATE_UP)
{
/* Check if the hardware is ready to send another packet. The driver
* starts a transmission process by setting ECON1.TXRTS. When the packet
* is finished transmitting or is aborted due to an error/cancellation,
* the ECON1.TXRTS bit will be cleared.
* starts a transmission process by setting ECON1.TXRTS. When the
* packet is finished transmitting or is aborted due to an error/
* cancellation, the ECON1.TXRTS bit will be cleared.
*/
if ((enc_rdgreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
/* The interface is up and TX is idle; poll the network for new XMIT data */
/* The interface is up and TX is idle;
* poll the network for new XMIT data
*/
devif_poll(&priv->dev, enc_txpoll);
}
drivers/net/encx24j600.c
+48 -42
View File
@@ -90,8 +90,8 @@
* CONFIG_ENCX24J600 - Enabled ENCX24J600 support
* CONFIG_ENCX24J600_SPIMODE - Controls the SPI mode
* CONFIG_ENCX24J600_FREQUENCY - Define to use a different bus frequency
* CONFIG_ENCX24J600_NINTERFACES - Specifies the number of physical ENCX24J600
* devices that will be supported.
* CONFIG_ENCX24J600_NINTERFACES - Specifies the number of physica
* l ENCX24J600 devices that will be supported.
*/
/* The ENCX24J600 spec says that it supports SPI mode 0,0 only: "The
@@ -136,7 +136,7 @@
#define ENCWORK LPWORK
/* CONFIG_ENCX24J600_DUMPPACKET will dump the contents of each packet to the console. */
/* CONFIG_ENCX24J600_DUMPPACKET will dump the contents of each packet. */
#ifdef CONFIG_ENCX24J600_DUMPPACKET
# define enc_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
@@ -152,7 +152,7 @@
/* Timing *******************************************************************/
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds. CLK_TCK is the number of ticks per second */
#define ENC_WDDELAY (1*CLK_TCK)
@@ -181,7 +181,7 @@
#define ENC_NTXDESCR ((PKTMEM_RX_START - PKTMEM_START) / PKTMEM_ALIGNED_BUFSIZE)
/* This is a helper pointer for accessing the contents of the Ethernet header */
/* This is a helper pointer for accessing the contents of Ethernet header */
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
@@ -305,7 +305,8 @@ static void enc_bfs(FAR struct enc_driver_s *priv, uint16_t ctrlreg,
uint16_t bits);
static void enc_bfc(FAR struct enc_driver_s *priv, uint16_t ctrlreg,
uint16_t bits);
static void enc_cmd(FAR struct enc_driver_s *priv, uint8_t cmd, uint16_t arg);
static void enc_cmd(FAR struct enc_driver_s *priv,
uint8_t cmd, uint16_t arg);
#if 0 /* Sometimes useful */
static void enc_rxdump(FAR struct enc_driver_s *priv);
@@ -395,8 +396,8 @@ static int enc_reset(FAR struct enc_driver_s *priv);
static void enc_lock(FAR struct enc_driver_s *priv)
{
/* Lock the SPI bus in case there are multiple devices competing for the SPI
* bus.
/* Lock the SPI bus in case there are multiple devices competing for the
* SPI bus.
*/
SPI_LOCK(priv->spi, true);
@@ -921,7 +922,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
uint16_t data = 0;
/* "To read from a PHY register:
* 1. Write the address of the PHY register to read from into the MIREGADR
* 1. Write the address of the PHY register to read from into MIREGADR
* register (Register 3-1). Make sure to also set reserved bit 8 of
* this register.
*/
@@ -937,7 +938,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
/* 3. Wait 25.6 μs. Poll the BUSY (MISTAT<0>) bit to be certain that the
* operation is complete. While busy, the host controller should not
* start any MIISCAN operations or write to the MIWR register. When the
* start any MIISCAN operations or write to the MIWR register. When
* MAC has obtained the register contents, the BUSY bit will clear
* itself.
*/
@@ -982,14 +983,14 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
{
/* "To write to a PHY register:
*
* 1. Write the address of the PHY register to write to into the MIREGADR
* 1. Write the address of the PHY register to write to into MIREGADR
* register. Make sure to also set reserved bit 8 of this register.
*/
enc_wrreg(priv, ENC_MIREGADR, 0x0100 | phyaddr);
/* 2. Write the 16 bits of data into the MIWR register. The low byte must
* be written first, followed by the high byte.
/* 2. Write the 16 bits of data into the MIWR register. The low byte
* must be written first, followed by the high byte.
*/
enc_wrreg(priv, ENC_MIWR, phydata);
@@ -1206,8 +1207,8 @@ static int enc_txpoll(struct net_driver_s *dev)
}
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return ret;
@@ -1385,8 +1386,8 @@ static struct enc_descr_s *enc_rxgetdescr(FAR struct enc_driver_s *priv)
* Name: enc_rxrmpkt
*
* Description:
* Remove packet from the RX queue and free the block of memory in the enc's
* SRAM.
* Remove packet from the RX queue and free the block of memory in the
* enc's SRAM.
*
* Input Parameters:
* priv - Reference to the driver state structure
@@ -1482,7 +1483,7 @@ static void enc_rxdispatch(FAR struct enc_driver_s *priv)
enc_rxldpkt(priv, descr);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
/* When packet sockets are enabled, feed the frame to the packet tap */
pkt_input(&priv->dev);
#endif
@@ -1656,7 +1657,7 @@ static void enc_pktif(FAR struct enc_driver_s *priv)
{
curpkt = priv->nextpkt;
/* Set the rx data pointer to the start of the received packet (ERXRDPT) */
/* Set the rx data pointer to the start of received packet (ERXRDPT) */
enc_cmd(priv, ENC_WRXRDPT, curpkt);
@@ -1835,11 +1836,12 @@ static void enc_irqworker(FAR void *arg)
/* A good practice is for the host controller to clear the Global Interrupt
* Enable bit, INTIE (EIE<15>), immediately after an interrupt event. This
* causes the interrupt pin to return to the non-asserted (high) state. Once
* the interrupt has been serviced, the INTIE bit is set again to re-enable
* interrupts. If a new interrupt occurs while servicing another, the act of
* resetting the global enable bit will cause a new falling edge to occur on
* the interrupt pin and ensure that the host does not miss any events
* causes the interrupt pin to return to the non-asserted (high) state.
* Once the interrupt has been serviced, the INTIE bit is set again to
* re-enable interrupts. If a new interrupt occurs while servicing another,
* the act of resetting the global enable bit will cause a new falling edge
* to occur on the interrupt pin and ensure that the host does not miss any
* events
*/
enc_bfc(priv, ENC_EIE, EIE_INTIE);
@@ -1893,13 +1895,13 @@ static void enc_irqworker(FAR void *arg)
}
/* The receive abort interrupt occurs when the reception of a frame has
* been aborted. A frame being received is aborted when the Head Pointer
* attempts to overrun the Tail Pointer, or when the packet counter has
* reached FFh. In either case, the receive buffer is full and cannot
* fit the incoming frame, so the packet has been dropped. This
* interrupt does not occur when packets are dropped due to the receive
* filters rejecting a packet. The interrupt should be cleared by
* software once it has been serviced.
* been aborted. A frame being received is aborted when the Head
* Pointer attempts to overrun the Tail Pointer, or when the packet
* counter has reached FFh. In either case, the receive buffer is full
* and cannot fit the incoming frame, so the packet has been dropped.
* This interrupt does not occur when packets are dropped due to the
* receive filters rejecting a packet. The interrupt should be cleared
* by software once it has been serviced.
*
* To enable the receive abort interrupt, set RXABTIE (EIE<1>).
* The corresponding interrupt flag is RXABTIF (EIR<1>).
@@ -1929,8 +1931,9 @@ static void enc_irqworker(FAR void *arg)
{
enc_pktif(priv); /* Handle packet receipt */
/* No clearing necessary, after PKTCNT == 0 the bit is automatically
* cleared. This means we will loop until all packets are processed.
/* No clearing necessary, after PKTCNT == 0 the bit is cleared
* automatically. This means we will loop until all packets are
* processed.
*/
}
@@ -2111,7 +2114,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...)
* can occur until we restart the Tx timeout watchdog.
*/
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0);
ret = work_queue(ENCWORK, &priv->towork, enc_toworker, priv, 0);
UNUSED(ret);
DEBUGASSERT(ret == OK);
}
@@ -2383,7 +2386,9 @@ static int enc_txavail(struct net_driver_s *dev)
if ((enc_rdreg(priv, ENC_ECON1) & ECON1_TXRTS) == 0)
{
/* The interface is up and TX is idle; poll the network for new XMIT data */
/* The interface is up and TX is idle;
* poll the network for new XMIT data
*/
devif_poll(&priv->dev, enc_txpoll);
}
@@ -2654,7 +2659,7 @@ static void enc_resetbuffers(FAR struct enc_driver_s *priv)
priv->nextpkt = PKTMEM_RX_START;
enc_wrreg(priv, ENC_ERXST, PKTMEM_RX_START);
/* Program the Tail Pointer, ERXTAIL, to the last even address of the buffer */
/* Program the Tail Pointer, ERXTAIL, to the last even address of buffer */
enc_wrreg(priv, ENC_ERXTAIL, PKTMEM_RX_END - 2);
@@ -2663,7 +2668,7 @@ static void enc_resetbuffers(FAR struct enc_driver_s *priv)
sq_init(&priv->txqueue);
sq_init(&priv->rxqueue);
/* For transmission we preinitialize the descriptors to aligned NET_BUFFSIZE */
/* For transmission we preinitialize the descriptors */
for (i = 0; i < ENC_NTXDESCR; i++)
{
@@ -2736,8 +2741,8 @@ static int enc_reset(FAR struct enc_driver_s *priv)
return -ENODEV;
}
/* Wait at least 256 μs for the PHY registers and PHY status bits to become
* available.
/* Wait at least 256 μs for the PHY registers and PHY status bits to
* become available.
*/
up_udelay(256);
@@ -2747,9 +2752,10 @@ static int enc_reset(FAR struct enc_driver_s *priv)
enc_resetbuffers(priv);
#if 0
/* When restarting auto-negotiation, the ESTAT_PHYLINK gets set but the link
* seems not to be ready. Because auto-negotiation is enabled by default
* (but with different PHANA_* settings) I did not investigate that further.
/* When restarting auto-negotiation, the ESTAT_PHYLINK gets set but the
* link seems not to be ready. Because auto-negotiation is enabled by
* default (but with different PHANA_* settings) I did not investigate
* that further.
*/
/* "Typically, when using auto-negotiation, users should write 0x05e1 to
drivers/power/activity_governor.c
+20 -19
View File
@@ -77,8 +77,8 @@ struct pm_domain_state_s
{
/* recommended - The recommended state based on the governor policy
* mndex - The index to the next slot in the memory[] array to use.
* mcnt - A tiny counter used only at start up. The actual
* algorithm cannot be applied until CONFIG_PM_GOVERNOR_MEMORY
* mcnt - A tiny counter used only at start up. The actual algorithm
* cannot be applied until CONFIG_PM_GOVERNOR_MEMORY
* samples have been collected.
*/
@@ -245,18 +245,18 @@ static void governor_activity(int domain, int count)
DEBUGASSERT(domain >= 0 && domain < CONFIG_PM_NDOMAINS);
pdomstate = &g_pm_activity_governor.domain_states[domain];
/* Just increment the activity count in the current time slice. The priority
* is simply the number of counts that are added.
/* Just increment the activity count in the current time slice. The
* priority is simply the number of counts that are added.
*/
if (count > 0)
{
/* Add the activity count to the accumulated counts in a critical section. */
/* Add the activity count to the accumulated counts. */
flags = enter_critical_section();
accum = (uint32_t)pdomstate->accum + count;
/* Make sure that we do not overflow the underlying uint16_t representation */
/* Make sure that we do not overflow the underlying representation */
if (accum > INT16_MAX)
{
@@ -270,9 +270,9 @@ static void governor_activity(int domain, int count)
/* Check the elapsed time. In periods of low activity, time slicing is
* controlled by IDLE loop polling; in periods of higher activity, time
* slicing is controlled by driver activity. In either case, the
* duration of the time slice is only approximate; during times of heavy
* activity, time slices may be become longer and the activity level may
* be over-estimated.
* duration of the time slice is only approximate; during times of
* heavy activity, time slices may be become longer and the activity
* level may be over-estimated.
*/
now = clock_systimer();
@@ -327,7 +327,7 @@ static void governor_update(int domain, int16_t accum)
int index;
#if CONFIG_PM_GOVERNOR_MEMORY > 1
int32_t denom;
int i;
int i = 0;
int j;
#endif
@@ -349,9 +349,9 @@ static void governor_update(int domain, int16_t accum)
return;
}
/* The averaging algorithm is simply: Y = (An*X + SUM(Ai*Yi))/SUM(Aj), where
* i = 1..n-1 and j= 1..n, n is the length of the "memory", Ai is the
* weight applied to each value, and X is the current activity.
/* The averaging algorithm is simply: Y = (An*X + SUM(Ai*Yi))/SUM(Aj),
* where i = 1..n-1 and j= 1..n, n is the length of the "memory", Ai is
* the weight applied to each value, and X is the current activity.
*
* CONFIG_PM_GOVERNOR_MEMORY:
* provides the memory for the algorithm. Default: 2
@@ -365,11 +365,11 @@ static void governor_update(int domain, int16_t accum)
denom = CONFIG_PM_GOVERNOR_COEFN;
/* Then calculate Y += SUM(Ai*Yi), i = 1..n-1. The oldest sample will
* reside at the domain's mndx (and this is the value that we will overwrite
* with the new value).
* reside at the domain's mndx (and this is the value that we will
* overwrite with the new value).
*/
for (i = 0, j = pdomstate->mndx; i < CONFIG_PM_GOVERNOR_MEMORY - 1; i++, j++)
for (j = pdomstate->mndx; i < CONFIG_PM_GOVERNOR_MEMORY - 1; i++, j++)
{
if (j >= CONFIG_PM_GOVERNOR_MEMORY - 1)
{
@@ -435,8 +435,8 @@ static void governor_update(int domain, int16_t accum)
{
unsigned int nextstate;
/* Get the next state and the table index for the next state (which will
* be the current state)
/* Get the next state and the table index for the next state (which
* will be the current state)
*/
index = state;
@@ -605,7 +605,8 @@ static void governor_timer(int domain)
delay = 1;
}
if (!WDOG_ISACTIVE(pdomstate->wdog) || abs(delay - left) > PM_TIMER_GAP)
if (!WDOG_ISACTIVE(pdomstate->wdog) ||
abs(delay - left) > PM_TIMER_GAP)
{
wd_start(pdomstate->wdog, delay, governor_timer_cb, 0);
}
drivers/serial/serial.c
+1 -1
View File
@@ -1359,7 +1359,7 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
#endif
#if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP)
/* Make the given terminal the controlling terminal of the calling process */
/* Make the controlling terminal of the calling process */
case TIOCSCTTY:
{
drivers/usbhost/usbhost_max3421e.c
+19 -19
View File
@@ -1873,7 +1873,7 @@ static ssize_t max3421e_out_transfer(FAR struct max3421e_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
max3421e_lock(priv);
ret = max3421e_out_setup(priv, chan);
@@ -1921,7 +1921,7 @@ static ssize_t max3421e_out_transfer(FAR struct max3421e_usbhost_s *priv,
}
else
{
/* Successfully transferred. Update the buffer pointer and length */
/* Successfully transferred. Update the buffer pointer/length */
buffer += xfrlen;
buflen -= xfrlen;
@@ -1953,7 +1953,7 @@ static void max3421e_out_next(FAR struct max3421e_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)priv->result;
if (priv->xfrd < priv->buflen && result == OK)
@@ -2018,7 +2018,7 @@ static int max3421e_out_asynch(FAR struct max3421e_usbhost_s *priv,
{
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
priv->buffer = buffer;
priv->buflen = buflen;
@@ -2699,7 +2699,7 @@ static ssize_t max3421e_in_transfer(FAR struct max3421e_usbhost_s *priv,
return (ssize_t)ret;
}
/* Set up for the transfer based on the direction and the endpoint type */
/* Set up for the transfer based on the direction and the endpoint */
max3421e_lock(priv);
ret = max3421e_in_setup(priv, chan);
@@ -2867,7 +2867,7 @@ static void max3421e_in_next(FAR struct max3421e_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
/* Is the full transfer complete? Did the last chunk transfer OK? */
result = -(int)priv->result;
if (priv->xfrd < priv->buflen && result == OK)
@@ -2933,7 +2933,7 @@ static int max3421e_in_asynch(FAR struct max3421e_usbhost_s *priv,
{
int ret;
/* Set up for the transfer data and callback BEFORE starting the first transfer */
/* Set up for the transfer BEFORE starting the first transfer */
priv->buffer = buffer;
priv->buflen = buflen;
@@ -3134,7 +3134,7 @@ static void max3421e_irqwork(FAR void *arg)
pending = max3421e_int_status(priv);
priv->lower->acknowledge(lower);
/* Break out of the loop when there are no further pending interrupts. */
/* Break out of the loop when there are no pending interrupts. */
if (pending == 0)
{
@@ -3398,7 +3398,7 @@ static int max3421e_wait(FAR struct usbhost_connection_s *conn,
for (; ; )
{
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -3577,7 +3577,7 @@ static int max3421e_enumerate(FAR struct usbhost_connection_s *conn,
DEBUGASSERT(maxconn != NULL && maxconn->priv != NULL);
priv = maxconn->priv;
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -3685,7 +3685,7 @@ static int max3421e_ep0configure(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(drvr != NULL && funcaddr < 128 && maxpacketsize <= 64);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -3746,7 +3746,7 @@ static int max3421e_epalloc(FAR struct usbhost_driver_s *drvr,
hport = epdesc->hport;
DEBUGASSERT(hport != NULL);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -3816,7 +3816,7 @@ static int max3421e_epfree(FAR struct usbhost_driver_s *drvr,
DEBUGASSERT(priv);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret >= 0)
@@ -4067,7 +4067,7 @@ static int max3421e_ctrlin(FAR struct usbhost_driver_s *drvr,
buflen = max3421e_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -4132,7 +4132,7 @@ static int max3421e_ctrlin(FAR struct usbhost_driver_s *drvr,
while (elapsed < MAX3421E_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
max3421e_give_exclsem(priv);
return -ETIMEDOUT;
@@ -4167,7 +4167,7 @@ static int max3421e_ctrlout(FAR struct usbhost_driver_s *drvr,
buflen = max3421e_getle16(req->len);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -4234,7 +4234,7 @@ static int max3421e_ctrlout(FAR struct usbhost_driver_s *drvr,
while (elapsed < MAX3421E_DATANAK_DELAY);
}
/* All failures exit here after all retries and timeouts have been exhausted */
/* All failures exit here after all retries and timeouts are exhausted */
max3421e_give_exclsem(priv);
return -ETIMEDOUT;
@@ -4295,7 +4295,7 @@ static ssize_t max3421e_transfer(FAR struct usbhost_driver_s *drvr,
usbhost_vtrace2(MAX3421E_VTRACE2_TRANSFER, (unsigned int)ep, buflen);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
@@ -4371,7 +4371,7 @@ static int max3421e_asynch(FAR struct usbhost_driver_s *drvr,
usbhost_vtrace2(MAX3421E_VTRACE2_ASYNCH, (unsigned int)ep, buflen);
/* We must have exclusive access to the USB host hardware and state structures */
/* We must have exclusive access to the USB host hardware and structures */
ret = max3421e_take_exclsem(priv);
if (ret < 0)
drivers/wireless/spirit/lib/spirit_spi.c
+2 -2
View File
@@ -617,7 +617,7 @@ int spirit_update_status(FAR struct spirit_library_s *spirit)
return spirit_reg_read(spirit, MC_STATE1_BASE, &regval, 1);
}
/****************************************************************************
/******************************************************************************
* Name: spirit_waitstatus
*
* Description:
@@ -635,7 +635,7 @@ int spirit_update_status(FAR struct spirit_library_s *spirit)
* Assumptions:
* We have exclusive access to the driver state and to the spirit library.
*
****************************************************************************/
******************************************************************************/
int spirit_waitstatus(FAR struct spirit_library_s *spirit,
enum spirit_state_e state, unsigned int msec)