From b73e89a6740396220c43ead28898b051c9a62b05 Mon Sep 17 00:00:00 2001 From: Sergey Nikitenko Date: Sat, 6 Mar 2021 17:21:06 +0300 Subject: [PATCH] stm32l4 RCC multi-bit field fixes --- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 13 ++++++++++--- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 6 ++++++ arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 8 +++++++- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 8 ++++++++ 4 files changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 9790370bdc1..2950e7ab272 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -117,7 +117,7 @@ static inline void rcc_enableahb1(void) { uint32_t regval; - /* Set the appropriate bits in the AHB1ENR register to enabled the + /* Set the appropriate bits in the AHB1ENR register to enable the * selected AHB1 peripherals. */ @@ -162,7 +162,7 @@ static inline void rcc_enableahb2(void) { uint32_t regval; - /* Set the appropriate bits in the AHB2ENR register to enable the + /* Set the appropriate bits in the AHB2ENR register to enabled the * selected AHB2 peripherals. */ @@ -519,16 +519,19 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ + regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C2 /* Select HSI16 as I2C2 clock source. */ + regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C3 /* Select HSI16 as I2C3 clock source. */ + regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif #endif /* STM32L4_I2C_USE_HSI16 */ @@ -539,12 +542,14 @@ static inline void rcc_enableccip(void) * warning messages. */ + regval &= ~RCC_CCIPR_CLK48SEL_MASK; regval |= STM32L4_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) /* Select SYSCLK as ADC clock source */ + regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif @@ -570,7 +575,8 @@ static inline void rcc_enableccip(void) /* Select HSI16 as I2C4 clock source. */ - regval |= RCC_CCIPR_I2C4SEL_HSI; + regval &= ~RCC_CCIPR2_I2C4SEL_MASK; + regval |= RCC_CCIPR2_I2C4SEL_HSI; putreg32(regval, STM32L4_RCC_CCIPR2); #endif @@ -637,6 +643,7 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ regval = getreg32(STM32L4_RCC_CR); + regval &= ~RCC_CR_MSIRANGE_MASK; regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ putreg32(regval, STM32L4_RCC_CR); diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 2c9b4de3f4c..4881f2b1dff 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -530,16 +530,19 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ + regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C2 /* Select HSI16 as I2C2 clock source. */ + regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C3 /* Select HSI16 as I2C3 clock source. */ + regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif #endif /* STM32L4_I2C_USE_HSI16 */ @@ -550,12 +553,14 @@ static inline void rcc_enableccip(void) * warning messages. */ + regval &= ~RCC_CCIPR_CLK48SEL_MASK; regval |= STM32L4_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) /* Select SYSCLK as ADC clock source */ + regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif @@ -628,6 +633,7 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ regval = getreg32(STM32L4_RCC_CR); + regval &= ~RCC_CR_MSIRANGE_MASK; regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ putreg32(regval, STM32L4_RCC_CR); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 57f0d310b6e..66b8cd6f643 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -593,16 +593,19 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ + regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C2 /* Select HSI16 as I2C2 clock source. */ + regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C3 /* Select HSI16 as I2C3 clock source. */ + regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif #endif /* STM32L4_I2C_USE_HSI16 */ @@ -613,12 +616,14 @@ static inline void rcc_enableccip(void) * warning messages. */ + regval &= ~RCC_CCIPR_CLK48SEL_MASK; regval |= STM32L4_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) /* Select SYSCLK as ADC clock source */ + regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif @@ -638,7 +643,8 @@ static inline void rcc_enableccip(void) /* Select HSI16 as I2C4 clock source. */ - regval |= RCC_CCIPR_I2C4SEL_HSI; + regval &= ~RCC_CCIPR2_I2C4SEL_MASK; + regval |= RCC_CCIPR2_I2C4SEL_HSI; putreg32(regval, STM32L4_RCC_CCIPR2); #endif diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 11b6e7d0838..433f63eb048 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -575,16 +575,19 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ + regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C2 /* Select HSI16 as I2C2 clock source. */ + regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif #ifdef CONFIG_STM32L4_I2C3 /* Select HSI16 as I2C3 clock source. */ + regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif #endif /* STM32L4_I2C_USE_HSI16 */ @@ -595,12 +598,14 @@ static inline void rcc_enableccip(void) * warning messages. */ + regval &= ~RCC_CCIPR_CLK48SEL_MASK; regval |= STM32L4_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) /* Select SYSCLK as ADC clock source */ + regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif @@ -614,6 +619,7 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_I2C4 /* Select HSI16 as I2C4 clock source. */ + regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; #endif #endif @@ -621,6 +627,7 @@ static inline void rcc_enableccip(void) #ifdef CONFIG_STM32L4_DFSDM1 /* Select SAI1 as DFSDM audio clock source. */ + regval &= ~RCC_CCIPR2_ADFSDMSEL_MASK; regval |= RCC_CCIPR2_ADFSDMSEL_SAI1; /* Select SYSCLK as DFSDM kernel clock source. */ @@ -692,6 +699,7 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ regval = getreg32(STM32L4_RCC_CR); + regval &= ~RCC_CR_MSIRANGE_MASK; regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ putreg32(regval, STM32L4_RCC_CR);