diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h index e3aba44dcd2..bd61476e89d 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h @@ -606,20 +606,20 @@ #define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) #define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) #define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) -#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) #define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9) diff --git a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h index 9c43d1bdcb0..7f74cd821a1 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h @@ -607,19 +607,19 @@ #define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) #define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) #define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_13) #define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h index ad33ee9587e..0db1e919630 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h @@ -606,20 +606,20 @@ #define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) #define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) #define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) -#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) #define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_scu.h b/arch/arm/src/lpc43xx/chip/lpc43_scu.h index a63fc35bde7..0c0dea3cb49 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_scu.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_scu.h @@ -117,6 +117,10 @@ #define LPC43_SCU_EMCDELAYCLK_OFFSET 0x0d00 +/* SD/MMC delay register */ + +#define LPC43_SDMMC_DELAY_OFFSET 0x0d80 + /* Pin interrupt select registers */ #define PINTSEL0 0 @@ -130,53 +134,57 @@ /* Pin Groups */ -#define LPC43_SCU_SFSP(p,n) (LPC43_SCU_BASE+LPC43_SCU_SFSP_OFFSET(p,n)) -#define LPC43_SCU_SFSP0(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP0_OFFSET(n)) -#define LPC43_SCU_SFSP1(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP1_OFFSET(n)) -#define LPC43_SCU_SFSP2(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP2_OFFSET(n)) -#define LPC43_SCU_SFSP3(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP3_OFFSET(n)) -#define LPC43_SCU_SFSP4(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP4_OFFSET(n)) -#define LPC43_SCU_SFSP5(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP5_OFFSET(n)) -#define LPC43_SCU_SFSP6(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP6_OFFSET(n)) -#define LPC43_SCU_SFSP7(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP7_OFFSET(n)) -#define LPC43_SCU_SFSP8(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP8_OFFSET(n)) -#define LPC43_SCU_SFSP9(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP9_OFFSET(n)) -#define LPC43_SCU_SFSPA(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPA_OFFSET(n)) -#define LPC43_SCU_SFSPB(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPB_OFFSET(n)) -#define LPC43_SCU_SFSPC(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPC_OFFSET(n)) -#define LPC43_SCU_SFSPD(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPD_OFFSET(n)) -#define LPC43_SCU_SFSPE(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPE_OFFSET(n)) -#define LPC43_SCU_SFSPF(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPF_OFFSET(n)) +#define LPC43_SCU_SFSP(p,n) (LPC43_SCU_BASE + LPC43_SCU_SFSP_OFFSET(p,n)) +#define LPC43_SCU_SFSP0(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP0_OFFSET(n)) +#define LPC43_SCU_SFSP1(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP1_OFFSET(n)) +#define LPC43_SCU_SFSP2(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP2_OFFSET(n)) +#define LPC43_SCU_SFSP3(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP3_OFFSET(n)) +#define LPC43_SCU_SFSP4(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP4_OFFSET(n)) +#define LPC43_SCU_SFSP5(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP5_OFFSET(n)) +#define LPC43_SCU_SFSP6(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP6_OFFSET(n)) +#define LPC43_SCU_SFSP7(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP7_OFFSET(n)) +#define LPC43_SCU_SFSP8(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP8_OFFSET(n)) +#define LPC43_SCU_SFSP9(n) (LPC43_SCU_BASE + LPC43_SCU_SFSP9_OFFSET(n)) +#define LPC43_SCU_SFSPA(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPA_OFFSET(n)) +#define LPC43_SCU_SFSPB(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPB_OFFSET(n)) +#define LPC43_SCU_SFSPC(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPC_OFFSET(n)) +#define LPC43_SCU_SFSPD(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPD_OFFSET(n)) +#define LPC43_SCU_SFSPE(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPE_OFFSET(n)) +#define LPC43_SCU_SFSPF(n) (LPC43_SCU_BASE + LPC43_SCU_SFSPF_OFFSET(n)) /* CLKn pins */ -#define LPC43_SCU_SFSCLK(n) (LPC43_SCU_BASE+LPC43_SCU_SFSCLK_OFFSET(n)) -#define LPC43_SCU_SFSCLK0 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK0_OFFSET) -#define LPC43_SCU_SFSCLK1 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK1_OFFSET) -#define LPC43_SCU_SFSCLK2 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK2_OFFSET) -#define LPC43_SCU_SFSCLK3 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK3_OFFSET) +#define LPC43_SCU_SFSCLK(n) (LPC43_SCU_BASE + LPC43_SCU_SFSCLK_OFFSET(n)) +#define LPC43_SCU_SFSCLK0 (LPC43_SCU_BASE + LPC43_SCU_SFSCLK0_OFFSET) +#define LPC43_SCU_SFSCLK1 (LPC43_SCU_BASE + LPC43_SCU_SFSCLK1_OFFSET) +#define LPC43_SCU_SFSCLK2 (LPC43_SCU_BASE + LPC43_SCU_SFSCLK2_OFFSET) +#define LPC43_SCU_SFSCLK3 (LPC43_SCU_BASE + LPC43_SCU_SFSCLK3_OFFSET) /* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ -#define LPC43_SCU_SFSUSB (LPC43_SCU_BASE+LPC43_SCU_SFSUSB_OFFSET) -#define LPC43_SCU_SFSI2C0 (LPC43_SCU_BASE+LPC43_SCU_SFSI2C0_OFFSET) +#define LPC43_SCU_SFSUSB (LPC43_SCU_BASE + LPC43_SCU_SFSUSB_OFFSET) +#define LPC43_SCU_SFSI2C0 (LPC43_SCU_BASE + LPC43_SCU_SFSI2C0_OFFSET) /* ADC pin select registers */ -#define LPC43_SCU_ENAIO(n) (LPC43_SCU_BASE+LPC43_SCU_ENAIO_OFFSET(n)) -#define LPC43_SCU_ENAIO0 (LPC43_SCU_BASE+LPC43_SCU_ENAIO0_OFFSET) -#define LPC43_SCU_ENAIO1 (LPC43_SCU_BASE+LPC43_SCU_ENAIO1_OFFSET) -#define LPC43_SCU_ENAIO2 (LPC43_SCU_BASE+LPC43_SCU_ENAIO2_OFFSET) +#define LPC43_SCU_ENAIO(n) (LPC43_SCU_BASE + LPC43_SCU_ENAIO_OFFSET(n)) +#define LPC43_SCU_ENAIO0 (LPC43_SCU_BASE + LPC43_SCU_ENAIO0_OFFSET) +#define LPC43_SCU_ENAIO1 (LPC43_SCU_BASE + LPC43_SCU_ENAIO1_OFFSET) +#define LPC43_SCU_ENAIO2 (LPC43_SCU_BASE + LPC43_SCU_ENAIO2_OFFSET) /* EMC delay register */ -#define LPC43_SCU_EMCDELAYCLK (LPC43_SCU_BASE+LPC43_SCU_EMCDELAYCLK_OFFSET) +#define LPC43_SCU_EMCDELAYCLK (LPC43_SCU_BASE + LPC43_SCU_EMCDELAYCLK_OFFSET) + +/* SD/MMC delay register : Section 17.4.10 of UM10503 */ + +#define LPC43_SDMMC_DELAY (LPC43_SCU_BASE + LPC43_SDMMC_DELAY_OFFSET) /* Pin interrupt select registers */ -#define LPC43_SCU_PINTSEL(n) (LPC43_SCU_BASE+LPC43_SCU_PINTSEL_OFFSET(n)) -#define LPC43_SCU_PINTSEL0 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL0_OFFSET) -#define LPC43_SCU_PINTSEL1 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL1_OFFSET) +#define LPC43_SCU_PINTSEL(n) (LPC43_SCU_BASE + LPC43_SCU_PINTSEL_OFFSET(n)) +#define LPC43_SCU_PINTSEL0 (LPC43_SCU_BASE + LPC43_SCU_PINTSEL0_OFFSET) +#define LPC43_SCU_PINTSEL1 (LPC43_SCU_BASE + LPC43_SCU_PINTSEL1_OFFSET) /* Register Bit Definitions *************************************************************************/ /* Common Pin configuration register bit settings */ @@ -420,6 +428,19 @@ #define SCU_PINTSEL1_PORTSEL7_SHIFT (29) /* Bits 29-31: Pin interrupt 7 */ #define SCU_PINTSEL1_PORTSEL7_MASK (7 << SCU_PINTSEL1_PORTSEL7_SHIFT) +/* SD/MMC delay register : Section 17.4.10 of UM10503 */ + +#define SCU_SDMMC_SAMPLE_DELAY_SHIFT (0) /* Bits 0-3: Sample delay */ +#define SCU_SDMMC_SAMPLE_DELAY_MASK (15 << SCU_SDMMC_SAMPLE_DELAY_SHIFT) +# define SCU_SDMMC_SAMPLE_DELAY(n) ((uint32_t)(n) << SCU_SDMMC_SAMPLE_DELAY_SHIFT) +#define SCU_SDMMC_DRV_DELAY_SHIFT (8) /* Bit 8-11: DRV delay */ +#define SCU_SDMMC_DRV_DELAY_MASK (15 << SCU_SDMMC_DRV_DELAY_SHIFT) +# define SCU_SDMMC_DRV_DELAY(n) ((uint32_t)(n) << SCU_SDMMC_DRV_DELAY_SHIFT) + +/* Default values taken from Table 37 of LPC4330 datasheet */ + +#define LPC43_SDMMC_DELAY_DEFAULT (SCU_SDMMC_SAMPLE_DELAY(9) | SCU_SDMMC_DRV_DELAY(6)) + /**************************************************************************************************** * Public Types ****************************************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c index daab422009d..c1bf86c46fd 100644 --- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -120,6 +120,10 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif +#ifndef CONFIG_SDIO_BLOCKSETUP +# error "Driver requires CONFIG_SDIO_BLOCKSETUP to be set" +#endif + /* Timing */ #define SDCARD_CMDTIMEOUT (10000) @@ -308,6 +312,10 @@ static int lpc43_attach(FAR struct sdio_dev_s *dev); static int lpc43_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); +#ifdef CONFIG_SDIO_BLOCKSETUP +static void lpc43_blocksetup(FAR struct sdio_dev_s *dev, + unsigned int blocklen, unsigned int nblocks); +#endif static int lpc43_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t nbytes); static int lpc43_sendsetup(FAR struct sdio_dev_s *dev, @@ -363,6 +371,9 @@ struct lpc43_dev_s g_scard_dev = .clock = lpc43_clock, .attach = lpc43_attach, .sendcmd = lpc43_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = lpc43_blocksetup, +#endif .recvsetup = lpc43_recvsetup, .sendsetup = lpc43_sendsetup, .cancel = lpc43_cancel, @@ -1395,6 +1406,17 @@ static sdio_statset_t lpc43_status(FAR struct sdio_dev_s *dev) { struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + if ((lpc43_getreg(LPC43_SDMMC_CDETECT) & SDMMC_CDETECT_NOTPRESENT) == 0) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_PRESENT; + } +#endif + mcinfo("cdstatus=%02x\n", priv->cdstatus); return priv->cdstatus; @@ -1648,6 +1670,38 @@ static int lpc43_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, return OK; } +/**************************************************************************** + * Name: lpc43_blocksetup + * + * Description: + * Configure block size and the number of blocks for next transfer + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * blocklen - The selected block size. + * nblocklen - The number of blocks to transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_BLOCKSETUP +static void lpc43_blocksetup(FAR struct sdio_dev_s *dev, + unsigned int blocklen, unsigned int nblocks) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + mcinfo("blocklen=%ld, total transfer=%ld (%ld blocks)\n", + blocklen, blocklen*nblocks, nblocks); + + /* Configure block size for next transfer */ + + lpc43_putreg(blocklen, LPC43_SDMMC_BLKSIZ); + lpc43_putreg(blocklen * nblocks, LPC43_SDMMC_BYTCNT); +} +#endif + /**************************************************************************** * Name: lpc43_recvsetup * @@ -1678,7 +1732,6 @@ static int lpc43_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #ifdef CONFIG_LPC43_SDMMC_DMA uint32_t regval; #endif - mcinfo("nbytes=%ld\n", (long) nbytes); DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); @@ -1693,23 +1746,6 @@ static int lpc43_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, priv->dmamode = false; #endif - /* Then set up the SD card data path */ - - if (nbytes < 64) - { - blocksize = nbytes; - bytecnt = nbytes; - } - else - { - blocksize = 64; - bytecnt = nbytes; - DEBUGASSERT((nbytes & 0x3f) == 0); - } - - lpc43_putreg(blocksize, LPC43_SDMMC_BLKSIZ); - lpc43_putreg(bytecnt, LPC43_SDMMC_BYTCNT); - /* Configure the FIFO so that we will receive the RXDR interrupt whenever * there are more than 1 words (at least 8 bytes) in the RX FIFO. */ @@ -2738,6 +2774,10 @@ FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno) regval |= CCU_CLK_CFG_WAKEUP; lpc43_putreg(regval, LPC43_CCU1_M4_SDIO_CFG); + /* Setup the delay register */ + + lpc43_putreg(LPC43_SDMMC_DELAY_DEFAULT, LPC43_SDMMC_DELAY); + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); diff --git a/configs/lpc4330-xplorer/include/board.h b/configs/lpc4330-xplorer/include/board.h index 513adb5ff2f..e70d7739e06 100644 --- a/configs/lpc4330-xplorer/include/board.h +++ b/configs/lpc4330-xplorer/include/board.h @@ -218,6 +218,34 @@ # define BOARD_SPIFI_FREQUENCY (102000000) /* 204MHz / 14 = 14.57MHz */ #endif +/* SD/MMC or SDIO interface ************************************************/ + +#define BOARD_SDMMC_CEIL(a,b) (((a) + (b) - 1) / (b)) + +/* For LPC4330 family there is no predivider for the clock */ + +#define BOARD_SDMMC_FREQUENCY BOARD_MAIN_CLK + +/* Mode-dependent function clock division + * + * NOTE: Clock division is 2*n. For example, value of 0 means divide by + * 2 * 0 = 0 (no division, bypass), value of 1 means divide by 2 * 1 = 2, value + * of 255 means divide by 2 * 255 = 510, and so on. + * + * SD/MMC logic will write the value ((clkdiv + 1) >> 1) as the divisor. So an + * odd value calculated below will be moved up to next higher divider value. So + * the value 3 will cause 2 to be written as the divider value and the effective + * divider will be 4. + * + * NOTE: The SDIO function clock to the interface can be up to 52 MHZ. + * See UM10503 Section 22.2. + */ + +#define BOARD_CLKDIV_INIT BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 400000) +#define BOARD_CLKDIV_MMCXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 20000000) +#define BOARD_CLKDIV_SDWIDEXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) +#define BOARD_CLKDIV_SDXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) + /* UART clocking ***********************************************************/ /* Configure all U[S]ARTs to use the XTAL input frequency */