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Replace all __attribute__((aligned(x)) with aligned_data(x)

Browse Source 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
2021-07-27 18:19:12 +08:00
committed by Gustavo Henrique Nihei
parent 9c3799f130
commit b3f9ffbe72
71 changed files with 188 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/armv6-m/arm_ramvec_initialize.c
+1 -1
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@@ -71,7 +71,7 @@
*/
up_vector_t g_ram_vectors[ARMV6M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
__attribute__ ((section (".ram_vectors"))) aligned_data(RAMVEC_ALIGN);
/****************************************************************************
* Public Functions
arch/arm/src/armv6-m/ram_vectors.h
+1 -1
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@@ -57,7 +57,7 @@
*/
extern up_vector_t g_ram_vectors[ARMV6M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"))) aligned_data(128);
/****************************************************************************
* Public Function Prototypes
arch/arm/src/armv7-m/arm_ramvec_initialize.c
+1 -1
View File
@@ -100,7 +100,7 @@
*/
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
__attribute__ ((section (".ram_vectors"))) aligned_data(RAMVEC_ALIGN);
/****************************************************************************
* Public Functions
arch/arm/src/armv7-m/ram_vectors.h
+1 -1
View File
@@ -62,7 +62,7 @@
*/
extern up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"))) aligned_data(128);
/****************************************************************************
* Public Function Prototypes
arch/arm/src/armv8-m/arm_ramvec_initialize.c
+1 -1
View File
@@ -99,7 +99,7 @@
*/
up_vector_t g_ram_vectors[ARMV8M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
__attribute__ ((section (".ram_vectors"))) aligned_data(RAMVEC_ALIGN);
/****************************************************************************
* Public Functions
arch/arm/src/armv8-m/ram_vectors.h
+1 -1
View File
@@ -62,7 +62,7 @@
*/
extern up_vector_t g_ram_vectors[ARMV8M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (128)));
__attribute__ ((section (".ram_vectors"))) aligned_data(128);
/****************************************************************************
* Public Function Prototypes
arch/arm/src/cxd56xx/cxd56_udmac.c
+1 -1
View File
@@ -114,7 +114,7 @@ static struct dma_channel_s g_dmach[CXD56_DMA_NCHANNELS];
#endif
static struct dma_descriptor_s g_descriptors[CXD56_DMA_NCHANNELS]
__attribute__((aligned(DESC_TABLE_ALIGN)));
aligned_data(DESC_TABLE_ALIGN);
/****************************************************************************
* Public Data
arch/arm/src/cxd56xx/cxd56_usbdev.c
+3 -7
View File
@@ -96,10 +96,6 @@
(PHY_STAGSELECT | PHY_HSFALLCNTRL | PHY_IHSTX(0xc) | PHY_INHSRFRED | \
PHY_INHSIPLUS | PHY_INHSDRVSLEW| PHY_INLFSFBCAP)
#ifndef __aligned
# define __aligned(x) __attribute__((aligned(x)))
#endif
/* Debug ********************************************************************/
/* Trace error codes */
@@ -556,9 +552,9 @@ static struct cxd56_usbdev_s g_usbdev;
/* DMA Descriptors for each endpoints */
static struct cxd56_setup_desc_s __aligned(4) g_ep0setup;
static struct cxd56_data_desc_s __aligned(4) g_ep0in;
static struct cxd56_data_desc_s __aligned(4) g_ep0out;
static struct cxd56_setup_desc_s aligned_data(4) g_ep0setup;
static struct cxd56_data_desc_s aligned_data(4) g_ep0in;
static struct cxd56_data_desc_s aligned_data(4) g_ep0out;
/* Summarizes information about all CXD56 endpoints */
arch/arm/src/efm32/efm32_dma.c
+2 -2
View File
@@ -113,10 +113,10 @@ static struct dma_channel_s g_dmach[EFM32_DMA_NCHANNELS];
#ifdef CONFIG_EFM32_DMA_ALTDSEC
static struct dma_descriptor_s
g_descriptors[DESC_TABLE_SIZE + EFM32_DMA_NCHANNELS]
__attribute__((aligned(DESC_TABLE_ALIGN)));
aligned_data(DESC_TABLE_ALIGN);
#else
static struct dma_descriptor_s g_descriptors[EFM32_DMA_NCHANNELS]
__attribute__((aligned(DESC_TABLE_ALIGN)));
aligned_data(DESC_TABLE_ALIGN);
#endif
/****************************************************************************
arch/arm/src/imx6/imx_enet.c
+2 -2
View File
@@ -306,7 +306,7 @@ static struct imx_driver_s g_enet[CONFIG_IMX_ENET_NETHIFS];
*/
static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -314,7 +314,7 @@ static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
*/
static uint8_t g_buffer_pool[NENET_NBUFFERS * IMX_BUF_SIZE]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/****************************************************************************
* Private Function Prototypes
arch/arm/src/imxrt/imxrt_edma.c
+1 -1
View File
@@ -171,7 +171,7 @@ static sq_queue_t g_tcd_free;
/* This is a pool of pre-allocated TCDs */
static struct imxrt_edmatcd_s g_tcd_pool[CONFIG_IMXRT_EDMA_NTCD]
__attribute__((aligned(EDMA_ALIGN)));
aligned_data(EDMA_ALIGN);
#endif
/****************************************************************************
arch/arm/src/imxrt/imxrt_ehci.c
+5 -5
View File
@@ -582,17 +582,17 @@ static const uint8_t g_ehci_speed[4] =
/* The head of the asynchronous queue */
static struct imxrt_qh_s g_asynchead __attribute__ ((aligned(32)));
static struct imxrt_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct imxrt_qh_s g_intrhead __attribute__ ((aligned(32)));
static struct imxrt_qh_s g_intrhead aligned_data(32);
/* The frame list */
#ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
#else
static uint32_t *g_framelist;
#endif
@@ -606,12 +606,12 @@ static uint32_t *g_framelist;
/* Queue Head (QH) pool */
static struct imxrt_qh_s g_qhpool[CONFIG_IMXRT_EHCI_NQHS]
__attribute__ ((aligned(32)));
aligned_data(32);
/* Queue Element Transfer Descriptor (qTD) pool */
static struct imxrt_qtd_s g_qtdpool[CONFIG_IMXRT_EHCI_NQTDS]
__attribute__ ((aligned(32)));
aligned_data(32);
#else
/* Pools of dynamically data structures. These will all be linked into the
arch/arm/src/imxrt/imxrt_enet.c
+2 -2
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@@ -288,7 +288,7 @@ static struct imxrt_driver_s g_enet[CONFIG_IMXRT_ENET_NETHIFS];
*/
static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -296,7 +296,7 @@ static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
*/
static uint8_t g_buffer_pool[NENET_NBUFFERS * IMXRT_BUF_SIZE]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/****************************************************************************
* Private Function Prototypes
arch/arm/src/imxrt/imxrt_usbdev.c
+2 -2
View File
@@ -503,10 +503,10 @@ static int imxrt_pullup(struct usbdev_s *dev, bool enable);
static struct imxrt_usbdev_s g_usbdev;
static struct imxrt_dqh_s g_qh[IMXRT_NPHYSENDPOINTS]
__attribute__((aligned(2048)));
aligned_data(2048);
static struct imxrt_dtd_s g_td[IMXRT_NPHYSENDPOINTS]
__attribute__((aligned(32)));
aligned_data(32);
static const struct usbdev_epops_s g_epops =
{
arch/arm/src/kinetis/kinetis_edma.c
+1 -1
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@@ -174,7 +174,7 @@ static sq_queue_t g_tcd_free;
/* This is a pool of pre-allocated TCDs */
static struct kinetis_edmatcd_s g_tcd_pool[CONFIG_KINETIS_EDMA_NTCD]
__attribute__((aligned(EDMA_ALIGN)));
aligned_data(EDMA_ALIGN);
#endif
/****************************************************************************
arch/arm/src/kinetis/kinetis_lpserial.c
+5 -5
View File
@@ -379,7 +379,7 @@ static char g_lpuart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE];
static char g_lpuart0txbuffer[CONFIG_LPUART0_TXBUFSIZE];
# ifdef CONFIG_KINETIS_LPUART0_RXDMA
static char g_lpuart0rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
#ifdef CONFIG_KINETIS_LPUART1
@@ -387,7 +387,7 @@ static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
# ifdef CONFIG_KINETIS_LPUART1_RXDMA
static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
#ifdef CONFIG_KINETIS_LPUART2
@@ -395,7 +395,7 @@ static char g_lpuart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE];
static char g_lpuart2txbuffer[CONFIG_LPUART2_TXBUFSIZE];
# ifdef CONFIG_KINETIS_LPUART2_RXDMA
static char g_lpuart2rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
#ifdef CONFIG_KINETIS_LPUART3
@@ -403,7 +403,7 @@ static char g_lpuart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE];
static char g_lpuart3txbuffer[CONFIG_LPUART3_TXBUFSIZE];
# ifdef CONFIG_KINETIS_LPUART3_RXDMA
static char g_lpuart3rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
#ifdef CONFIG_KINETIS_LPUART4
@@ -411,7 +411,7 @@ static char g_lpuart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE];
static char g_lpuart4txbuffer[CONFIG_LPUART4_TXBUFSIZE];
# ifdef CONFIG_KINETIS_LPUART4_RXDMA
static char g_lpuart4rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
arch/arm/src/kinetis/kinetis_serial.c
+6 -6
View File
@@ -409,7 +409,7 @@ static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART0_RXDMA
static char g_uart0rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
@@ -418,7 +418,7 @@ static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART1_RXDMA
static char g_uart1rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
@@ -427,7 +427,7 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART2_RXDMA
static char g_uart2rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
@@ -436,7 +436,7 @@ static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART3_RXDMA
static char g_uart3rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
@@ -445,7 +445,7 @@ static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
@@ -454,7 +454,7 @@ static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART5_RXDMA
static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
#endif
arch/arm/src/kinetis/kinetis_spi.c
+1 -1
View File
@@ -1160,7 +1160,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
int ret;
size_t adjust;
ssize_t nbytes;
static uint8_t rxdummy[4] __attribute__((aligned(4)));
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
FAR struct kinetis_spidev_s *priv = (FAR struct kinetis_spidev_s *)dev;
arch/arm/src/kinetis/kinetis_usbdev.c
+1 -1
View File
@@ -674,7 +674,7 @@ static const struct usbdev_ops_s g_devops =
*/
static volatile struct usbotg_bdtentry_s g_bdt[4*KHCI_NENDPOINTS]
__attribute__ ((aligned(512)));
aligned_data(512);
/****************************************************************************
* Private Private Functions
arch/arm/src/kinetis/kinetis_usbhshost.c
+5 -5
View File
@@ -609,17 +609,17 @@ static const uint8_t g_ehci_speed[4] =
/* The head of the asynchronous queue */
static struct kinetis_qh_s g_asynchead __attribute__ ((aligned(32)));
static struct kinetis_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct kinetis_qh_s g_intrhead __attribute__ ((aligned(32)));
static struct kinetis_qh_s g_intrhead aligned_data(32);
/* The frame list */
#ifdef CONFIG_KINETIS_EHCI_PREALLOCATE
static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
#else
static uint32_t *g_framelist;
#endif
@@ -633,12 +633,12 @@ static uint32_t *g_framelist;
/* Queue Head (QH) pool */
static struct kinetis_qh_s g_qhpool[CONFIG_KINETIS_EHCI_NQHS]
__attribute__ ((aligned(32)));
aligned_data(32);
/* Queue Element Transfer Descriptor (qTD) pool */
static struct kinetis_qtd_s g_qtdpool[CONFIG_KINETIS_EHCI_NQTDS]
__attribute__ ((aligned(32)));
aligned_data(32);
#else
/* Pools of dynamically data structures. These will all be linked into the
arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
+1 -1
View File
@@ -509,7 +509,7 @@ static const struct usbdev_ops_s g_devops =
#ifdef CONFIG_LPC17_40_USBDEV_DMA
static uint32_t
g_udca[LPC17_40_NPHYSENDPOINTS] __attribute__ ((aligned (128)));
g_udca[LPC17_40_NPHYSENDPOINTS] aligned_data(128);
static struct
lpc17_40_dmadesc_s g_usbddesc[CONFIG_LPC17_40_USBDEV_NDMADESCRIPTORS];
#endif
arch/arm/src/lpc31xx/lpc31_ehci.c
+5 -5
View File
@@ -585,17 +585,17 @@ static const uint8_t g_ehci_speed[4] =
/* The head of the asynchronous queue */
static struct lpc31_qh_s g_asynchead __attribute__ ((aligned(32)));
static struct lpc31_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct lpc31_qh_s g_intrhead __attribute__ ((aligned(32)));
static struct lpc31_qh_s g_intrhead aligned_data(32);
/* The frame list */
#ifdef CONFIG_LPC31_EHCI_PREALLOCATE
static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
#else
static uint32_t *g_framelist;
#endif
@@ -609,12 +609,12 @@ static uint32_t *g_framelist;
/* Queue Head (QH) pool */
static struct lpc31_qh_s g_qhpool[CONFIG_LPC31_EHCI_NQHS]
__attribute__ ((aligned(32)));
aligned_data(32);
/* Queue Element Transfer Descriptor (qTD) pool */
static struct lpc31_qtd_s g_qtdpool[CONFIG_LPC31_EHCI_NQTDS]
__attribute__ ((aligned(32)));
aligned_data(32);
#else
/* Pools of dynamically data structures. These will all be linked into the
arch/arm/src/lpc31xx/lpc31_usbdev.c
+2 -2
View File
@@ -450,9 +450,9 @@ static int lpc31_pullup(struct usbdev_s *dev, bool enable);
static struct lpc31_usbdev_s g_usbdev;
static struct
lpc31_dqh_s __attribute__((aligned(2048))) g_qh[LPC31_NPHYSENDPOINTS];
lpc31_dqh_s aligned_data(2048) g_qh[LPC31_NPHYSENDPOINTS];
static struct
lpc31_dtd_s __attribute__((aligned(32))) g_td[LPC31_NPHYSENDPOINTS];
lpc31_dtd_s aligned_data(32) g_td[LPC31_NPHYSENDPOINTS];
static const struct usbdev_epops_s g_epops =
{
arch/arm/src/lpc43xx/lpc43_ehci.c
+5 -5
View File
@@ -575,17 +575,17 @@ static const uint8_t g_ehci_speed[4] =
/* The head of the asynchronous queue */
static struct lpc43_qh_s g_asynchead __attribute__ ((aligned(32)));
static struct lpc43_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct lpc43_qh_s g_intrhead __attribute__ ((aligned(32)));
static struct lpc43_qh_s g_intrhead aligned_data(32);
/* The frame list */
#ifdef CONFIG_LPC43_EHCI_PREALLOCATE
static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
#else
static uint32_t *g_framelist;
#endif
@@ -599,12 +599,12 @@ static uint32_t *g_framelist;
/* Queue Head (QH) pool */
static struct lpc43_qh_s g_qhpool[CONFIG_LPC43_EHCI_NQHS]
__attribute__ ((aligned(32)));
aligned_data(32);
/* Queue Element Transfer Descriptor (qTD) pool */
static struct lpc43_qtd_s g_qtdpool[CONFIG_LPC43_EHCI_NQTDS]
__attribute__ ((aligned(32)));
aligned_data(32);
#else
/* Pools of dynamically data structures. These will all be linked into the
arch/arm/src/lpc43xx/lpc43_usb0dev.c
+2 -2
View File
@@ -452,9 +452,9 @@ static int lpc43_pullup(struct usbdev_s *dev, bool enable);
static struct lpc43_usbdev_s g_usbdev;
static struct
lpc43_dqh_s __attribute__((aligned(2048))) g_qh[LPC43_NPHYSENDPOINTS];
lpc43_dqh_s aligned_data(2048) g_qh[LPC43_NPHYSENDPOINTS];
static struct
lpc43_dtd_s __attribute__((aligned(32))) g_td[LPC43_NPHYSENDPOINTS];
lpc43_dtd_s aligned_data(32) g_td[LPC43_NPHYSENDPOINTS];
static const struct usbdev_epops_s g_epops =
{
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
+7 -7
View File
@@ -521,21 +521,21 @@ static struct usbhost_connection_s g_usbconn =
/* Aligned static memory allocations */
static uint8_t g_hcca[LPC54_HCCA_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
static uint8_t g_tdtail_alloc[LPC54_TD_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
static uint8_t g_edctrl_alloc[LPC54_ED_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
static uint8_t g_edfree_alloc[LPC54_EDFREE_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
static uint8_t g_tdfree_alloc[LPC54_TDFREE_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
static uint8_t g_tbfree_alloc[LPC54_TBFREE_SIZE] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
#if LPC54_IOBUFFERS > 0
static uint8_t g_iobuffers[LPC54_IOBUF_ALLOC] \
__attribute__ ((aligned(LPC54_ALIGN_SIZE)));
aligned_data(LPC54_ALIGN_SIZE);
#endif
/* This is a free list of EDs and TD buffers */
arch/arm/src/rtl8720c/ameba_vectors.c
+1 -1
View File
@@ -64,7 +64,7 @@ extern void exception_common(void);
*/
unsigned _vectors[] __attribute__((section(".vectors"))) \
__attribute__((aligned(0x100))) =
aligned_data(0x100) =
{
/* Initial stack */
arch/arm/src/s32k1xx/s32k1xx_edma.c
+1 -1
View File
@@ -171,7 +171,7 @@ static sq_queue_t g_tcd_free;
/* This is a pool of pre-allocated TCDs */
static struct s32k1xx_edmatcd_s g_tcd_pool[CONFIG_S32K1XX_EDMA_NTCD]
__attribute__((aligned(EDMA_ALIGN)));
aligned_data(EDMA_ALIGN);
#endif
/****************************************************************************
arch/arm/src/s32k1xx/s32k1xx_enet.c
+2 -2
View File
@@ -282,7 +282,7 @@ static struct s32k1xx_driver_s g_enet[CONFIG_S32K1XX_ENET_NETHIFS];
*/
static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
* memory; 16 is added to assure that we can meet the descriptor alignment
@@ -290,7 +290,7 @@ static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
*/
static uint8_t g_buffer_pool[NENET_NBUFFERS * S32K1XX_BUF_SIZE]
__attribute__((aligned(ENET_ALIGN)));
aligned_data(ENET_ALIGN);
/****************************************************************************
* Private Function Prototypes
arch/arm/src/sam34/sam_emac.c
+5 -5
View File
@@ -303,12 +303,12 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
/* TX descriptors list */
static struct emac_txdesc_s g_txdesc[CONFIG_SAM34_EMAC_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* RX descriptors list */
static struct emac_rxdesc_s g_rxdesc[CONFIG_SAM34_EMAC_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* Transmit Buffers
*
@@ -317,13 +317,13 @@ static struct emac_rxdesc_s g_rxdesc[CONFIG_SAM34_EMAC_NRXBUFFERS]
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAM34_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE];
__attribute__((aligned(8)))
static uint8_t g_txbuffer[CONFIG_SAM34_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE]
aligned_data(8);
/* Receive Buffers */
static uint8_t g_rxbuffer[CONFIG_SAM34_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
arch/arm/src/sama5/sam_ehci.c
+5 -5
View File
@@ -454,17 +454,17 @@ static const uint8_t g_ehci_speed[4] =
/* The head of the asynchronous queue */
static struct sam_qh_s g_asynchead __attribute__ ((aligned(32)));
static struct sam_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct sam_qh_s g_intrhead __attribute__ ((aligned(32)));
static struct sam_qh_s g_intrhead aligned_data(32);
/* The frame list */
#ifdef CONFIG_SAMA5_EHCI_PREALLOCATE
static uint32_t g_framelist[FRAME_LIST_SIZE] __attribute__ ((aligned(4096)));
static uint32_t g_framelist[FRAME_LIST_SIZE] aligned_data(4096);
#else
static uint32_t *g_framelist;
#endif
@@ -478,12 +478,12 @@ static uint32_t *g_framelist;
/* Queue Head (QH) pool */
static struct sam_qh_s g_qhpool[CONFIG_SAMA5_EHCI_NQHS]
__attribute__ ((aligned(32)));
aligned_data(32);
/* Queue Element Transfer Descriptor (qTD) pool */
static struct sam_qtd_s g_qtdpool[CONFIG_SAMA5_EHCI_NQTDS]
__attribute__ ((aligned(32)));
aligned_data(32);
#else
/* Pools of dynamically data structures. These will all be linked into the
arch/arm/src/sama5/sam_emaca.c
+5 -5
View File
@@ -334,12 +334,12 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
/* TX descriptors list */
static struct emac_txdesc_s g_txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* RX descriptors list */
static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* Transmit Buffers
*
@@ -348,13 +348,13 @@ static struct emac_rxdesc_s g_rxdesc[CONFIG_SAMA5_EMAC_NRXBUFFERS]
* lsb bits of the address shall be set to 0
*/
static uint8_t g_txbuffer[CONFIG_SAMA5_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE];
__attribute__((aligned(8)))
static uint8_t g_txbuffer[CONFIG_SAMA5_EMAC_NTXBUFFERS * EMAC_TX_UNITSIZE]
aligned_data(8);
/* Receive Buffers */
static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
arch/arm/src/sama5/sam_emacb.c
+8 -8
View File
@@ -546,12 +546,12 @@ static int sam_emac_configure(struct sam_emac_s *priv);
/* EMAC0 TX descriptors list */
static struct emac_txdesc_s g_emac0_txdesc[CONFIG_SAMA5_EMAC0_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC0 RX descriptors list */
static struct emac_rxdesc_s g_emac0_rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC0 Transmit Buffers
*
@@ -562,13 +562,13 @@ static struct emac_rxdesc_s g_emac0_rxdesc[CONFIG_SAMA5_EMAC0_NRXBUFFERS]
static uint8_t
g_emac0_txbuffer[CONFIG_SAMA5_EMAC0_NTXBUFFERS * EMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC0 Receive Buffers */
static uint8_t
g_emac0_rxbuffer[CONFIG_SAMA5_EMAC0_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
@@ -576,12 +576,12 @@ __attribute__((aligned(8)));
/* EMAC1 TX descriptors list */
static struct emac_txdesc_s g_emac1_txdesc[CONFIG_SAMA5_EMAC1_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC1 RX descriptors list */
static struct emac_rxdesc_s g_emac1_rxdesc[CONFIG_SAMA5_EMAC1_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC1 Transmit Buffers
*
@@ -592,13 +592,13 @@ static struct emac_rxdesc_s g_emac1_rxdesc[CONFIG_SAMA5_EMAC1_NRXBUFFERS]
static uint8_t
g_emac1_txbuffer[CONFIG_SAMA5_EMAC1_NTXBUFFERS * EMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
/* EMAC1 Receive Buffers */
static uint8_t
g_emac1_rxbuffer[CONFIG_SAMA5_EMAC1_NRXBUFFERS * EMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
#endif
arch/arm/src/sama5/sam_gmac.c
+4 -4
View File
@@ -260,12 +260,12 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
/* TX descriptors list */
static struct gmac_txdesc_s g_txdesc[CONFIG_SAMA5_GMAC_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* RX descriptors list */
static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMA5_GMAC_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* Transmit Buffers
*
@@ -275,12 +275,12 @@ static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMA5_GMAC_NRXBUFFERS]
*/
static uint8_t g_txbuffer[CONFIG_SAMA5_GMAC_NTXBUFFERS * GMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
/* Receive Buffers */
static uint8_t g_rxbuffer[CONFIG_SAMA5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
/****************************************************************************
arch/arm/src/sama5/sam_ohci.c
+4 -4
View File
@@ -487,7 +487,7 @@ static struct sam_list_s *g_tbfree; /* List of unused transfer buffers */
/* This must be aligned to a 256-byte boundary */
static struct ohci_hcca_s g_hcca
__attribute__ ((aligned (256)));
aligned_data(256);
/* Pools of free descriptors and buffers. These will all be linked
* into the free lists declared above. These must be aligned to 8-byte
@@ -495,11 +495,11 @@ static struct ohci_hcca_s g_hcca
*/
static struct sam_ed_s g_edalloc[SAMA5_OHCI_NEDS]
__attribute__ ((aligned (SAMA5_DMA_ALIGN)));
aligned_data(SAMA5_DMA_ALIGN);
static struct sam_gtd_s g_tdalloc[SAMA5_OHCI_NTDS]
__attribute__ ((aligned (SAMA5_DMA_ALIGN)));
aligned_data(SAMA5_DMA_ALIGN);
static uint8_t g_bufalloc[SAM_BUFALLOC]
__attribute__ ((aligned (SAMA5_DMA_ALIGN)));
aligned_data(SAMA5_DMA_ALIGN);
/****************************************************************************
* Private Functions
arch/arm/src/sama5/sam_udphs.c
+1 -1
View File
@@ -563,7 +563,7 @@ static const struct usb_epdesc_s g_ep0desc =
/* This is a properly aligned pool of preallocated DMA transfer descriptors */
static struct sam_dtd_s g_dtdpool[CONFIG_SAMA5_UDPHS_NDTDS]
__attribute__ ((aligned(16)));
aligned_data(16);
#endif
#endif
arch/arm/src/samd5e5/sam_gmac.c
+4 -4
View File
@@ -257,12 +257,12 @@ static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
/* TX descriptors list */
static struct gmac_txdesc_s g_txdesc[CONFIG_SAMD5E5_GMAC_NTXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* RX descriptors list */
static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMD5E5_GMAC_NRXBUFFERS]
__attribute__((aligned(8)));
aligned_data(8);
/* Transmit Buffers
*
@@ -272,12 +272,12 @@ static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMD5E5_GMAC_NRXBUFFERS]
*/
static uint8_t g_txbuffer[CONFIG_SAMD5E5_GMAC_NTXBUFFERS * GMAC_TX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
/* Receive Buffers */
static uint8_t g_rxbuffer[CONFIG_SAMD5E5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE]
__attribute__((aligned(8)));
aligned_data(8);
#endif
/****************************************************************************
arch/arm/src/samd5e5/sam_usb.c
+6 -6
View File
@@ -393,11 +393,11 @@ struct sam_usbdev_s
/* The endpoint list */
__attribute__((__aligned__(4))) struct sam_ep_s eplist[SAM_USB_NENDPOINTS];
aligned_data(4) struct sam_ep_s eplist[SAM_USB_NENDPOINTS];
/* Endpoint descriptors 2 banks for each endpoint */
__attribute__((__aligned__(4)))
aligned_data(4)
struct usbdev_epdesc_s ep_descriptors[SAM_USB_NENDPOINTS *
SAM_USB_NBANKS()];
@@ -409,7 +409,7 @@ struct sam_usbdev_s
* used and the class driver provides the buffering.
*/
__attribute__((__aligned__(4))) uint8_t ep0out[SAM_EP0_MAXPACKET];
aligned_data(4) uint8_t ep0out[SAM_EP0_MAXPACKET];
};
#endif
@@ -699,19 +699,19 @@ struct sam_usbhost_s
/* The pipe list */
__attribute__((__aligned__(4)))
aligned_data(4)
struct sam_pipe_s pipelist[SAM_USB_NENDPOINTS];
/* Pipe descriptors 2 banks for each pipe */
__attribute__((__aligned__(4)))
aligned_data(4)
struct usbhost_pipedesc_s pipe_descriptors[SAM_USB_NENDPOINTS *
SAM_USB_NBANKS()];
/* CTRL */
usbhost_ep_t ep0; /* Root hub port EP0 description */
__attribute__((__aligned__(4))) uint8_t ctrl_buffer[64];
aligned_data(4) uint8_t ctrl_buffer[64];
};
#endif
arch/arm/src/samv7/sam_emac.c
+15 -15
View File
@@ -665,26 +665,26 @@ static int sam_emac_configure(struct sam_emac_s *priv);
/* EMAC0 TX descriptors list */
static struct emac_txdesc_s g_emac0_tx0desc[CONFIG_SAMV7_EMAC0_NTXBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#if EMAC0_TX_DPADSIZE > 0
static uint8_t g_emac0_txdpad[EMAC0_TX_DPADSIZE] __atrribute__((used));
#endif
static struct emac_txdesc_s g_emac0_tx1desc[DUMMY_NBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC0 RX descriptors list */
static struct emac_rxdesc_s g_emac0_rx0desc[CONFIG_SAMV7_EMAC0_NRXBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#if EMAC0_RX_DPADSIZE > 0
static uint8_t g_emac0_rxdpad[EMAC0_RX_DPADSIZE] __atrribute__((used));
#endif
static struct emac_rxdesc_s g_emac0_rx1desc[DUMMY_NBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC0 Transmit Buffers
*
@@ -694,15 +694,15 @@ static struct emac_rxdesc_s g_emac0_rx1desc[DUMMY_NBUFFERS]
*/
static uint8_t g_emac0_tx0buffer[EMAC0_TX_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
static uint8_t g_emac0_tx1buffer[DUMMY_NBUFFERS * DUMMY_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC0 Receive Buffers */
static uint8_t g_emac0_rx0buffer[EMAC0_RX_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#endif
@@ -710,26 +710,26 @@ static uint8_t g_emac0_rx0buffer[EMAC0_RX_BUFSIZE]
/* EMAC1 TX descriptors list */
static struct emac_txdesc_s g_emac1_tx1desc[CONFIG_SAMV7_EMAC1_NTXBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#if EMAC1_TX_DPADSIZE > 0
static uint8_t g_emac1_txdpad[EMAC1_TX_DPADSIZE] __atrribute__((used));
#endif
static struct emac_txdesc_s g_emac1_tx1desc[DUMMY_NBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC1 RX descriptors list */
static struct emac_rxdesc_s g_emac1_rx1desc[CONFIG_SAMV7_EMAC1_NRXBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#if EMAC1_RX_DPADSIZE > 0
static uint8_t g_emac1_rxdpad[EMAC1_RX_DPADSIZE] __atrribute__((used));
#endif
static struct emac_rxdesc_s g_emac1_rx1desc[DUMMY_NBUFFERS]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC1 Transmit Buffers
*
@@ -739,18 +739,18 @@ static struct emac_rxdesc_s g_emac1_rx1desc[DUMMY_NBUFFERS]
*/
static uint8_t g_emac1_tx1buffer[EMAC1_TX_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
static uint8_t g_emac1_tx1buffer[DUMMY_NBUFFERS * DUMMY_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
/* EMAC1 Receive Buffers */
static uint8_t g_emac1_rxbuffer[EMAC1_RX_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
static uint8_t g_emac1_rx1buffer[DUMMY_NBUFFERS * DUMMY_BUFSIZE]
__attribute__((aligned(EMAC_ALIGN)));
aligned_data(EMAC_ALIGN);
#endif
#endif
arch/arm/src/samv7/sam_mcan.c
+2 -2
View File
@@ -991,7 +991,7 @@ static const struct can_ops_s g_mcanops =
static uint32_t g_mcan0_msgram[MCAN0_MSGRAM_WORDS]
#ifdef CONFIG_ARMV7M_DCACHE
__attribute__((aligned(MCAN_ALIGN)));
aligned_data(MCAN_ALIGN);
#else
;
#endif
@@ -1071,7 +1071,7 @@ static struct can_dev_s g_mcan0dev;
static uint32_t g_mcan1_msgram[MCAN1_MSGRAM_WORDS]
#ifdef CONFIG_ARMV7M_DCACHE
__attribute__((aligned(MCAN_ALIGN)));
aligned_data(MCAN_ALIGN);
#else
;
#endif
arch/arm/src/samv7/sam_usbdevhs.c
+1 -1
View File
@@ -632,7 +632,7 @@ static const struct usb_epdesc_s g_ep0desc =
/* This is a properly aligned pool of preallocated DMA transfer descriptors */
static struct sam_dtd_s g_dtdpool[CONFIG_SAMV7_USBDEVHS_NDTDS]
__attribute__ ((aligned(16)));
aligned_data(16);
#endif
#endif
arch/arm/src/stm32f7/stm32_ethernet.c
+4 -4
View File
@@ -666,16 +666,16 @@ struct stm32_ethmac_s
/* Descriptor allocations */
static union stm32_rxdesc_u g_rxtable[RXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static union stm32_txdesc_u g_txtable[TXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
/* Buffer allocations */
static uint8_t g_rxbuffer[RXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static uint8_t g_txbuffer[TXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
/* These are the pre-allocated Ethernet device structures */
arch/arm/src/stm32f7/stm32_serial.c
+1 -1
View File
@@ -236,7 +236,7 @@
#if defined(CONFIG_ARMV7M_DCACHE)
# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK)
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE);
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE)
#else
# define TXDMA_BUF_SIZE(b) (b)
# define TXDMA_BUF_ALIGN
arch/arm/src/stm32f7/stm32_spi.c
+1 -1
View File
@@ -1841,7 +1841,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
{
/* The dummy buffer is used to DMA with out increment into */
static uint8_t rxdummy[4] __attribute__((aligned(4)));
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n",
arch/arm/src/stm32h7/stm32_ethernet.c
+4 -4
View File
@@ -668,16 +668,16 @@ struct stm32_ethmac_s
/* Descriptor allocations */
static union stm32_desc_u g_rxtable[RXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static union stm32_desc_u g_txtable[TXTABLE_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
/* Buffer allocations */
static uint8_t g_rxbuffer[RXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static uint8_t g_txbuffer[TXBUFFER_ALLOC]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
/* These are the pre-allocated Ethernet device structures */
arch/arm/src/stm32h7/stm32_sdmmc.c
+2 -2
View File
@@ -372,7 +372,7 @@ struct stm32_dev_s
struct work_s cbfifo; /* Monitor for Lame FIFO */
#endif
uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA */
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
bool unaligned_rx; /* read buffer is not cache-line aligned */
#endif
@@ -649,7 +649,7 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
/* Input dma buffer for unaligned transfers */
#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_STM32H7_SDMMC_IDMA)
static uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
/****************************************************************************
arch/arm/src/stm32h7/stm32_serial.c
+1 -1
View File
@@ -379,7 +379,7 @@
#if defined(CONFIG_ARMV7M_DCACHE)
# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK)
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE);
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE)
#else
# define TXDMA_BUF_SIZE(b) (b)
# define TXDMA_BUF_ALIGN
arch/arm/src/stm32h7/stm32_spi.c
+1 -1
View File
@@ -1964,7 +1964,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
stm32_dmacfg_t rxdmacfg;
stm32_dmacfg_t txdmacfg;
static uint8_t rxdummy[ARMV7M_DCACHE_LINESIZE]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static const uint16_t txdummy = 0xffff;
FAR void * orig_rxbuffer = rxbuffer;
arch/arm/src/stm32h7/stm32_spi_slave.c
+12 -12
View File
@@ -344,10 +344,10 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops =
static
uint8_t SPI_SLAVE_OUTQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi1ctrlr = SPI_SLAVE_INIT(1);
#endif
@@ -356,10 +356,10 @@ static struct stm32_spidev_s g_spi1ctrlr = SPI_SLAVE_INIT(1);
static
uint8_t SPI_SLAVE_OUTQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi2ctrlr = SPI_SLAVE_INIT(2);
#endif
@@ -368,10 +368,10 @@ static struct stm32_spidev_s g_spi2ctrlr = SPI_SLAVE_INIT(2);
static
uint8_t SPI_SLAVE_OUTQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi3ctrlr = SPI_SLAVE_INIT(3);
#endif
@@ -380,10 +380,10 @@ static struct stm32_spidev_s g_spi3ctrlr = SPI_SLAVE_INIT(3);
static
uint8_t SPI_SLAVE_OUTQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi4ctrlr = SPI_SLAVE_INIT(4);
#endif
@@ -392,10 +392,10 @@ static struct stm32_spidev_s g_spi4ctrlr = SPI_SLAVE_INIT(4);
static
uint8_t SPI_SLAVE_OUTQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi5ctrlr = SPI_SLAVE_INIT(5);
#endif
@@ -406,10 +406,10 @@ static struct stm32_spidev_s g_spi5ctrlr = SPI_SLAVE_INIT(5);
static
uint8_t SPI_SLAVE_OUTQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static
uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)]
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
aligned_data(ARMV7M_DCACHE_LINESIZE);
static struct stm32_spidev_s g_spi6ctrlr = SPI_SLAVE_INIT(6);
#endif
arch/mips/src/pic32mx/pic32mx_usbdev.c
+1 -1
View File
@@ -576,7 +576,7 @@ static const struct usbdev_ops_s g_devops =
*/
static volatile struct usbotg_bdtentry_s g_bdt[4*PIC32MX_NENDPOINTS]
__attribute__ ((aligned(512)));
aligned_data(512);
/****************************************************************************
* Private Functions

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