diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h index 97cd32ebbc3..5c4a52ae4f3 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h @@ -107,139 +107,139 @@ /** edma_mux0 **/ -#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default) -#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0 -#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1 -#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2 -#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3 -#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4 -#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5 -#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6 -#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7 -#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request -#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0 -#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1 -#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0 -#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1 -#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9 -#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10 -#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0 -#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1 -#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9 -#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10 -#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0 -#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1 -#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9 -#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10 -#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0 -#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0 -#define DMA_REQ_RESERVED1 26 ///< RESERVED -#define DMA_REQ_RESERVED2 27 ///< RESERVED -#define DMA_REQ_RESERVED3 28 ///< RESERVED -#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request -#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request -#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request -#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request -#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request -#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request -#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request -#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request -#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request -#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request -#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request -#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request -#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request -#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request -#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request -#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request -#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request -#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request -#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request -#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request -#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request -#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request -#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request -#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request -#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request -#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request -#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request -#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request -#define DMA_REQ_RESERVED4 57 ///< RESERVED -#define DMA_REQ_ADC0 58 ///< ADC0 DMA request -#define DMA_REQ_ADC1 59 ///< ADC1 DMA request -#define DMA_REQ_ADC2 60 ///< ADC2 DMA request -#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request -#define DMA_REQ_ENABLED0 62 ///< Always enabled -#define DMA_REQ_ENABLED1 63 ///< Always enabled */ +#define DMA_REQ_DISABLED0 (0) ///< Channel disabled (default) +#define DMA_REQ_SIUL_0 (1) ///< SIUL DMA request 0 +#define DMA_REQ_SIUL_1 (2) ///< SIUL DMA request 1 +#define DMA_REQ_SIUL_2 (3) ///< SIUL DMA request 2 +#define DMA_REQ_SIUL_3 (4) ///< SIUL DMA request 3 +#define DMA_REQ_SIUL_4 (5) ///< SIUL DMA request 4 +#define DMA_REQ_SIUL_5 (6) ///< SIUL DMA request 5 +#define DMA_REQ_SIUL_6 (7) ///< SIUL DMA request 6 +#define DMA_REQ_SIUL_7 (8) ///< SIUL DMA request 7 +#define DMA_REQ_BCTU_FIFO1 (10) ///< BCTU DMA FIFO1 request +#define DMA_REQ_BCTU_0 (10) ///< BCTU DMA request 0 +#define DMA_REQ_BCTU_1 (11) ///< BCTU DMA request 1 +#define DMA_REQ_EMIOS0_0 (12) ///< eMIOS0 DMA request ch0 +#define DMA_REQ_EMIOS0_1 (13) ///< eMIOS0 DMA request ch1 +#define DMA_REQ_EMIOS0_9 (14) ///< eMIOS0 DMA request ch9 +#define DMA_REQ_EMIOS0_10 (15) ///< eMIOS0 DMA request ch10 +#define DMA_REQ_EMIOS1_0 (16) ///< eMIOS1 DMA request ch0 +#define DMA_REQ_EMIOS1_1 (17) ///< eMIOS1 DMA request ch1 +#define DMA_REQ_EMIOS1_9 (18) ///< eMIOS1 DMA request ch9 +#define DMA_REQ_EMIOS1_10 (19) ///< eMIOS1 DMA request ch10 +#define DMA_REQ_EMIOS2_0 (20) ///< eMIOS2 DMA request ch0 +#define DMA_REQ_EMIOS2_1 (21) ///< eMIOS2 DMA request ch1 +#define DMA_REQ_EMIOS2_9 (22) ///< eMIOS2 DMA request ch9 +#define DMA_REQ_EMIOS2_10 (23) ///< eMIOS2 DMA request ch10 +#define DMA_REQ_LCU0_0 (24) ///< LCU0 DMA request 0 +#define DMA_REQ_LCU1_0 (25) ///< LCU1 DMA request 0 +#define DMA_REQ_RESERVED1 (26) ///< RESERVED +#define DMA_REQ_RESERVED2 (27) ///< RESERVED +#define DMA_REQ_RESERVED3 (28) ///< RESERVED +#define DMA_REQ_FLEXCAN0 (29) ///< FLEXCAN0 DMA request +#define DMA_REQ_FLEXCAN1 (30) ///< FLEXCAN1 DMA request +#define DMA_REQ_FLEXCAN2 (31) ///< FLEXCAN2 DMA request +#define DMA_REQ_FLEXCAN3 (32) ///< FLEXCAN3 DMA request +#define DMA_REQ_FLEXIO_0 (33) ///< FLEXIO DMA shifter0 | timer0 request +#define DMA_REQ_FLEXIO_1 (34) ///< FLEXIO DMA shifter1 | timer1 request +#define DMA_REQ_FLEXIO_2 (35) ///< FLEXIO DMA shifter2 | timer2 request +#define DMA_REQ_FLEXIO_3 (36) ///< FLEXIO DMA shifter3 | timer3 request +#define DMA_REQ_LPUART08_TX (37) ///< LPUART0 | LPUART8 DMA transmit request +#define DMA_REQ_LPUART08_RX (38) ///< LPUART0 | LPUART8 DMA receive request +#define DMA_REQ_LPUART19_TX (39) ///< LPUART1 | LPUART9 DMA transmit request +#define DMA_REQ_LPUART19_RX (40) ///< LPUART1 | LPUART9 DMA receive request +#define DMA_REQ_LPI2C0_RX (41) ///< LPI2C0 DMA receive | receive slave request +#define DMA_REQ_LPI2C0_TX (42) ///< LPI2C0 DMA transmit | transmit slave request +#define DMA_REQ_LPSPI0_TX (43) ///< LPSPI0 DMA transmit request +#define DMA_REQ_LPSPI0_RX (44) ///< LPSPI0 DMA receive request +#define DMA_REQ_LPSPI1_TX (45) ///< LPSPI1 DMA transmit request +#define DMA_REQ_LPSPI1_RX (46) ///< LPSPI1 DMA receive request +#define DMA_REQ_LPSPI2_TX (47) ///< LPSPI2 DMA transmit request +#define DMA_REQ_LPSPI2_RX (48) ///< LPSPI2 DMA receive request +#define DMA_REQ_LPSPI3_TX (49) ///< LPSPI3 DMA transmit request +#define DMA_REQ_LPSPI3_RX (50) ///< LPSPI3 DMA receive request +#define DMA_REQ_I3C0_RX (51) ///< I3C0 DMA receive request +#define DMA_REQ_I3C0_TX (52) ///< I3C0 DMA transmit request +#define DMA_REQ_QSPI_RX (53) ///< QSPI DMA receive buffer drain request +#define DMA_REQ_QSPI_TX (54) ///< QSPI DMA transmit buffer fill request +#define DMA_REQ_SAI0_RX (55) ///< SAI0 DMA receive request +#define DMA_REQ_SAI0_TX (56) ///< SAI0 DMA transmit request +#define DMA_REQ_RESERVED4 (57) ///< RESERVED +#define DMA_REQ_ADC0 (58) ///< ADC0 DMA request +#define DMA_REQ_ADC1 (59) ///< ADC1 DMA request +#define DMA_REQ_ADC2 (60) ///< ADC2 DMA request +#define DMA_REQ_LPCMP0 (61) ///< LPCMP0 DMA request +#define DMA_REQ_ENABLED0 (62) ///< Always enabled +#define DMA_REQ_ENABLED1 (63) ///< Always enabled */ /** edma_mux1 **/ -#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default) -#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8 -#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9 -#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10 -#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11 -#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12 -#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13 -#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14 -#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15 -#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request -#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2 -#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16 -#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17 -#define DMA_REQ_EMIOS0_18 DMAMUX_CHCFG_DMAMUX1 | 13 ///< eMIOS0 DMA request ch18 -#define DMA_REQ_EMIOS0_19 DMAMUX_CHCFG_DMAMUX1 | 14 ///< eMIOS0 DMA request ch19 -#define DMA_REQ_EMIOS1_16 DMAMUX_CHCFG_DMAMUX1 | 15 ///< eMIOS1 DMA request ch16 -#define DMA_REQ_EMIOS1_17 DMAMUX_CHCFG_DMAMUX1 | 16 ///< eMIOS1 DMA request ch17 -#define DMA_REQ_EMIOS1_18 DMAMUX_CHCFG_DMAMUX1 | 17 ///< eMIOS1 DMA request ch18 -#define DMA_REQ_EMIOS1_19 DMAMUX_CHCFG_DMAMUX1 | 18 ///< eMIOS1 DMA request ch19 -#define DMA_REQ_EMIOS2_16 DMAMUX_CHCFG_DMAMUX1 | 19 ///< eMIOS2 DMA request ch16 -#define DMA_REQ_EMIOS2_17 DMAMUX_CHCFG_DMAMUX1 | 20 ///< eMIOS2 DMA request ch17 -#define DMA_REQ_EMIOS2_18 DMAMUX_CHCFG_DMAMUX1 | 21 ///< eMIOS2 DMA request ch18 -#define DMA_REQ_EMIOS2_19 DMAMUX_CHCFG_DMAMUX1 | 22 ///< eMIOS2 DMA request ch19 -#define DMA_REQ_LCU0_1 DMAMUX_CHCFG_DMAMUX1 | 23 ///< LCU0 DMA request 1 -#define DMA_REQ_LCU0_2 DMAMUX_CHCFG_DMAMUX1 | 24 ///< LCU1 DMA request 2 -#define DMA_REQ_LCU1_1 DMAMUX_CHCFG_DMAMUX1 | 25 ///< LCU1 DMA request 1 -#define DMA_REQ_LCU1_2 DMAMUX_CHCFG_DMAMUX1 | 26 ///< LCU1 DMA request 2 -#define DMA_REQ_ENET_0 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[0] DMA request -#define DMA_REQ_ENET_1 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[1] DMA request -#define DMA_REQ_ENET_2 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[2] DMA request -#define DMA_REQ_ENET_3 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[3] DMA request -#define DMA_REQ_RESERVED5 DMAMUX_CHCFG_DMAMUX1 | 28 ///< RESERVED -#define DMA_REQ_RESERVED6 DMAMUX_CHCFG_DMAMUX1 | 29 ///< RESERVED -#define DMA_REQ_FLECAN4 DMAMUX_CHCFG_DMAMUX1 | 30 ///< FLEXCAN4 DMA request -#define DMA_REQ_FLECAN5 DMAMUX_CHCFG_DMAMUX1 | 31 ///< FLEXCAN5 DMA request -#define DMA_REQ_RESERVED7 DMAMUX_CHCFG_DMAMUX1 | 32 ///< RESERVED -#define DMA_REQ_RESERVED8 DMAMUX_CHCFG_DMAMUX1 | 33 ///< RESERVED -#define DMA_REQ_FLEXIO_4 DMAMUX_CHCFG_DMAMUX1 | 34 ///< FLEXIO DMA shifter4 | timer4 request -#define DMA_REQ_FLEXIO_5 DMAMUX_CHCFG_DMAMUX1 | 35 ///< FLEXIO DMA shifter5 | timer5 request -#define DMA_REQ_FLEXIO_6 DMAMUX_CHCFG_DMAMUX1 | 36 ///< FLEXIO DMA shifter6 | timer6 request -#define DMA_REQ_FLEXIO_7 DMAMUX_CHCFG_DMAMUX1 | 37 ///< FLEXIO DMA shifter7 | timer7 request -#define DMA_REQ_LPUART210_TX DMAMUX_CHCFG_DMAMUX1 | 38 ///< LPUART2 | LPUART10 DMA transmit request -#define DMA_REQ_LPUART210_RX DMAMUX_CHCFG_DMAMUX1 | 39 ///< LPUART2 | LPUART10 DMA receive request -#define DMA_REQ_LPUART311_TX DMAMUX_CHCFG_DMAMUX1 | 40 ///< LPUART3 | LPUART11 DMA transmit request -#define DMA_REQ_LPUART311_RX DMAMUX_CHCFG_DMAMUX1 | 41 ///< LPUART3 | LPUART11 DMA receive request -#define DMA_REQ_LPUART412_TX DMAMUX_CHCFG_DMAMUX1 | 42 ///< LPUART4 | LPUART12 DMA transmit request -#define DMA_REQ_LPUART412_RX DMAMUX_CHCFG_DMAMUX1 | 43 ///< LPUART4 | LPUART12 DMA receive request -#define DMA_REQ_LPUART513_TX DMAMUX_CHCFG_DMAMUX1 | 44 ///< LPUART5 | LPUART13 DMA transmit request -#define DMA_REQ_LPUART513_RX DMAMUX_CHCFG_DMAMUX1 | 45 ///< LPUART5 | LPUART13 DMA receive request -#define DMA_REQ_LPUART614_TX DMAMUX_CHCFG_DMAMUX1 | 46 ///< LPUART6 | LPUART14 DMA transmit request -#define DMA_REQ_LPUART614_RX DMAMUX_CHCFG_DMAMUX1 | 47 ///< LPUART6 | LPUART14 DMA receive request -#define DMA_REQ_LPUART715_TX DMAMUX_CHCFG_DMAMUX1 | 48 ///< LPUART7 | LPUART15 DMA transmit request -#define DMA_REQ_LPUART715_RX DMAMUX_CHCFG_DMAMUX1 | 49 ///< LPUART7 | LPUART15 DMA receive request -#define DMA_REQ_LPI2C1_RX DMAMUX_CHCFG_DMAMUX1 | 50 ///< LPI2C1 DMA receive | receive slave request -#define DMA_REQ_LPI2C1_TX DMAMUX_CHCFG_DMAMUX1 | 51 ///< LPI2C1 DMA transmit | transmit slave request -#define DMA_REQ_LPSPI4_TX DMAMUX_CHCFG_DMAMUX1 | 52 ///< LPSPI4 DMA transmit request -#define DMA_REQ_LPSPI4_RX DMAMUX_CHCFG_DMAMUX1 | 53 ///< LPSPI4 DMA receive request -#define DMA_REQ_LPSPI5_TX DMAMUX_CHCFG_DMAMUX1 | 54 ///< LPSPI5 DMA transmit request -#define DMA_REQ_LPSPI5_RX DMAMUX_CHCFG_DMAMUX1 | 55 ///< LPSPI5 DMA receive request -#define DMA_REQ_SAI1_RX DMAMUX_CHCFG_DMAMUX1 | 56 ///< SAI1 DMA RX request -#define DMA_REQ_SAI1_TX DMAMUX_CHCFG_DMAMUX1 | 57 ///< SAI1 DMA TX request -#define DMA_REQ_RESERVED9 DMAMUX_CHCFG_DMAMUX1 | 58 ///< RESERVED -#define DMA_REQ_RESERVED10 DMAMUX_CHCFG_DMAMUX1 | 59 ///< RESERVED -#define DMA_REQ_LPCMP1 DMAMUX_CHCFG_DMAMUX1 | 60 ///< LPCMP1 DMA request -#define DMA_REQ_LPCMP2 DMAMUX_CHCFG_DMAMUX1 | 61 ///< LPCMP2 DMA request -#define DMA_REQ_ENABLED2 DMAMUX_CHCFG_DMAMUX1 | 62 ///< Always enabled -#define DMA_REQ_ENABLED3 DMAMUX_CHCFG_DMAMUX1 | 63 ///< Always enabled +#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) ///< Channel disabled (default) +#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) ///< SIUL DMA request 8 +#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) ///< SIUL DMA request 9 +#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) ///< SIUL DMA request 10 +#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) ///< SIUL DMA request 11 +#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) ///< SIUL DMA request 12 +#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) ///< SIUL DMA request 13 +#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) ///< SIUL DMA request 14 +#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) ///< SIUL DMA request 15 +#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) ///< BCTU DMA FIFO2 request +#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) ///< BCTU DMA request 2 +#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) ///< eMIOS0 DMA request ch16 +#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) ///< eMIOS0 DMA request ch17 +#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) ///< eMIOS0 DMA request ch18 +#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) ///< eMIOS0 DMA request ch19 +#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) ///< eMIOS1 DMA request ch16 +#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) ///< eMIOS1 DMA request ch17 +#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) ///< eMIOS1 DMA request ch18 +#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) ///< eMIOS1 DMA request ch19 +#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) ///< eMIOS2 DMA request ch16 +#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) ///< eMIOS2 DMA request ch17 +#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) ///< eMIOS2 DMA request ch18 +#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) ///< eMIOS2 DMA request ch19 +#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) ///< LCU0 DMA request 1 +#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) ///< LCU1 DMA request 2 +#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) ///< LCU1 DMA request 1 +#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) ///< LCU1 DMA request 2 +#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[0] DMA request +#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[1] DMA request +#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[2] DMA request +#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[3] DMA request +#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) ///< RESERVED +#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) ///< RESERVED +#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) ///< FLEXCAN4 DMA request +#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) ///< FLEXCAN5 DMA request +#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) ///< RESERVED +#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) ///< RESERVED +#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) ///< FLEXIO DMA shifter4 | timer4 request +#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) ///< FLEXIO DMA shifter5 | timer5 request +#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) ///< FLEXIO DMA shifter6 | timer6 request +#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) ///< FLEXIO DMA shifter7 | timer7 request +#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) ///< LPUART2 | LPUART10 DMA transmit request +#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) ///< LPUART2 | LPUART10 DMA receive request +#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) ///< LPUART3 | LPUART11 DMA transmit request +#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) ///< LPUART3 | LPUART11 DMA receive request +#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) ///< LPUART4 | LPUART12 DMA transmit request +#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) ///< LPUART4 | LPUART12 DMA receive request +#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) ///< LPUART5 | LPUART13 DMA transmit request +#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) ///< LPUART5 | LPUART13 DMA receive request +#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) ///< LPUART6 | LPUART14 DMA transmit request +#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) ///< LPUART6 | LPUART14 DMA receive request +#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) ///< LPUART7 | LPUART15 DMA transmit request +#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) ///< LPUART7 | LPUART15 DMA receive request +#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) ///< LPI2C1 DMA receive | receive slave request +#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) ///< LPI2C1 DMA transmit | transmit slave request +#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) ///< LPSPI4 DMA transmit request +#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) ///< LPSPI4 DMA receive request +#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) ///< LPSPI5 DMA transmit request +#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) ///< LPSPI5 DMA receive request +#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) ///< SAI1 DMA RX request +#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) ///< SAI1 DMA TX request +#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) ///< RESERVED +#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) ///< RESERVED +#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) ///< LPCMP1 DMA request +#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) ///< LPCMP2 DMA request +#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) ///< Always enabled +#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) ///< Always enabled #endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h index 5fcead5f76f..cb39c54d5ec 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h @@ -1311,13 +1311,13 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = #define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */ #define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT) -#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) +#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) #define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */ #define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT) -#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) +#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) #define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */ #define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT) -#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) +#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) # define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ # define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ # define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ @@ -1328,7 +1328,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = #define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */ #define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT) -#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) +#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) /* TCDn Transfer Size (TCDn_NBYTES) */ @@ -1364,7 +1364,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = #define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT) #define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */ #define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT) -#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) #define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ /* TCDn Last Destination Address Adjustment / Scatter Gather Address Register @@ -1386,7 +1386,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = #define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */ #define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */ #define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) -#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) +#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) /* Bit 13: Reserved */ #define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */ #define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT) @@ -1402,7 +1402,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] = #define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT) #define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */ #define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT) -#define EDMA_TCD_BITER_LINKCH(n) ((n << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) +#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) #define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ /**************************************************************************** diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h index 3ebb256b27a..b53f34ef87c 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h @@ -594,11 +594,11 @@ #define EMAC_MAC_CONFIGURATION_TE (1 << 1) /* Bit 1: Transmitter Enable */ #define EMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2) /* Bits 2-4: Preamble Length for Transmit Packets */ #define EMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3 << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) -#define EMAC_MAC_CONFIGURATION_PRELEN(n) ((n << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK) +#define EMAC_MAC_CONFIGURATION_PRELEN(n) (((n) << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK) #define EMAC_MAC_CONFIGURATION_DC (1 << 4) /* Bit 4: Deferral Check */ #define EMAC_MAC_CONFIGURATION_BL_SHIFT (5) /* Bits 5-7: Back-Off Limit */ #define EMAC_MAC_CONFIGURATION_BL_MASK (0x3 << EMAC_MAC_CONFIGURATION_BL_SHIFT) -#define EMAC_MAC_CONFIGURATION_BL(n) ((n << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK) +#define EMAC_MAC_CONFIGURATION_BL(n) (((n) << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK) #define EMAC_MAC_CONFIGURATION_DR (1 << 8) /* Bit 8: Disable Retry */ #define EMAC_MAC_CONFIGURATION_DCRS (1 << 9) /* Bit 9: Disable Carrier Sense During Transmission */ #define EMAC_MAC_CONFIGURATION_DO (1 << 10) /* Bit 10: Disable Receive Own */ @@ -616,16 +616,16 @@ #define EMAC_MAC_CONFIGURATION_GPSLCE (1 << 23) /* Bit 23: Giant Packet Size Limit Control Enable */ #define EMAC_MAC_CONFIGURATION_IPG_SHIFT (24) /* Bits 24-27: Inter-Packet Gap */ #define EMAC_MAC_CONFIGURATION_IPG_MASK (0x7 << EMAC_MAC_CONFIGURATION_IPG_SHIFT) -#define EMAC_MAC_CONFIGURATION_IPG(n) ((n << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK) +#define EMAC_MAC_CONFIGURATION_IPG(n) (((n) << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK) #define EMAC_MAC_CONFIGURATION_IPC (1 << 27) /* Bit 27: Checksum Offload */ #define EMAC_MAC_CONFIGURATION_SARC_SHIFT (28) /* Bits 28-31: Source Address Insertion Or Replacement Control */ #define EMAC_MAC_CONFIGURATION_SARC_MASK (0x7 << EMAC_MAC_CONFIGURATION_SARC_SHIFT) -#define EMAC_MAC_CONFIGURATION_SARC(n) ((n << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK) +#define EMAC_MAC_CONFIGURATION_SARC(n) (((n) << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK) /* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */ #define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */ #define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) -#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) ((n << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK) +#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK) #define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */ #define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */ #define EMAC_MAC_EXT_CONFIGURATION_USP (1 << 18) /* Bit 18: Unicast Slow Protocol Packet Detect */ @@ -633,7 +633,7 @@ #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */ #define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */ #define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) -#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) ((n << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK) +#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK) /* MAC Packet Filter (MAC_PACKET_FILTER) */ #define EMAC_MAC_PACKET_FILTER_PR (1 << 0) /* Bit 0: Promiscuous Mode */ @@ -644,7 +644,7 @@ #define EMAC_MAC_PACKET_FILTER_DBF (1 << 5) /* Bit 5: Disable Broadcast Packets */ #define EMAC_MAC_PACKET_FILTER_PCF_SHIFT (6) /* Bits 6-8: Pass Control Packets */ #define EMAC_MAC_PACKET_FILTER_PCF_MASK (0x3 << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) -#define EMAC_MAC_PACKET_FILTER_PCF(n) ((n << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK) +#define EMAC_MAC_PACKET_FILTER_PCF(n) (((n) << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK) #define EMAC_MAC_PACKET_FILTER_SAIF (1 << 8) /* Bit 8: SA Inverse Filtering */ #define EMAC_MAC_PACKET_FILTER_SAF (1 << 9) /* Bit 9: Source Address Filter Enable */ #define EMAC_MAC_PACKET_FILTER_HPF (1 << 10) /* Bit 10: Hash Or Perfect Filter */ @@ -656,23 +656,23 @@ /* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */ #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */ #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) -#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) ((n << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK) +#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) (((n) << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK) #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */ /* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */ #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */ #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) -#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) ((n << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK) +#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) (((n) << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK) /* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */ #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */ #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) -#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) ((n << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK) +#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) (((n) << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK) /* MAC VLAN Tag (MAC_VLAN_TAG) */ #define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */ #define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT) -#define EMAC_MAC_VLAN_TAG_VL(n) ((n << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK) +#define EMAC_MAC_VLAN_TAG_VL(n) (((n) << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK) #define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */ #define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */ #define EMAC_MAC_VLAN_TAG_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */ @@ -680,14 +680,14 @@ #define EMAC_MAC_VLAN_TAG_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */ #define EMAC_MAC_VLAN_TAG_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */ #define EMAC_MAC_VLAN_TAG_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) -#define EMAC_MAC_VLAN_TAG_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK) +#define EMAC_MAC_VLAN_TAG_EVLS(n) (((n) << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK) #define EMAC_MAC_VLAN_TAG_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */ #define EMAC_MAC_VLAN_TAG_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */ #define EMAC_MAC_VLAN_TAG_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */ #define EMAC_MAC_VLAN_TAG_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */ #define EMAC_MAC_VLAN_TAG_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */ #define EMAC_MAC_VLAN_TAG_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) -#define EMAC_MAC_VLAN_TAG_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EIVLS_MASK) +#define EMAC_MAC_VLAN_TAG_EIVLS(n) (((n) << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EIVLS_MASK) #define EMAC_MAC_VLAN_TAG_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */ /* MAC VLAN Tag Control (MAC_VLAN_TAG_CTRL) */ @@ -695,7 +695,7 @@ #define EMAC_MAC_VLAN_TAG_CTRL_CT (1 << 1) /* Bit 1: Command Type */ #define EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2) /* Bits 2-4: Offset */ #define EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) -#define EMAC_MAC_VLAN_TAG_CTRL_OFS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK) +#define EMAC_MAC_VLAN_TAG_CTRL_OFS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK) #define EMAC_MAC_VLAN_TAG_CTRL_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */ #define EMAC_MAC_VLAN_TAG_CTRL_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */ #define EMAC_MAC_VLAN_TAG_CTRL_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */ @@ -703,20 +703,20 @@ #define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */ #define EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */ #define EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) -#define EMAC_MAC_VLAN_TAG_CTRL_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK) +#define EMAC_MAC_VLAN_TAG_CTRL_EVLS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK) #define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */ #define EMAC_MAC_VLAN_TAG_CTRL_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */ #define EMAC_MAC_VLAN_TAG_CTRL_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */ #define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */ #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */ #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) -#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK) +#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK) #define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */ /* MAC VLAN Tag Data (MAC_VLAN_TAG_DATA) */ #define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ #define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) -#define EMAC_MAC_VLAN_TAG_DATA_VID(n) ((n << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK) +#define EMAC_MAC_VLAN_TAG_DATA_VID(n) (((n) << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK) #define EMAC_MAC_VLAN_TAG_DATA_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_DATA_ETV (1 << 17) /* Bit 17: VLAN Comparison */ #define EMAC_MAC_VLAN_TAG_DATA_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */ @@ -728,7 +728,7 @@ /* MAC VLAN Tag Filter 0 (MAC_VLAN_TAG_FILTER0) */ #define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ #define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) -#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK) +#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER0_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER0_ETV (1 << 17) /* Bit 17: VLAN Comparison */ #define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */ @@ -740,7 +740,7 @@ /* MAC VLAN Tag Filter 1 (MAC_VLAN_TAG_FILTER1) */ #define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ #define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) -#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK) +#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER1_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER1_ETV (1 << 17) /* Bit 17: VLAN Comparison */ #define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */ @@ -752,7 +752,7 @@ /* MAC VLAN Tag Filter 2 (MAC_VLAN_TAG_FILTER2) */ #define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ #define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) -#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK) +#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER2_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER2_ETV (1 << 17) /* Bit 17: VLAN Comparison */ #define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */ @@ -764,7 +764,7 @@ /* MAC VLAN Tag Filter 3 (MAC_VLAN_TAG_FILTER3) */ #define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */ #define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) -#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK) +#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK) #define EMAC_MAC_VLAN_TAG_FILTER3_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */ #define EMAC_MAC_VLAN_TAG_FILTER3_ETV (1 << 17) /* Bit 17: VLAN Comparison */ #define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */ @@ -776,15 +776,15 @@ /* MAC VLAN Hash Table (MAC_VLAN_HASH_TABLE) */ #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0) /* Bits 0-16: VLAN Hash Table */ #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFF << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) -#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) ((n << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK) +#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) (((n) << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK) /* MAC VLAN Inclusion Or Replacement (MAC_VLAN_INCL) */ #define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */ #define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_VLAN_INCL_VLT_SHIFT) -#define EMAC_MAC_VLAN_INCL_VLT(n) ((n << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK) +#define EMAC_MAC_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK) #define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control */ #define EMAC_MAC_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_VLAN_INCL_VLC_SHIFT) -#define EMAC_MAC_VLAN_INCL_VLC(n) ((n << EMAC_MAC_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_VLAN_INCL_VLC_MASK) +#define EMAC_MAC_VLAN_INCL_VLC(n) (((n) << EMAC_MAC_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_VLAN_INCL_VLC_MASK) #define EMAC_MAC_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */ #define EMAC_MAC_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */ #define EMAC_MAC_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */ @@ -796,10 +796,10 @@ /* Inner VLAN Tag Inclusion Or Replacement (MAC_INNER_VLAN_INCL) */ #define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */ #define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) -#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK) +#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK) #define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control in Transmit Packets */ #define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) -#define EMAC_MAC_INNER_VLAN_INCL_VLC(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK) +#define EMAC_MAC_INNER_VLAN_INCL_VLC(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK) #define EMAC_MAC_INNER_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */ #define EMAC_MAC_INNER_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */ #define EMAC_MAC_INNER_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */ @@ -809,11 +809,11 @@ #define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1 << 1) /* Bit 1: Transmit Flow Control Enable */ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4) /* Bits 4-7: Pause Low Threshold */ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x7 << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK) +#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK) #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16) /* Bits 16-32: Pause Time */ #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) -#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK) +#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK) /* MAC Receive Flow Control (MAC_RX_FLOW_CTRL) */ #define EMAC_MAC_RX_FLOW_CTRL_RFE (1 << 0) /* Bit 0: Receive Flow Control Enable */ @@ -830,13 +830,13 @@ /* MAC RxQ Control 0 (MAC_RXQ_CTRL0) */ #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0) /* Bits 0-2: Receive Queue 0 Enable */ #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) -#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK) +#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(n) (((n) << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK) #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ0EN(0) #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x1) #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x2) #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-4: Receive Queue 1 Enable */ #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) -#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK) +#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(n) (((n) << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK) #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ1EN(0) #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x1) #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x2) @@ -844,32 +844,32 @@ /* Receive Queue Control 1 (MAC_RXQ_CTRL1) */ #define EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0) /* Bits 0-3: AV Untagged Control Packets Queue */ #define EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_AVCPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK) +#define EMAC_MAC_RXQ_CTRL1_AVCPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK) #define EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT (4) /* Bits 4-7: PTP Packets Queue */ #define EMAC_MAC_RXQ_CTRL1_PTPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_PTPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK) +#define EMAC_MAC_RXQ_CTRL1_PTPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK) #define EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-15: Untagged Packet Queue */ #define EMAC_MAC_RXQ_CTRL1_UPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_UPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK) +#define EMAC_MAC_RXQ_CTRL1_UPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK) #define EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-19: Multicast And Broadcast Queue */ #define EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_MCBCQ(n) ((n << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK) +#define EMAC_MAC_RXQ_CTRL1_MCBCQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK) #define EMAC_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast And Broadcast Queue Enable */ #define EMAC_MAC_RXQ_CTRL1_TACPQE (1 << 21) /* Bit 21: Tagged AV Control Packets Queuing Enable */ #define EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT (22) /* Bits 22-24: Tagged PTP Over Ethernet Packets Queuing Control */ #define EMAC_MAC_RXQ_CTRL1_TPQC_MASK (0x3 << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_TPQC(n) ((n << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK) +#define EMAC_MAC_RXQ_CTRL1_TPQC(n) (((n) << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK) #define EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT (24) /* Bits 24-27: Frame Preemption Residue Queue */ #define EMAC_MAC_RXQ_CTRL1_FPRQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) -#define EMAC_MAC_RXQ_CTRL1_FPRQ(n) ((n << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK) +#define EMAC_MAC_RXQ_CTRL1_FPRQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK) /* MAC RxQ Control 2 (MAC_RXQ_CTRL2) */ #define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-8: Priorities Selected In Receive Queue 0 */ #define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) -#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK) +#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK) #define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-16: Priorities Selected In Receive Queue 1 */ #define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) -#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK) +#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK) /* MAC Interrupt Status (MAC_INTERRUPT_STATUS) */ #define EMAC_MAC_INTERRUPT_STATUS_PHYIS (1 << 3) /* Bit 3: PHY Interrupt */ @@ -904,20 +904,20 @@ /* MAC Version (MAC_VERSION) */ #define EMAC_MAC_VERSION_IPVER_SHIFT (0) /* Bits 0-8: IP Version */ #define EMAC_MAC_VERSION_IPVER_MASK (0xFF << EMAC_MAC_VERSION_IPVER_SHIFT) -#define EMAC_MAC_VERSION_IPVER(n) ((n << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK) +#define EMAC_MAC_VERSION_IPVER(n) (((n) << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK) #define EMAC_MAC_VERSION_CFGVER_SHIFT (8) /* Bits 8-16: IP Configuration Version */ #define EMAC_MAC_VERSION_CFGVER_MASK (0xFF << EMAC_MAC_VERSION_CFGVER_SHIFT) -#define EMAC_MAC_VERSION_CFGVER(n) ((n << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK) +#define EMAC_MAC_VERSION_CFGVER(n) (((n) << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK) /* MAC Debug (MAC_DEBUG) */ #define EMAC_MAC_DEBUG_RPESTS (1 << 0) /* Bit 0: Receive Protocol Engine Status */ #define EMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1) /* Bits 1-3: MAC Receive Packet Controller FIFO Status */ #define EMAC_MAC_DEBUG_RFCFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) -#define EMAC_MAC_DEBUG_RFCFCSTS(n) ((n << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) & EMAC_MAC_DEBUG_RFCFCSTS_MASK) +#define EMAC_MAC_DEBUG_RFCFCSTS(n) (((n) << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) & EMAC_MAC_DEBUG_RFCFCSTS_MASK) #define EMAC_MAC_DEBUG_TPESTS (1 << 16) /* Bit 16: MAC GMII Or MII Transmit Protocol Engine Status */ #define EMAC_MAC_DEBUG_TFCSTS_SHIFT (17) /* Bits 17-19: MAC Transmit Packet Controller Status */ #define EMAC_MAC_DEBUG_TFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_TFCSTS_SHIFT) -#define EMAC_MAC_DEBUG_TFCSTS(n) ((n << EMAC_MAC_DEBUG_TFCSTS_SHIFT) & EMAC_MAC_DEBUG_TFCSTS_MASK) +#define EMAC_MAC_DEBUG_TFCSTS(n) (((n) << EMAC_MAC_DEBUG_TFCSTS_SHIFT) & EMAC_MAC_DEBUG_TFCSTS_MASK) /* MAC Hardware Feature 0 (MAC_HW_FEATURE0) */ #define EMAC_MAC_HW_FEATURE0_MIISEL (1 << 0) /* Bit 0: 10 or 100 Mbit/s Support Feature */ @@ -936,31 +936,31 @@ #define EMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) /* Bit 16: Receive Checksum Offload Feature */ #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18) /* Bits 18-23: MAC Addresses 1-31 */ #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1F << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) -#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK) +#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK) #define EMAC_MAC_HW_FEATURE0_MACADR32SEL (1 << 23) /* Bit 23: MAC Addresses 32-63 */ #define EMAC_MAC_HW_FEATURE0_MACADR64SEL (1 << 24) /* Bit 24: MAC Addresses 64-127 */ #define EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25) /* Bits 25-27: Timestamp System Time Source Feature */ #define EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x3 << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) -#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(n) ((n << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK) +#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK) #define EMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27) /* Bit 27: SA or VLAN Insertion Feature */ #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28) /* Bits 28-31: Active PHY Feature */ #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0x7 << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) -#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK) +#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK) /* MAC Hardware Feature 1 (MAC_HW_FEATURE1) */ #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0) /* Bits 0-5: MTL Receive FIFO Size Feature */ #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) -#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK) +#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK) #define EMAC_MAC_HW_FEATURE1_SPRAM (1 << 5) /* Bit 5: Single Port RAM Feature */ #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6) /* Bits 6-11: MTL Transmit FIFO Size Feature */ #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) -#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK) +#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK) #define EMAC_MAC_HW_FEATURE1_OSTEN (1 << 11) /* Bit 11: One-Step Timestamping Enable Feature */ #define EMAC_MAC_HW_FEATURE1_PTOEN (1 << 12) /* Bit 12: PTP Offload Enable Feature */ #define EMAC_MAC_HW_FEATURE1_ADVTHWORD (1 << 13) /* Bit 13: IEEE 1588 High-Word Feature */ #define EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14) /* Bits 14-16: Address Width Feature */ #define EMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3 << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) -#define EMAC_MAC_HW_FEATURE1_ADDR64(n) ((n << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK) +#define EMAC_MAC_HW_FEATURE1_ADDR64(n) (((n) << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK) #define EMAC_MAC_HW_FEATURE1_DCBEN (1 << 16) /* Bit 16: DCB Enable Feature */ #define EMAC_MAC_HW_FEATURE1_SPHEN (1 << 17) /* Bit 17: Split Header Enable Feature */ #define EMAC_MAC_HW_FEATURE1_TSOEN (1 << 18) /* Bit 18: TCP Segmentation Offload Enable Feature */ @@ -970,57 +970,57 @@ #define EMAC_MAC_HW_FEATURE1_POUOST (1 << 23) /* Bit 23: One Step For PTP Over UDP/IP Feature */ #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24) /* Bits 24-26: Hash Table Size */ #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3 << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) -#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) ((n << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK) +#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) (((n) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK) #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27) /* Bits 27-31: L3 Or L4 Filter Number */ #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xF << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) -#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) ((n << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK) +#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) (((n) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK) /* MAC Hardware Feature 2 (MAC_HW_FEATURE2) */ #define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0) /* Bits 0-4: Number Of MTL Receive Queues */ #define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) -#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK) +#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK) #define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6) /* Bits 6-10: Number Of MTL Transmit Queues */ #define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) -#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK) +#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK) #define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12) /* Bits 12-16: Number Of DMA Receive Channels */ #define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) -#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK) +#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK) #define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18) /* Bits 18-22: Number Of DMA Transmit Channels */ #define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) -#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK) +#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK) #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24) /* Bits 24-27: Number Of PPS Outputs */ #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) -#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(n) ((n << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK) +#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(n) (((n) << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK) #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28) /* Bits 28-31: Number Of Auxiliary Snapshot Inputs */ #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) -#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(n) ((n << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK) +#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(n) (((n) << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK) /* MAC Hardware Feature 3 (MAC_HW_FEATURE3) */ #define EMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0) /* Bits 0-3: Number Of Extended VLAN Tag Filters Indicates the number of selected extended VLAN tag filters. */ #define EMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7 << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) -#define EMAC_MAC_HW_FEATURE3_NRVF(n) ((n << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) & EMAC_MAC_HW_FEATURE3_NRVF_MASK) +#define EMAC_MAC_HW_FEATURE3_NRVF(n) (((n) << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) & EMAC_MAC_HW_FEATURE3_NRVF_MASK) #define EMAC_MAC_HW_FEATURE3_CBTISEL (1 << 4) /* Bit 4: Queue/Channel Based VLAN Tag Insertion On Transmit Feature */ #define EMAC_MAC_HW_FEATURE3_DVLAN (1 << 5) /* Bit 5: Double VLAN Tag Processing Feature */ #define EMAC_MAC_HW_FEATURE3_PDUPSEL (1 << 9) /* Bit 9: Broadcast/Multicast Packet Duplication Feature */ #define EMAC_MAC_HW_FEATURE3_FRPSEL (1 << 10) /* Bit 10: Flexible Receive Parser Feature */ #define EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11) /* Bits 11-13: Flexible Receive Parser Buffer Size */ #define EMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) -#define EMAC_MAC_HW_FEATURE3_FRPBS(n) ((n << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK) +#define EMAC_MAC_HW_FEATURE3_FRPBS(n) (((n) << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK) #define EMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13) /* Bits 13-15: Flexible Receive Parser Table Entry Size */ #define EMAC_MAC_HW_FEATURE3_FRPES_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) -#define EMAC_MAC_HW_FEATURE3_FRPES(n) ((n << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPES_MASK) +#define EMAC_MAC_HW_FEATURE3_FRPES(n) (((n) << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPES_MASK) #define EMAC_MAC_HW_FEATURE3_ESTSEL (1 << 16) /* Bit 16: Enhancements To Scheduling Traffic Feature */ #define EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17) /* Bits 17-20: Depth Of Gate Control List */ #define EMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0x7 << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) -#define EMAC_MAC_HW_FEATURE3_ESTDEP(n) ((n << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK) +#define EMAC_MAC_HW_FEATURE3_ESTDEP(n) (((n) << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK) #define EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20) /* Bits 20-22: Estimated Time Interval Width */ #define EMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) -#define EMAC_MAC_HW_FEATURE3_ESTWID(n) ((n << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK) +#define EMAC_MAC_HW_FEATURE3_ESTWID(n) (((n) << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK) #define EMAC_MAC_HW_FEATURE3_FPESEL (1 << 26) /* Bit 26: Frame Preemption Feature */ #define EMAC_MAC_HW_FEATURE3_TBSSEL (1 << 27) /* Bit 27: Time-Based Scheduling Feature */ #define EMAC_MAC_HW_FEATURE3_ASP_SHIFT (28) /* Bits 28-30: Automotive Safety Package */ #define EMAC_MAC_HW_FEATURE3_ASP_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) -#define EMAC_MAC_HW_FEATURE3_ASP(n) ((n << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) & EMAC_MAC_HW_FEATURE3_ASP_MASK) +#define EMAC_MAC_HW_FEATURE3_ASP(n) (((n) << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) & EMAC_MAC_HW_FEATURE3_ASP_MASK) /* MAC DPP FSM Interrupt Status (MAC_DPP_FSM_INTERRUPT_STATUS) */ #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES (1 << 2) /* Bit 2: Read Descriptor Parity Checker Error Status */ @@ -1053,18 +1053,18 @@ /* MAC FSM ACT Timer (MAC_FSM_ACT_TIMER) */ #define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0) /* Bits 0-10: CSR Clocks For 1 us Tic */ #define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FF << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) -#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) ((n << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK) +#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK) #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16) /* Bits 16-20: Normal Mode Timeout Value */ #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) -#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK) +#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK) #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20) /* Bits 20-24: Large Mode Timeout Value */ #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) -#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK) +#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK) /* SCS_REG 1 (SCS_REG1) */ #define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0) /* Bits 0-32: MAC SCS 1 */ #define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFF << EMAC_SCS_REG1_MAC_SCS1_SHIFT) -#define EMAC_SCS_REG1_MAC_SCS1(n) ((n << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK) +#define EMAC_SCS_REG1_MAC_SCS1(n) (((n) << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK) /* MAC MDIO Address (MAC_MDIO_ADDRESS) */ #define EMAC_MAC_MDIO_ADDRESS_GB (1 << 0) /* Bit 0: GMII Busy */ @@ -1074,26 +1074,26 @@ #define EMAC_MAC_MDIO_ADDRESS_SKAP (1 << 4) /* Bit 4: Skip Address Packet */ #define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8) /* Bits 8-12: CSR Clock Range */ #define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) -#define EMAC_MAC_MDIO_ADDRESS_CR(n) ((n << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK) +#define EMAC_MAC_MDIO_ADDRESS_CR(n) (((n) << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK) #define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12) /* Bits 12-15: Number Of Trailing Clocks */ #define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7 << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) -#define EMAC_MAC_MDIO_ADDRESS_NTC(n) ((n << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK) +#define EMAC_MAC_MDIO_ADDRESS_NTC(n) (((n) << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK) #define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16) /* Bits 16-21: Register Or Device Address */ #define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) -#define EMAC_MAC_MDIO_ADDRESS_RDA(n) ((n << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK) +#define EMAC_MAC_MDIO_ADDRESS_RDA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK) #define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21) /* Bits 21-26: Physical Layer Address */ #define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) -#define EMAC_MAC_MDIO_ADDRESS_PA(n) ((n << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK) +#define EMAC_MAC_MDIO_ADDRESS_PA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK) #define EMAC_MAC_MDIO_ADDRESS_BTB (1 << 26) /* Bit 26: Back-To-Back Transactions */ #define EMAC_MAC_MDIO_ADDRESS_PSE (1 << 27) /* Bit 27: Preamble Suppression Enable */ /* MAC MDIO Data (MAC_MDIO_DATA) */ #define EMAC_MAC_MDIO_DATA_GD_SHIFT (0) /* Bits 0-16: GMII Data */ #define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_GD_SHIFT) -#define EMAC_MAC_MDIO_DATA_GD(n) ((n << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK) +#define EMAC_MAC_MDIO_DATA_GD(n) (((n) << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK) #define EMAC_MAC_MDIO_DATA_RA_SHIFT (16) /* Bits 16-32: Register Address */ #define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_RA_SHIFT) -#define EMAC_MAC_MDIO_DATA_RA(n) ((n << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK) +#define EMAC_MAC_MDIO_DATA_RA(n) (((n) << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK) /* MAC CSR Software Control (MAC_CSR_SW_CTRL) */ #define EMAC_MAC_CSR_SW_CTRL_RCWE (1 << 0) /* Bit 0: Enable Register Write 1 To Clear (W1C) */ @@ -1112,62 +1112,62 @@ /* MAC Presentation Time (MAC_PRESN_TIME_NS) */ #define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time (In Nanoseconds) */ #define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) -#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) ((n << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK) +#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) (((n) << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK) /* MAC Presentation Time Update (MAC_PRESN_TIME_UPDT) */ #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time Update */ #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) -#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) ((n << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK) +#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) (((n) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK) /* MAC Address 0 High (MAC_ADDRESS0_HIGH) */ #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 0 [47:32] */ #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) -#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK) +#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) -#define EMAC_MAC_ADDRESS0_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK) +#define EMAC_MAC_ADDRESS0_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK) #define EMAC_MAC_ADDRESS0_HIGH_AE (1 << 31) /* Bit 31: Address Enable */ /* MAC Address 0 Low (MAC_ADDRESS0_LOW) */ #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 0 [31:0] */ #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) -#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK) +#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK) /* MAC Address 1 High (MAC_ADDRESS1_HIGH) */ #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */ #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) -#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK) +#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) -#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK) +#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK) #define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */ #define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) -#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK) +#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK) #define EMAC_MAC_ADDRESS1_HIGH_SA (1 << 30) /* Bit 30: Source Address */ #define EMAC_MAC_ADDRESS1_HIGH_AE (1 << 31) /* Bit 31: Address Enable */ /* MAC Address 1 Low (MAC_ADDRESS1_LOW) */ #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */ #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) -#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK) +#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK) /* MAC Address 2 High (MAC_ADDRESS2_HIGH) */ #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */ #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) -#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK) +#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK) #define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */ #define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) -#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK) +#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK) #define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */ #define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) -#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK) +#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK) #define EMAC_MAC_ADDRESS2_HIGH_SA (1 << 30) /* Bit 30: Source Address */ #define EMAC_MAC_ADDRESS2_HIGH_AE (1 << 31) /* Bit 31: Address Enable */ /* MAC Address 2 Low (MAC_ADDRESS2_LOW) */ #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */ #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) -#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK) +#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK) /* MMC Control (MMC_CONTROL) */ #define EMAC_MMC_CONTROL_CNTRST (1 << 0) /* Bit 0: Counters Reset */ @@ -1293,27 +1293,27 @@ /* Transmit Octet Count Good Bad (TX_OCTET_COUNT_GOOD_BAD) */ #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good Bad */ #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) -#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) +#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) /* Transmit Packet Count Good Bad (TX_PACKET_COUNT_GOOD_BAD) */ #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good Bad */ #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) -#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) +#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) /* Transmit Broadcast Packets Good (TX_BROADCAST_PACKETS_GOOD) */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) -#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) +#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) /* Transmit Multicast Packets Good (TX_MULTICAST_PACKETS_GOOD) */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) -#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) +#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) /* Transmit 64-Octet Packets Good Bad (TX_64OCTETS_PACKETS_GOOD_BAD) */ #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0) /* Bits 0-32: Transmit 64-Octet Packets Good Bad */ #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFF << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) -#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) ((n << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) +#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) (((n) << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) /* Transmit 65 To 127 Octet Packets Good Bad * (TX_65TO127OCTETS_PACKETS_GOOD_BAD) @@ -1321,7 +1321,7 @@ #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0) /* Bits 0-32: Transmit 65 To 127 Octet Packets Good Bad */ #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) -#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) ((n << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) +#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) (((n) << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) /* Transmit 128 To 255 Octet Packets Good Bad * (TX_128TO255OCTETS_PACKETS_GOOD_BAD) @@ -1329,7 +1329,7 @@ #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0) /* Bits 0-32: Transmit 128 To 255 Octet Packets Good Bad */ #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) -#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) ((n << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) +#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) (((n) << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) /* Transmit 256 To 511 Octet Packets Good Bad * (TX_256TO511OCTETS_PACKETS_GOOD_BAD) @@ -1337,7 +1337,7 @@ #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0) /* Bits 0-32: Transmit 256 To 511 Octet Packets Good Bad */ #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) -#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) ((n << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) +#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) (((n) << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) /* Transmit 512 To 1023 Octet Packets Good Bad * (TX_512TO1023OCTETS_PACKETS_GOOD_BAD) @@ -1345,7 +1345,7 @@ #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Transmit 512 To 1023 Octet Packets Good Bad */ #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) -#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) ((n << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) +#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) (((n) << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) /* Transmit 1024 To Max Octet Packets Good Bad * (TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD) @@ -1353,7 +1353,7 @@ #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Transmit 1024 To Max Octet Packets Good Bad */ #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) -#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) ((n << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) +#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) (((n) << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) /* Transmit Unicast Packets Good Bad * (TX_UNICAST_PACKETS_GOOD_BAD) @@ -1361,22 +1361,22 @@ #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0) /* Bits 0-32: Transmit Unicast Packets Good Bad */ #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFF << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) -#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) ((n << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) +#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) (((n) << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) /* Transmit Multicast Packets Good Bad (TX_MULTICAST_PACKETS_GOOD_BAD) */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good Bad */ #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) -#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) +#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) /* Transmit Broadcast Packets Good Bad (TX_BROADCAST_PACKETS_GOOD_BAD) */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good Bad */ #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) -#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) +#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) /* Transmit Underflow Error Packets (TX_UNDERFLOW_ERROR_PACKETS) */ #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0) /* Bits 0-32: Transmit Underflow Error Packets */ #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFF << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) -#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) ((n << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) +#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) (((n) << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) /* Transmit Single Collision Good Packets * (TX_SINGLE_COLLISION_GOOD_PACKETS) @@ -1384,7 +1384,7 @@ #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0) /* Bits 0-32: Transmit Single Collision Good Packets */ #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFF << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) -#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) ((n << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) +#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) (((n) << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) /* Transmit Multiple Collision Good Packets * (TX_MULTIPLE_COLLISION_GOOD_PACKETS) @@ -1392,117 +1392,117 @@ #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0) /* Bits 0-32: Transmit Multiple Collision Good Packets */ #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFF << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) -#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) ((n << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) +#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) (((n) << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) /* Transmit Deferred Packets (TX_DEFERRED_PACKETS) */ #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0) /* Bits 0-32: Transmit Deferred Packets */ #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFF << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) -#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) ((n << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) +#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) (((n) << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) /* Transmit Late Collision Packets (TX_LATE_COLLISION_PACKETS) */ #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0) /* Bits 0-32: Transmit Late Collision Packets */ #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFF << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) -#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) ((n << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) +#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) (((n) << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) /* Transmit Excessive Collision Packets (TX_EXCESSIVE_COLLISION_PACKETS) */ #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0) /* Bits 0-32: Transmit Excessive Collision Packets */ #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) -#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) ((n << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) +#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) (((n) << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) /* Transmit Carrier Error Packets (TX_CARRIER_ERROR_PACKETS) */ #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0) /* Bits 0-32: Transmit Carrier Error Packets */ #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFF << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) -#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) ((n << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) +#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) (((n) << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) /* Transmit Octet Count Good (TX_OCTET_COUNT_GOOD) */ #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good */ #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) -#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) +#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) /* Transmit Packet Count Good (TX_PACKET_COUNT_GOOD) */ #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good */ #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) -#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) +#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) /* Transmit Excessive Deferral Error (TX_EXCESSIVE_DEFERRAL_ERROR) */ #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0) /* Bits 0-32: Transmit Excessive Deferral Error */ #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) -#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) ((n << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) +#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) (((n) << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) /* Transmit Pause Packets (TX_PAUSE_PACKETS) */ #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0) /* Bits 0-32: Transmit Pause Packets */ #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFF << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) -#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) ((n << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) +#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) (((n) << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) /* Transmit VLAN Packets Good (TX_VLAN_PACKETS_GOOD) */ #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0) /* Bits 0-32: Transmit VLAN Packets Good */ #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFF << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) -#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) ((n << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) +#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) (((n) << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) /* Transmit O Size Packets Good (TX_OSIZE_PACKETS_GOOD) */ #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0) /* Bits 0-32: Transmit O Size Packets Good */ #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFF << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) -#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) ((n << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) +#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) (((n) << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) /* Receive Packets Count Good Bad (RX_PACKETS_COUNT_GOOD_BAD) */ #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0) /* Bits 0-32: Receive Packets Count Good Bad */ #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFF << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) -#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) ((n << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) +#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) (((n) << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) /* Receive Octet Count Good Bad (RX_OCTET_COUNT_GOOD_BAD) */ #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0) /* Bits 0-32: Receive Octet Count Good Bad */ #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) -#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) +#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) /* Receive Octet Count Good (RX_OCTET_COUNT_GOOD) */ #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0) /* Bits 0-32: Receive Octet Count Good */ #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) -#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) +#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) /* Receive Broadcast Packets Good (RX_BROADCAST_PACKETS_GOOD) */ #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0) /* Bits 0-32: Receive Broadcast Packets Good */ #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFF << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) -#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) ((n << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) +#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) (((n) << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) /* Receive Multicast Packets Good (RX_MULTICAST_PACKETS_GOOD) */ #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0) /* Bits 0-32: Receive Multicast Packets Good */ #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFF << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) -#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) ((n << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) +#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) (((n) << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) /* Receive CRC Error Packets (RX_CRC_ERROR_PACKETS) */ #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0) /* Bits 0-32: Receive CRC Error Packets */ #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFF << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) -#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) ((n << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) +#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) (((n) << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) /* Receive Alignment Error Packets (RX_ALIGNMENT_ERROR_PACKETS) */ #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0) /* Bits 0-32: Receive Alignment Error Packets */ #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFF << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) -#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) ((n << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) +#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) (((n) << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) /* Receive Runt Error Packets (RX_RUNT_ERROR_PACKETS) */ #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0) /* Bits 0-32: Receive Runt Error Packets */ #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFF << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) -#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) ((n << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) +#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) (((n) << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) /* Receive Jabber Error Packets (RX_JABBER_ERROR_PACKETS) */ #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0) /* Bits 0-32: Receive Jabber Error Packets */ #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFF << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) -#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) ((n << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) +#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) (((n) << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) /* Receive Undersize Packets Good (RX_UNDERSIZE_PACKETS_GOOD) */ #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0) /* Bits 0-32: Receive Undersize Packets Good */ #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFF << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) -#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) ((n << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) +#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) (((n) << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) /* Receive Oversize Packets Good (RX_OVERSIZE_PACKETS_GOOD) */ #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0) /* Bits 0-32: Receive Oversize Packets Good */ #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFF << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) -#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) ((n << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) +#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) (((n) << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) /* Receive 64 Octets Packets Good Bad (RX_64OCTETS_PACKETS_GOOD_BAD) */ #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0) /* Bits 0-32: Receive 64 Octets Packets Good Bad */ #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFF << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) -#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) ((n << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) +#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) (((n) << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) /* Receive 65-127 Octets Packets Good Bad * (RX_65TO127OCTETS_PACKETS_GOOD_BAD) @@ -1510,7 +1510,7 @@ #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0) /* Bits 0-32: Receive 65-127 Octets Packets Good Bad */ #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) -#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) ((n << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) +#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) (((n) << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) /* Receive 128-255 Octets Packets Good Bad * (RX_128TO255OCTETS_PACKETS_GOOD_BAD) @@ -1518,7 +1518,7 @@ #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0) /* Bits 0-32: Receive 128-255 Octets Packets Good Bad */ #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) -#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) ((n << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) +#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) (((n) << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) /* Receive 256-511 Octets Packets Good Bad * (RX_256TO511OCTETS_PACKETS_GOOD_BAD) @@ -1526,7 +1526,7 @@ #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0) /* Bits 0-32: Receive 256-511 Octets Packets Good Bad */ #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) -#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) ((n << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) +#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) (((n) << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) /* Receive 512-1023 Octets Packets Good Bad * (RX_512TO1023OCTETS_PACKETS_GOOD_BAD) @@ -1534,7 +1534,7 @@ #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Receive 512-1023 Octets Packets Good Bad */ #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) -#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) ((n << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) +#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) (((n) << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) /* Receive 1024 To Max Octets Good Bad * (RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD) @@ -1542,52 +1542,52 @@ #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Receive 1024-Max Octets Good Bad */ #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) -#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) ((n << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) +#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) (((n) << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) /* Receive Unicast Packets Good (RX_UNICAST_PACKETS_GOOD) */ #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0) /* Bits 0-32: Receive Unicast Packets Good */ #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFF << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) -#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) ((n << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) +#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) (((n) << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) /* Receive Length Error Packets (RX_LENGTH_ERROR_PACKETS) */ #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0) /* Bits 0-32: Receive Length Error Packets */ #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFF << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) -#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) ((n << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) +#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) (((n) << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) /* Receive Out of Range Type Packet (RX_OUT_OF_RANGE_TYPE_PACKETS) */ #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0) /* Bits 0-32: Receive Out of Range Type Packet */ #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFF << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) -#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) ((n << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) +#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) (((n) << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) /* Receive Pause Packets (RX_PAUSE_PACKETS) */ #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0) /* Bits 0-32: Receive Pause Packets */ #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFF << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) -#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) ((n << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) +#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) (((n) << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) /* Receive FIFO Overflow Packets (RX_FIFO_OVERFLOW_PACKETS) */ #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0) /* Bits 0-32: Receive FIFO Overflow Packets */ #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFF << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) -#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) ((n << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) +#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) (((n) << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) /* Receive VLAN Packets Good Bad (RX_VLAN_PACKETS_GOOD_BAD) */ #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0) /* Bits 0-32: Receive VLAN Packets Good Bad */ #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFF << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) -#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) ((n << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) +#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) (((n) << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) /* Receive Watchdog Error Packets (RX_WATCHDOG_ERROR_PACKETS) */ #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0) /* Bits 0-32: Receive Watchdog Error Packets */ #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFF << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) -#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) ((n << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) +#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) (((n) << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) /* Receive Receive Error Packets (RX_RECEIVE_ERROR_PACKETS) */ #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0) /* Bits 0-32: Receive Receive Error Packets */ #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFF << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) -#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) ((n << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) +#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) (((n) << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) /* Receive Control Packets Good (RX_CONTROL_PACKETS_GOOD) */ #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0) /* Bits 0-32: Receive Control Packets Good */ #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFF << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) -#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) ((n << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) +#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) (((n) << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) /* MMC Transmit FPE Fragment Counter Interrupt Status * (MMC_FPE_TX_INTERRUPT) @@ -1603,12 +1603,12 @@ /* Transmit FPE Fragment Counter (MMC_TX_FPE_FRAGMENT_CNTR) */ #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0) /* Bits 0-32: Transmit FPE Fragment Counter */ #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFF << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) -#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) ((n << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) +#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) (((n) << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) /* Transmit Hold Request Counter (MMC_TX_HOLD_REQ_CNTR) */ #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0) /* Bits 0-32: Transmit Hold Request Counter */ #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFF << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) -#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) ((n << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) +#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) (((n) << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) /* MMC Receive Packet Assembly Error Counter Interrupt Status * (MMC_FPE_RX_INTERRUPT) @@ -1631,22 +1631,22 @@ #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0) /* Bits 0-32: Packet Assembly Error Counter */ #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) -#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) ((n << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) +#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) /* MMC Receive Packet SMD Error Counter (MMC_RX_PACKET_SMD_ERR_CNTR) */ #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0) /* Bits 0-32: Packet SMD Error Counter */ #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) -#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) ((n << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) +#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) (((n) << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) /* MMC Receive Packet Assembly OK Counter (MMC_RX_PACKET_ASSEMBLY_OK_CNTR) */ #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0) /* Bits 0-32: Packet Assembly OK Counter */ #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) -#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) ((n << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) +#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) /* MMC Receive FPE Fragment Counter (MMC_RX_FPE_FRAGMENT_CNTR) */ #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0) /* Bits 0-32: FPE Fragment Counter */ #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFF << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) -#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) ((n << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) +#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) (((n) << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) /* MAC Layer 3 Layer 4 Control 0 (MAC_L3_L4_CONTROL0) */ #define EMAC_MAC_L3_L4_CONTROL0_L3PEN0 (1 << 0) /* Bit 0: Layer 3 Protocol Enable */ @@ -1656,10 +1656,10 @@ #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match */ #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) ((n << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) +#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match */ #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) ((n << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) +#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0 (1 << 16) /* Bit 16: Layer 4 Protocol Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable */ #define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable */ @@ -1671,30 +1671,30 @@ /* MAC Layer 4 Address 0 (MAC_LAYER4_ADDRESS0) */ #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number */ #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) ((n << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK) +#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK) #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number */ #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) ((n << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK) +#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK) /* MAC Layer 3 Address 0 Reg 0 (MAC_LAYER3_ADDR0_REG0) */ #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) -#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) +#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) /* MAC Layer 3 Address 1 Reg 0 (MAC_LAYER3_ADDR1_REG0) */ #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) -#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) +#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) /* MAC Layer 3 Address 2 Reg 0 (MAC_LAYER3_ADDR2_REG0) */ #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) -#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) +#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) /* MAC Layer 3 Address 3 Reg 0 (MAC_LAYER3_ADDR3_REG0) */ #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) -#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) +#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) /* MAC L3 L4 Control 1 (MAC_L3_L4_CONTROL1) */ #define EMAC_MAC_L3_L4_CONTROL1_L3PEN1 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 1 */ @@ -1704,10 +1704,10 @@ #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) ((n << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) +#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) ((n << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) +#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 1 */ #define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 1 */ @@ -1719,30 +1719,30 @@ /* MAC Layer 4 Address 1 (MAC_LAYER4_ADDRESS1) */ #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 1 */ #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) ((n << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK) +#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK) #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 1 */ #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) ((n << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK) +#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK) /* MAC Layer 3 Address 0 Reg 1 (MAC_LAYER3_ADDR0_REG1) */ #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) -#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) +#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) /* MAC Layer 3 Address 1 Reg 1 (MAC_LAYER3_ADDR1_REG1) */ #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) -#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) +#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) /* MAC Layer 3 Address 2 Reg 1 (MAC_LAYER3_ADDR2_REG1) */ #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) -#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) +#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) /* MAC Layer 3 Address 3 Reg 1 (MAC_LAYER3_ADDR3_REG1) */ #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) -#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) +#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) /* MAC L3 L4 Control 2 (MAC_L3_L4_CONTROL2) */ #define EMAC_MAC_L3_L4_CONTROL2_L3PEN2 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 2 */ @@ -1752,10 +1752,10 @@ #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) ((n << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) +#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) ((n << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) +#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 2 */ #define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 2 */ @@ -1767,30 +1767,30 @@ /* MAC Layer 4 Address 2 (MAC_LAYER4_ADDRESS2) */ #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 2 */ #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) ((n << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK) +#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK) #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 2 */ #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) ((n << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK) +#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK) /* MAC Layer 3 Address 0 Reg 2 (MAC_LAYER3_ADDR0_REG2) */ #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) -#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) +#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) /* MAC Layer 3 Address 1 Reg 2 (MAC_LAYER3_ADDR1_REG2) */ #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) -#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) +#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) /* MAC Layer 3 Address 2 Reg 2 (MAC_LAYER3_ADDR2_REG2) */ #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) -#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) +#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) /* MAC Layer 3 Address 3 Reg 2 (MAC_LAYER3_ADDR3_REG2) */ #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) -#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) +#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) /* MAC L3 L4 Control 3 (MAC_L3_L4_CONTROL3) */ #define EMAC_MAC_L3_L4_CONTROL3_L3PEN3 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 3 */ @@ -1800,10 +1800,10 @@ #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) ((n << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) +#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) -#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) ((n << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) +#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 3 */ #define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 3 */ @@ -1815,30 +1815,30 @@ /* MAC Layer 4 Address 3 (MAC_LAYER4_ADDRESS3) */ #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 3 */ #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) ((n << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK) +#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK) #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 3 */ #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) -#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) ((n << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK) +#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK) /* MAC Layer 3 Address 0 Reg 3 (MAC_LAYER3_ADDR0_REG3) */ #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */ #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) -#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) +#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) /* MAC Layer 3 Address 1 Reg 3 (MAC_LAYER3_ADDR1_REG3) */ #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */ #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) -#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) +#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) /* MAC Layer 3 Address 2 Reg 3 (MAC_LAYER3_ADDR2_REG3) */ #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */ #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) -#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) +#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) /* MAC Layer 3 Address 3 Reg 3 (MAC_LAYER3_ADDR3_REG3) */ #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */ #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) -#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) +#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) /* MAC Timestamp Control (MAC_TIMESTAMP_CONTROL) */ #define EMAC_MAC_TIMESTAMP_CONTROL_TSENA (1 << 0) /* Bit 0: Timestamp Enable */ @@ -1857,7 +1857,7 @@ #define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA (1 << 15) /* Bit 15: Enable Snapshot For Messages Relevant To Master */ #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16) /* Bits 16-18: Select PTP Packets For Taking Snapshots */ #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x3 << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) -#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(n) ((n << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) & EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) +#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(n) (((n) << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) & EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) #define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR (1 << 18) /* Bit 18: Enable MAC Address For PTP Packet Filtering */ #define EMAC_MAC_TIMESTAMP_CONTROL_ESTI (1 << 20) /* Bit 20: External System Time Input */ #define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM (1 << 24) /* Bit 24: Transmit Timestamp Status Mode */ @@ -1866,36 +1866,36 @@ /* MAC Sub Second Increment (MAC_SUB_SECOND_INCREMENT) */ #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8) /* Bits 8-16: Sub-Nanosecond Increment Value */ #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) -#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) ((n << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) +#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16) /* Bits 16-24: Sub-Second Increment Value */ #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) -#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) ((n << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) +#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) /* MAC System Time In Seconds (MAC_SYSTEM_TIME_SECONDS) */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0) /* Bits 0-32: Timestamp Second */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) -#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) ((n << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) +#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) /* MAC System Time In Nanoseconds (MAC_SYSTEM_TIME_NANOSECONDS) */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Sub Seconds */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) -#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) ((n << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) +#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) /* MAC System Time Seconds Update (MAC_SYSTEM_TIME_SECONDS_UPDATE) */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0) /* Bits 0-32: Timestamp Seconds */ #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) -#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) ((n << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) +#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) /* MAC System Time Nanoseconds Update (MAC_SYSTEM_TIME_NANOSECONDS_UPDATE) */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Subseconds */ #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) -#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) ((n << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) +#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB (1 << 31) /* Bit 31: Add Or Subtract Time */ /* MAC Timestamp Addend (MAC_TIMESTAMP_ADDEND) */ #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0) /* Bits 0-32: Timestamp Addend Register */ #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) -#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) ((n << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK) +#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) (((n) << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK) /* MAC System Time Higher Word In Seconds * (MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS) @@ -1903,7 +1903,7 @@ #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0) /* Bits 0-16: Timestamp Higher Word Register */ #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFF << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) -#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) ((n << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) +#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) (((n) << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) /* MAC Timestamp Status (MAC_TIMESTAMP_STATUS) */ #define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF (1 << 0) /* Bit 0: Timestamp Seconds Overflow */ @@ -1923,7 +1923,7 @@ #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0) /* Bits 0-31: Transmit Timestamp Status Low */ #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) -#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) ((n << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) +#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS (1 << 31) /* Bit 31: Transmit Timestamp Status Missed */ /* MAC Transmit Timestamp Status In Seconds @@ -1932,7 +1932,7 @@ #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0) /* Bits 0-32: Transmit Timestamp Status High */ #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) -#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) ((n << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) +#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) /* MAC Timestamp Ingress Asymmetry Correction * (MAC_TIMESTAMP_INGRESS_ASYM_CORR) @@ -1940,7 +1940,7 @@ #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Ingress Asymmetry Correction */ #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) -#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) +#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) /* MAC Timestamp Egress Asymmetry Correction * (MAC_TIMESTAMP_EGRESS_ASYM_CORR) @@ -1948,7 +1948,7 @@ #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Egress Asymmetry Correction */ #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) -#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) +#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) /* MAC Timestamp Ingress Correction In Nanoseconds * (MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND) @@ -1956,7 +1956,7 @@ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0) /* Bits 0-32: Timestamp Ingress Correction */ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) -#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) +#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) /* MAC Timestamp Egress Correction In Nanoseconds * (MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND) @@ -1964,7 +1964,7 @@ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0) /* Bits 0-32: Timestamp Egress Correction */ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) -#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) +#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) /* MAC Timestamp Ingress Correction In Subnanoseconds * (MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC) @@ -1972,7 +1972,7 @@ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8) /* Bits 8-16: Timestamp Ingress Correction In Sub-Nanoseconds */ #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) +#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) /* MAC Timestamp Engress Correction In Subnanoseconds * (MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC) @@ -1980,145 +1980,145 @@ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8) /* Bits 8-16: Timestamp Egress Correction In Sub-Nanoseconds */ #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) +#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) /* MAC Timestamp Ingress Latency (MAC_TIMESTAMP_INGRESS_LATENCY) */ #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8) /* Bits 8-16: Ingress Timestamp Latency In Nanoseconds */ #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) +#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16) /* Bits 16-28: Ingress Timestamp Latency In Sub-Nanoseconds */ #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) +#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) /* MAC Timestamp Egress Latecy (MAC_TIMESTAMP_EGRESS_LATENCY) */ #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8) /* Bits 8-16: Egress Timestamp Latency In Sub-Nanoseconds */ #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) +#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16) /* Bits 16-28: Egress Timestamp Latency In Nanoseconds */ #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) -#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) +#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) /* MAC PPS Control (MAC_PPS_CONTROL) */ #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0) /* Bits 0-4: PPS Output Frequency Control */ #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) -#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) +#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) #define EMAC_MAC_PPS_CONTROL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable 0 */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5) /* Bits 5-7: Target Time Register Mode For PPS0 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) -#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) +#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN0 (1 << 7) /* Bit 7: MCGR Mode Enable For PPS0 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8) /* Bits 8-12: Flexible PPS1 Output Control */ #define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) -#define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK) +#define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13) /* Bits 13-15: Target Time Register Mode For PPS1 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) -#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) +#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN1 (1 << 15) /* Bit 15: MCGR Mode Enable For PPS1 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16) /* Bits 16-20: Flexible PPS2 Output Control */ #define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) -#define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK) +#define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21) /* Bits 21-23: Target Time Register Mode For PPS2 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) -#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) +#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN2 (1 << 23) /* Bit 23: MCGR Mode Enable For PPS2 Output */ #define EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24) /* Bits 24-28: Flexible PPS3 Output Control */ #define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) -#define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK) +#define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK) #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29) /* Bits 29-31: Target Time Register Mode For PPS3 Output */ #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) -#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) +#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) #define EMAC_MAC_PPS_CONTROL_MCGREN3 (1 << 31) /* Bit 31: MCGR Mode Enable For PPS3 Output */ /* MAC PPS0 Target Time In Seconds (MAC_PPS0_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds Register */ #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) -#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) ((n << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) +#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) /* MAC PPS0 Target Time In Nanoseconds (MAC_PPS0_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0) /* Bits 0-31: Target Time Low For PPS0 */ #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) -#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) ((n << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) +#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0 (1 << 31) /* Bit 31: PPS Target Time Busy Status 0 */ /* MAC PPS0 Interval (MAC_PPS0_INTERVAL) */ #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 0 */ #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) -#define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) ((n << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK) +#define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) (((n) << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK) /* MAC PPS0 Width (MAC_PPS0_WIDTH) */ #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 0 */ #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) -#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) ((n << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) +#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) (((n) << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) /* MAC PPS1 Target Time In Seconds (MAC_PPS1_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 1 */ #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) -#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) ((n << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) +#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) /* MAC PPS1 Target Time In Nanoseconds (MAC_PPS1_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0) /* Bits 0-31: Target Time Low For PPS1 */ #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) -#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) ((n << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) +#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1 (1 << 31) /* Bit 31: PPS Target Time Busy Status 1 */ /* MAC PPS1 Interval (MAC_PPS1_INTERVAL) */ #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 1 */ #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) -#define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) ((n << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK) +#define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) (((n) << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK) /* MAC PPS1 Width (MAC_PPS1_WIDTH) */ #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 1 */ #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) -#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) ((n << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) +#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) (((n) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) /* MAC PPS2 Taget Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 2 */ #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) -#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) ((n << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) +#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) /* MAC PPS2 Target Time In Nanoseconds (MAC_PPS2_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0) /* Bits 0-31: Target Time Low For PPS2 */ #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) -#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) ((n << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) +#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2 (1 << 31) /* Bit 31: PPS Target Time Busy Status 2 */ /* MAC PPS2 Interval (MAC_PPS2_INTERVAL) */ #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 2 */ #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) -#define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) ((n << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK) +#define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) (((n) << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK) /* MAC PPS2 Width (MAC_PPS2_WIDTH) */ #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 2 */ #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) -#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) ((n << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) +#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) (((n) << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) /* MAC PPS3 Target Time In Seconds (MAC_PPS3_TARGET_TIME_SECONDS) */ #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 3 */ #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) -#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) ((n << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) +#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) /* MAC PPS3 Target Time In Nanoseconds (MAC_PPS3_TARGET_TIME_NANOSECONDS) */ #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0) /* Bits 0-31: Target Time Low For PPS3 */ #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) -#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) ((n << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) +#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3 (1 << 31) /* Bit 31: PPS Target Time Register Busy 3 */ /* MAC PPS3 Interval (MAC_PPS3_INTERVAL) */ #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval */ #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) -#define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) ((n << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK) +#define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) (((n) << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK) /* MAC PPS3 Width (MAC_PPS3_WIDTH) */ #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 3 */ #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) -#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) ((n << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) +#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) (((n) << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) /* MTL Operation Mode (MTL_OPERATION_MODE) */ #define EMAC_MTL_OPERATION_MODE_DTXSTS (1 << 1) /* Bit 1: Drop Transmit Status */ #define EMAC_MTL_OPERATION_MODE_RAA (1 << 2) /* Bit 2: Receive Arbitration Algorithm */ #define EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT (5) /* Bits 5-7: Transmit Scheduling Algorithm */ #define EMAC_MTL_OPERATION_MODE_SCHALG_MASK (0x3 << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT) -#define EMAC_MTL_OPERATION_MODE_SCHALG(n) ((n << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT) & EMAC_MTL_OPERATION_MODE_SCHALG_MASK) +#define EMAC_MTL_OPERATION_MODE_SCHALG(n) (((n) << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT) & EMAC_MTL_OPERATION_MODE_SCHALG_MASK) #define EMAC_MTL_OPERATION_MODE_SCHALG_WRR EMAC_MTL_OPERATION_MODE_SCHALG(0x0) #define EMAC_MTL_OPERATION_MODE_SCHALG_WFQ EMAC_MTL_OPERATION_MODE_SCHALG(0x1) #define EMAC_MTL_OPERATION_MODE_SCHALG_DWRR EMAC_MTL_OPERATION_MODE_SCHALG(0x2) @@ -2132,42 +2132,42 @@ #define EMAC_MTL_DBG_CTL_DBGMOD (1 << 1) /* Bit 1: Debug Mode Access to FIFO */ #define EMAC_MTL_DBG_CTL_BYTEEN_SHIFT (2) /* Bits 2-4: Byte Enables */ #define EMAC_MTL_DBG_CTL_BYTEEN_MASK (0x3 << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT) -#define EMAC_MTL_DBG_CTL_BYTEEN(n) ((n << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT) & EMAC_MTL_DBG_CTL_BYTEEN_MASK) +#define EMAC_MTL_DBG_CTL_BYTEEN(n) (((n) << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT) & EMAC_MTL_DBG_CTL_BYTEEN_MASK) #define EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT (5) /* Bits 5-7: Encoded Packet State */ #define EMAC_MTL_DBG_CTL_PKTSTATE_MASK (0x3 << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) -#define EMAC_MTL_DBG_CTL_PKTSTATE(n) ((n << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) & EMAC_MTL_DBG_CTL_PKTSTATE_MASK) +#define EMAC_MTL_DBG_CTL_PKTSTATE(n) (((n) << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) & EMAC_MTL_DBG_CTL_PKTSTATE_MASK) #define EMAC_MTL_DBG_CTL_RSTALL (1 << 8) /* Bit 8: Reset All Pointers */ #define EMAC_MTL_DBG_CTL_RSTSEL (1 << 9) /* Bit 9: Reset Pointers Of Selected FIFO */ #define EMAC_MTL_DBG_CTL_FIFORDEN (1 << 10) /* Bit 10: FIFO Read Enable */ #define EMAC_MTL_DBG_CTL_FIFOWREN (1 << 11) /* Bit 11: FIFO Write Enable */ #define EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT (12) /* Bits 12-14: FIFO Selected for Access */ #define EMAC_MTL_DBG_CTL_FIFOSEL_MASK (0x3 << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) -#define EMAC_MTL_DBG_CTL_FIFOSEL(n) ((n << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) & EMAC_MTL_DBG_CTL_FIFOSEL_MASK) +#define EMAC_MTL_DBG_CTL_FIFOSEL(n) (((n) << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) & EMAC_MTL_DBG_CTL_FIFOSEL_MASK) #define EMAC_MTL_DBG_CTL_PKTIE (1 << 14) /* Bit 14: Receive Packet Available Interrupt Status Enable */ #define EMAC_MTL_DBG_CTL_STSIE (1 << 15) /* Bit 15: Transmit Status Available Interrupt Status Enable */ #define EMAC_MTL_DBG_CTL_EIEE (1 << 16) /* Bit 16: ECC Inject Error Enable */ #define EMAC_MTL_DBG_CTL_EIEC_SHIFT (17) /* Bits 17-19: ECC Inject Error Control */ #define EMAC_MTL_DBG_CTL_EIEC_MASK (0x3 << EMAC_MTL_DBG_CTL_EIEC_SHIFT) -#define EMAC_MTL_DBG_CTL_EIEC(n) ((n << EMAC_MTL_DBG_CTL_EIEC_SHIFT) & EMAC_MTL_DBG_CTL_EIEC_MASK) +#define EMAC_MTL_DBG_CTL_EIEC(n) (((n) << EMAC_MTL_DBG_CTL_EIEC_SHIFT) & EMAC_MTL_DBG_CTL_EIEC_MASK) /* MTL Debug Status (MTL_DBG_STS) */ #define EMAC_MTL_DBG_STS_FIFOBUSY (1 << 0) /* Bit 0: FIFO Busy */ #define EMAC_MTL_DBG_STS_PKTSTATE_SHIFT (1) /* Bits 1-3: Encoded Packet State */ #define EMAC_MTL_DBG_STS_PKTSTATE_MASK (0x3 << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT) -#define EMAC_MTL_DBG_STS_PKTSTATE(n) ((n << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT) & EMAC_MTL_DBG_STS_PKTSTATE_MASK) +#define EMAC_MTL_DBG_STS_PKTSTATE(n) (((n) << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT) & EMAC_MTL_DBG_STS_PKTSTATE_MASK) #define EMAC_MTL_DBG_STS_BYTEEN_SHIFT (3) /* Bits 3-5: Byte Enables */ #define EMAC_MTL_DBG_STS_BYTEEN_MASK (0x3 << EMAC_MTL_DBG_STS_BYTEEN_SHIFT) -#define EMAC_MTL_DBG_STS_BYTEEN(n) ((n << EMAC_MTL_DBG_STS_BYTEEN_SHIFT) & EMAC_MTL_DBG_STS_BYTEEN_MASK) +#define EMAC_MTL_DBG_STS_BYTEEN(n) (((n) << EMAC_MTL_DBG_STS_BYTEEN_SHIFT) & EMAC_MTL_DBG_STS_BYTEEN_MASK) #define EMAC_MTL_DBG_STS_PKTI (1 << 8) /* Bit 8: Receive Packet Available Interrupt Status */ #define EMAC_MTL_DBG_STS_STSI (1 << 9) /* Bit 9: Transmit Status Available Interrupt Status */ #define EMAC_MTL_DBG_STS_LOCR_SHIFT (15) /* Bits 15-32: Remaining Locations In FIFO */ #define EMAC_MTL_DBG_STS_LOCR_MASK (0x1FFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT) -#define EMAC_MTL_DBG_STS_LOCR(n) ((n << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK) +#define EMAC_MTL_DBG_STS_LOCR(n) (((n) << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK) /* MTL FIFO Debug Data (MTL_FIFO_DEBUG_DATA) */ #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0) /* Bits 0-32: FIFO Debug Data */ #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFF << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) -#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) ((n << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) +#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) (((n) << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) /* MTL Interrupt Status (MTL_INTERRUPT_STATUS) */ #define EMAC_MTL_INTERRUPT_STATUS_Q0IS (1 << 0) /* Bit 0: Queue 0 Interrupt Status */ @@ -2187,10 +2187,10 @@ #define EMAC_MTL_TBS_CTRL_LEOV (1 << 1) /* Bit 1: Launch Expiry Offset Valid */ #define EMAC_MTL_TBS_CTRL_LEGOS_SHIFT (4) /* Bits 4-7: Launch Expiry GSN Offset */ #define EMAC_MTL_TBS_CTRL_LEGOS_MASK (0x7 << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) -#define EMAC_MTL_TBS_CTRL_LEGOS(n) ((n << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK) +#define EMAC_MTL_TBS_CTRL_LEGOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK) #define EMAC_MTL_TBS_CTRL_LEOS_SHIFT (8) /* Bits 8-32: Launch Expiry Offset */ #define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) -#define EMAC_MTL_TBS_CTRL_LEOS(n) ((n << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK) +#define EMAC_MTL_TBS_CTRL_LEOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK) /* MTL EST Control (MTL_EST_CONTROL) */ #define EMAC_MTL_EST_CONTROL_EEST (1 << 0) /* Bit 0: Enable EST */ @@ -2199,16 +2199,16 @@ #define EMAC_MTL_EST_CONTROL_DFBS (1 << 5) /* Bit 5: Drop Frames Causing Scheduling Error */ #define EMAC_MTL_EST_CONTROL_LCSE_SHIFT (6) /* Bits 6-8: Loop Count to Report Scheduling Error */ #define EMAC_MTL_EST_CONTROL_LCSE_MASK (0x3 << EMAC_MTL_EST_CONTROL_LCSE_SHIFT) -#define EMAC_MTL_EST_CONTROL_LCSE(n) ((n << EMAC_MTL_EST_CONTROL_LCSE_SHIFT) & EMAC_MTL_EST_CONTROL_LCSE_MASK) +#define EMAC_MTL_EST_CONTROL_LCSE(n) (((n) << EMAC_MTL_EST_CONTROL_LCSE_SHIFT) & EMAC_MTL_EST_CONTROL_LCSE_MASK) #define EMAC_MTL_EST_CONTROL_TILS_SHIFT (8) /* Bits 8-11: Time Interval Left Shift Amount */ #define EMAC_MTL_EST_CONTROL_TILS_MASK (0x7 << EMAC_MTL_EST_CONTROL_TILS_SHIFT) -#define EMAC_MTL_EST_CONTROL_TILS(n) ((n << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK) +#define EMAC_MTL_EST_CONTROL_TILS(n) (((n) << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK) #define EMAC_MTL_EST_CONTROL_CTOV_SHIFT (12) /* Bits 12-24: Current Time Offset Value */ #define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xFFF << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) -#define EMAC_MTL_EST_CONTROL_CTOV(n) ((n << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK) +#define EMAC_MTL_EST_CONTROL_CTOV(n) (((n) << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK) #define EMAC_MTL_EST_CONTROL_PTOV_SHIFT (24) /* Bits 24-32: PTP Time Offset Value */ #define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xFF << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) -#define EMAC_MTL_EST_CONTROL_PTOV(n) ((n << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK) +#define EMAC_MTL_EST_CONTROL_PTOV(n) (((n) << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK) /* MTL EST Status (MTL_EST_STATUS) */ #define EMAC_MTL_EST_STATUS_SWLC (1 << 0) /* Bit 0: Switch to Software Owned List Complete */ @@ -2217,27 +2217,27 @@ #define EMAC_MTL_EST_STATUS_HLBS (1 << 3) /* Bit 3: Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL */ #define EMAC_MTL_EST_STATUS_CGCE (1 << 4) /* Bit 4: Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting */ #define EMAC_MTL_EST_STATUS_SWOL (1 << 7) /* Bit 7: S/W owned list When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software */ -#define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true */ +#define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + ((n) * New Cycle Time) becomes true */ #define EMAC_MTL_EST_STATUS_BTRL_MASK (0xF << EMAC_MTL_EST_STATUS_BTRL_SHIFT) -#define EMAC_MTL_EST_STATUS_BTRL(n) ((n << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK) +#define EMAC_MTL_EST_STATUS_BTRL(n) (((n) << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK) #define EMAC_MTL_EST_STATUS_CGSN_SHIFT (16) /* Bits 16-20: Current GCL Slot Number Indicates the slot number of the GCL list */ #define EMAC_MTL_EST_STATUS_CGSN_MASK (0xF << EMAC_MTL_EST_STATUS_CGSN_SHIFT) -#define EMAC_MTL_EST_STATUS_CGSN(n) ((n << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK) +#define EMAC_MTL_EST_STATUS_CGSN(n) (((n) << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK) /* MTL EST Scheduling Error (MTL_EST_SCH_ERROR) */ #define EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT (0) /* Bits 0-2: Schedule Error Queue Number */ #define EMAC_MTL_EST_SCH_ERROR_SEQN_MASK (0x3 << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT) -#define EMAC_MTL_EST_SCH_ERROR_SEQN(n) ((n << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT) & EMAC_MTL_EST_SCH_ERROR_SEQN_MASK) +#define EMAC_MTL_EST_SCH_ERROR_SEQN(n) (((n) << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT) & EMAC_MTL_EST_SCH_ERROR_SEQN_MASK) /* MTL EST Frame Size Error (MTL_EST_FRM_SIZE_ERROR) */ #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0) /* Bits 0-2: Frame Size Error Queue Number */ #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x3 << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT) -#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(n) ((n << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT) & EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) +#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(n) (((n) << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT) & EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) /* MTL EST Frame Size Capture (MTL_EST_FRM_SIZE_CAPTURE) */ #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0) /* Bits 0-15: Frame Size of HLBF */ #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) -#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) ((n << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) +#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) (((n) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ (1 << 16) /* Bit 16: Queue Number of HLBF */ /* MTL EST Interrupt Enable (MTL_EST_INTR_ENABLE) */ @@ -2255,43 +2255,43 @@ #define EMAC_MTL_EST_GCL_CONTROL_DBGB (1 << 5) /* Bit 5: Debug Mode Bank Select */ #define EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8) /* Bits 8-16: Gate Control List Address: (GCLA when GCRR is "0") */ #define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xFF << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) -#define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) ((n << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK) +#define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK) #define EMAC_MTL_EST_GCL_CONTROL_ERR0 (1 << 20) /* Bit 20: If this field is 1, it indicates that when the software writes to GCL the last write operation was aborted and when MTL_EST_Control[SSWL] is 1, GCL registers are prohibited */ #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE (1 << 21) /* Bit 21: EST ECC Inject Error Enable */ #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22) /* Bits 22-24: ECC Inject Error Control for EST Memory */ #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0x3 << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT) -#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(n) ((n << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) +#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) /* MTL EST GCL Data (MTL_EST_GCL_DATA) */ #define EMAC_MTL_EST_GCL_DATA_GCD_SHIFT (0) /* Bits 0-32: Gate Control Data */ #define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFF << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) -#define EMAC_MTL_EST_GCL_DATA_GCD(n) ((n << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK) +#define EMAC_MTL_EST_GCL_DATA_GCD(n) (((n) << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK) /* MTL FPE Control Status (MTL_FPE_CTRL_STS) */ #define EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0) /* Bits 0-2: Additional Fragment Size */ #define EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3 << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT) -#define EMAC_MTL_FPE_CTRL_STS_AFSZ(n) ((n << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT) & EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK) +#define EMAC_MTL_FPE_CTRL_STS_AFSZ(n) (((n) << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT) & EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK) #define EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT (8) /* Bits 8-10: Preemption Classification */ #define EMAC_MTL_FPE_CTRL_STS_PEC_MASK (0x3 << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT) -#define EMAC_MTL_FPE_CTRL_STS_PEC(n) ((n << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT) & EMAC_MTL_FPE_CTRL_STS_PEC_MASK) +#define EMAC_MTL_FPE_CTRL_STS_PEC(n) (((n) << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT) & EMAC_MTL_FPE_CTRL_STS_PEC_MASK) #define EMAC_MTL_FPE_CTRL_STS_HRS (1 << 28) /* Bit 28: Hold/Release Status */ /* MTL FPE Advance (MTL_FPE_ADVANCE) */ #define EMAC_MTL_FPE_ADVANCE_HADV_SHIFT (0) /* Bits 0-16: Hold Advance */ #define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) -#define EMAC_MTL_FPE_ADVANCE_HADV(n) ((n << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK) +#define EMAC_MTL_FPE_ADVANCE_HADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK) #define EMAC_MTL_FPE_ADVANCE_RADV_SHIFT (16) /* Bits 16-32: Release Advance */ #define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) -#define EMAC_MTL_FPE_ADVANCE_RADV(n) ((n << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK) +#define EMAC_MTL_FPE_ADVANCE_RADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK) /* MTL Rx Parser Control Status (MTL_RXP_CONTROL_STATUS) */ #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0) /* Bits 0-6: Number Of Valid Entry Address Or Index In The Instruction Table */ #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) -#define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) ((n << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK) +#define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK) #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1 (1 << 15) /* Bit 15: MTL_SCS1 */ #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16) /* Bits 16-22: Number of parsable entries in the Instruction table */ #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) -#define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) ((n << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK) +#define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK) #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI (1 << 31) /* Bit 31: RX Parser in Idle State */ /* MTL Rx Parser Interrupt Control Status @@ -2310,13 +2310,13 @@ /* MTL Rx Parser Drop Count (MTL_RXP_DROP_CNT) */ #define EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0) /* Bits 0-31: Rx Parser Drop Count */ #define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) -#define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) ((n << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK) +#define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) (((n) << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK) #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF (1 << 31) /* Bit 31: Rx Parser Drop Counter Overflow Bit */ /* MTL Rx Parser Error Count (MTL_RXP_ERROR_CNT) */ #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0) /* Bits 0-31: Rx Parser Error Count */ #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) -#define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) ((n << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK) +#define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) (((n) << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK) #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF (1 << 31) /* Bit 31: Rx Parser Error Counter Overflow Bit */ /* MTL Rx Parser Indirect Access Control Status @@ -2325,18 +2325,18 @@ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0) /* Bits 0-8: FRP Instruction Table Offset Address */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xFF << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) -#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) +#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN (1 << 16) /* Bit 16: Read Write Control */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE (1 << 20) /* Bit 20: ECC Inject Error Enable for Rx Parser Memory */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT (21) /* Bits 21-23: ECC Inject Error Control for Rx Parser Memory */ #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK (0x3 << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT) -#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK) +#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK) #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY (1 << 31) /* Bit 31: FRP Instruction Table Access Busy */ /* MTL Rx Parser Indirect Access Data (MTL_RXP_INDIRECT_ACC_DATA) */ #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0) /* Bits 0-32: FRP Instruction Table Write/Read Data */ #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFF << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) -#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) +#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) /* MTL ECC Control (MTL_ECC_CONTROL) */ #define EMAC_MTL_ECC_CONTROL_MTXEE (1 << 0) /* Bit 0: MTL Tx FIFO ECC Enable */ @@ -2373,25 +2373,25 @@ #define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE (1 << 0) /* Bit 0: MTL ECC Error Status Read Enable */ #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT (1) /* Bits 1-4: MTL ECC Memory Selection */ #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK (0x7 << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT) -#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS(n) ((n << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT) & EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK) +#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS(n) (((n) << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT) & EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK) #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES (1 << 4) /* Bit 4: Clear Correctable Error Status */ #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES (1 << 5) /* Bit 5: Clear Uncorrectable Error Status */ /* MTL ECC Error Adress Status (MTL_ECC_ERR_ADDR_STATUS) */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0) /* Bits 0-16: MTL ECC Correctable Error Address Status */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) -#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) ((n << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK) +#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK) #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT (16) /* Bits 16-32: MTL ECC Uncorrectable Error Address Status */ #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) -#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) ((n << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK) +#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK) /* MTL ECC Error Control Status (MTL_ECC_ERR_CNTR_STATUS) */ #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT (0) /* Bits 0-8: MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's correctable error count value */ #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xFF << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) -#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) ((n << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK) +#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK) #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT (16) /* Bits 16-20: MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's uncorrectable error count value */ #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xF << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) -#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) ((n << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK) +#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK) /* MTL DPP Control (MTL_DPP_CONTROL) */ #define EMAC_MTL_DPP_CONTROL_EDPP (1 << 0) /* Bit 0: Enable Data path Parity Protection */ @@ -2409,47 +2409,47 @@ #define EMAC_MTL_TXQ0_OPERATION_MODE_TSF (1 << 1) /* Bit 1: Transmit Store and Forward */ #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT (2) /* Bits 2-4: Transmit Queue Enable */ #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3 << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK) +#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK) #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_DISABLE EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0) #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_AVB EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0x1) #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_DCB_GEN EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0x2) #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4) /* Bits 4-7: Transmit Threshold Control */ #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK) +#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK) #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */ #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) -#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK) +#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK) /* MTL Tx Queue 0 Underflow (MTL_TXQ0_UNDERFLOW) */ #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */ #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) -#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) ((n << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK) +#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK) #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */ /* MTL Tx Queue 0 Debug (MTL_TXQ0_DEBUG) */ #define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED (1 << 0) /* Bit 0: Transmit Queue in Pause */ #define EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1) /* Bits 1-3: MTL Tx Queue Read Controller Status */ #define EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x3 << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) -#define EMAC_MTL_TXQ0_DEBUG_TRCSTS(n) ((n << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK) +#define EMAC_MTL_TXQ0_DEBUG_TRCSTS(n) (((n) << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK) #define EMAC_MTL_TXQ0_DEBUG_TWCSTS (1 << 3) /* Bit 3: MTL Tx Queue Write Controller Status */ #define EMAC_MTL_TXQ0_DEBUG_TXQSTS (1 << 4) /* Bit 4: MTL Tx Queue Not Empty Status */ #define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS (1 << 5) /* Bit 5: MTL Tx Status FIFO Full Status */ #define EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16) /* Bits 16-19: Number of Packets in the Transmit Queue */ #define EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x7 << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) -#define EMAC_MTL_TXQ0_DEBUG_PTXQ(n) ((n << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK) +#define EMAC_MTL_TXQ0_DEBUG_PTXQ(n) (((n) << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK) #define EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20) /* Bits 20-23: Number of Status Words in Tx Status FIFO of Queue */ #define EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x7 << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) -#define EMAC_MTL_TXQ0_DEBUG_STXSTSF(n) ((n << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK) +#define EMAC_MTL_TXQ0_DEBUG_STXSTSF(n) (((n) << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK) /* MTL Tx Queue 0 ETS Status (MTL_TXQ0_ETS_STATUS) */ #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */ #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) -#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) ((n << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK) +#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK) /* MTL Tx Queue Quantum Weight (MTL_TXQ0_QUANTUM_WEIGHT) */ #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: Quantum or Weights */ #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) -#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) ((n << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK) +#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK) /* MTL Queue 0 Interrupt Control Status (MTL_Q0_INTERRUPT_CONTROL_STATUS) */ #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS (1 << 0) /* Bit 0: Transmit Queue Underflow Interrupt Status */ @@ -2462,7 +2462,7 @@ /* MTL Rx Queue 0 Operation Mode (MTL_RXQ0_OPERATION_MODE) */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0) /* Bits 0-2: Receive Queue Threshold Control */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3 << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK) #define EMAC_MTL_RXQ0_OPERATION_MODE_FUP (1 << 3) /* Bit 3: Forward Undersized Good Packets */ #define EMAC_MTL_RXQ0_OPERATION_MODE_FEP (1 << 4) /* Bit 4: Forward Error Packets */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RSF (1 << 5) /* Bit 5: Receive Queue Store and Forward */ @@ -2470,13 +2470,13 @@ #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex) */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK) #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK) #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */ #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) -#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK) +#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK) /* MTL Rx Queue Missed Packet Overflow Count * (MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT) @@ -2484,29 +2484,29 @@ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) ((n << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) +#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */ #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) -#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) ((n << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) +#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */ /* MTL Rx Queue 0 Debug (MTL_RXQ0_DEBUG) */ #define EMAC_MTL_RXQ0_DEBUG_RWCSTS (1 << 0) /* Bit 0: MTL Rx Queue Write Controller Active Status */ #define EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1) /* Bits 1-3: MTL Rx Queue Read Controller State */ #define EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) -#define EMAC_MTL_RXQ0_DEBUG_RRCSTS(n) ((n << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK) +#define EMAC_MTL_RXQ0_DEBUG_RRCSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK) #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4) /* Bits 4-6: MTL Rx Queue Fill-Level Status */ #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) -#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) ((n << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) +#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) #define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */ #define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) -#define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) ((n << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK) +#define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK) /* MTL Rx Queue 0 Control 0 (MTL_RXQ0_CONTROL) */ #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT (0) /* Bits 0-3: Receive Queue Weight */ #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK (0x7 << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT) -#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(n) ((n << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK) +#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(n) (((n) << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK) #define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT (1 << 3) /* Bit 3: Receive Queue Packet Arbitration */ /* MTL Tx Queue 1 Operation Mode (MTL_TXQ1_OPERATION_MODE) */ @@ -2514,66 +2514,66 @@ #define EMAC_MTL_TXQ1_OPERATION_MODE_TSF (1 << 1) /* Bit 1: Transmit Store and Forward */ #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT (2) /* Bits 2-4: Transmit Queue Enable */ #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK (0x3 << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK) +#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK) #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT (4) /* Bits 4-7: Transmit Threshold Control */ #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK) +#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK) #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */ #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) -#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK) +#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK) /* MTL Tx Queue 1 Underflow (MTL_TXQ1_UNDERFLOW) */ #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */ #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) -#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) ((n << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK) +#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK) #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */ /* MTL Tx Queue 1 Debug (MTL_TXQ1_DEBUG) */ #define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED (1 << 0) /* Bit 0: Transmit Queue in Pause */ #define EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT (1) /* Bits 1-3: MTL Tx Queue Read Controller Status */ #define EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK (0x3 << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT) -#define EMAC_MTL_TXQ1_DEBUG_TRCSTS(n) ((n << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK) +#define EMAC_MTL_TXQ1_DEBUG_TRCSTS(n) (((n) << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK) #define EMAC_MTL_TXQ1_DEBUG_TWCSTS (1 << 3) /* Bit 3: MTL Tx Queue Write Controller Status */ #define EMAC_MTL_TXQ1_DEBUG_TXQSTS (1 << 4) /* Bit 4: MTL Tx Queue Not Empty Status */ #define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS (1 << 5) /* Bit 5: MTL Tx Status FIFO Full Status */ #define EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT (16) /* Bits 16-19: Number of Packets in the Transmit Queue */ #define EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK (0x7 << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT) -#define EMAC_MTL_TXQ1_DEBUG_PTXQ(n) ((n << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK) +#define EMAC_MTL_TXQ1_DEBUG_PTXQ(n) (((n) << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK) #define EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT (20) /* Bits 20-23: Number of Status Words in Tx Status FIFO of Queue */ #define EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK (0x7 << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT) -#define EMAC_MTL_TXQ1_DEBUG_STXSTSF(n) ((n << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK) +#define EMAC_MTL_TXQ1_DEBUG_STXSTSF(n) (((n) << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK) /* MTL Tx Queue 1 ETS Control (MTL_TXQ1_ETS_CONTROL) */ #define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG (1 << 2) /* Bit 2: AV Algorithm */ #define EMAC_MTL_TXQ1_ETS_CONTROL_CC (1 << 3) /* Bit 3: Credit Control */ #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT (4) /* Bits 4-7: Slot Count */ #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK (0x7 << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT) -#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(n) ((n << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK) +#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(n) (((n) << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK) /* MTL Tx Queue 1 ETS Status (MTL_TXQ1_ETS_STATUS) */ #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */ #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) -#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) ((n << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK) +#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK) /* MTL Tx Queue 1 Quantum Weight (MTL_TXQ1_QUANTUM_WEIGHT) */ #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: idleSlopeCredit, Quantum or Weights */ #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) -#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) ((n << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK) +#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK) /* MTL Tx Queue 1 Sendslope Credit (MTL_TXQ1_SENDSLOPECREDIT) */ #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0) /* Bits 0-14: sendSlopeCredit Value */ #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFF << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) -#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) ((n << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK) +#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) (((n) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK) /* MTL Tx Queue 1 HiCredit (MTL_TXQ1_HICREDIT) */ #define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0) /* Bits 0-29: hiCredit Value */ #define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) -#define EMAC_MTL_TXQ1_HICREDIT_HC(n) ((n << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK) +#define EMAC_MTL_TXQ1_HICREDIT_HC(n) (((n) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK) /* MTL Tx Queue 1 LoCredit (MTL_TXQ1_LOCREDIT) */ #define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0) /* Bits 0-29: loCredit Value */ #define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) -#define EMAC_MTL_TXQ1_LOCREDIT_LC(n) ((n << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK) +#define EMAC_MTL_TXQ1_LOCREDIT_LC(n) (((n) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK) /* MTL Queue 1 Interrupt Control Status (MTL_Q1_INTERRUPT_CONTROL_STATUS) */ #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS (1 << 0) /* Bit 0: Transmit Queue Underflow Interrupt Status */ @@ -2586,7 +2586,7 @@ /* MTL Rx Queue 1 Operation Mode (MTL_RXQ1_OPERATION_MODE) */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT (0) /* Bits 0-2: Receive Queue Threshold Control */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK (0x3 << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK) #define EMAC_MTL_RXQ1_OPERATION_MODE_FUP (1 << 3) /* Bit 3: Forward Undersized Good Packets */ #define EMAC_MTL_RXQ1_OPERATION_MODE_FEP (1 << 4) /* Bit 4: Forward Error Packets */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RSF (1 << 5) /* Bit 5: Receive Queue Store and Forward */ @@ -2594,13 +2594,13 @@ #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK) #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK) #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */ #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) -#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK) +#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK) /* MTL Rx Queue 1 Missed Packet Overflow Counter * (MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT) @@ -2608,29 +2608,29 @@ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) ((n << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) +#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */ #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) -#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) ((n << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) +#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */ /* MTL Rx Queue 1 Debug (MTL_RXQ1_DEBUG) */ #define EMAC_MTL_RXQ1_DEBUG_RWCSTS (1 << 0) /* Bit 0: MTL Rx Queue Write Controller Active Status */ #define EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT (1) /* Bits 1-3: MTL Rx Queue Read Controller State */ #define EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT) -#define EMAC_MTL_RXQ1_DEBUG_RRCSTS(n) ((n << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK) +#define EMAC_MTL_RXQ1_DEBUG_RRCSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK) #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT (4) /* Bits 4-6: MTL Rx Queue Fill-Level Status */ #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) -#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) ((n << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK) +#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK) #define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */ #define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) -#define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) ((n << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK) +#define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK) /* MTL Rx Queue 1 Control (MTL_RXQ1_CONTROL) */ #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT (0) /* Bits 0-3: Receive Queue Weight */ #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK (0x7 << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT) -#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(n) ((n << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK) +#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(n) (((n) << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK) #define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT (1 << 3) /* Bit 3: Receive Queue Packet Arbitration */ /* DMA Mode (DMA_MODE) */ @@ -2638,15 +2638,15 @@ #define EMAC_DMA_MODE_DA (1 << 1) /* Bit 1: DMA Tx or Rx Arbitration Scheme */ #define EMAC_DMA_MODE_TAA_SHIFT (2) /* Bits 2-5: Transmit Arbitration Algorithm */ #define EMAC_DMA_MODE_TAA_MASK (0x7 << EMAC_DMA_MODE_TAA_SHIFT) -#define EMAC_DMA_MODE_TAA(n) ((n << EMAC_DMA_MODE_TAA_SHIFT) & EMAC_DMA_MODE_TAA_MASK) +#define EMAC_DMA_MODE_TAA(n) (((n) << EMAC_DMA_MODE_TAA_SHIFT) & EMAC_DMA_MODE_TAA_MASK) #define EMAC_DMA_MODE_ARBC (1 << 9) /* Bit 9: Is reserved for NXP internal use */ #define EMAC_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit Priority */ #define EMAC_DMA_MODE_PR_SHIFT (12) /* Bits 12-15: Priority Ratio */ #define EMAC_DMA_MODE_PR_MASK (0x7 << EMAC_DMA_MODE_PR_SHIFT) -#define EMAC_DMA_MODE_PR(n) ((n << EMAC_DMA_MODE_PR_SHIFT) & EMAC_DMA_MODE_PR_MASK) +#define EMAC_DMA_MODE_PR(n) (((n) << EMAC_DMA_MODE_PR_SHIFT) & EMAC_DMA_MODE_PR_MASK) #define EMAC_DMA_MODE_INTM_SHIFT (16) /* Bits 16-18: Interrupt Mode */ #define EMAC_DMA_MODE_INTM_MASK (0x3 << EMAC_DMA_MODE_INTM_SHIFT) -#define EMAC_DMA_MODE_INTM(n) ((n << EMAC_DMA_MODE_INTM_SHIFT) & EMAC_DMA_MODE_INTM_MASK) +#define EMAC_DMA_MODE_INTM(n) (((n) << EMAC_DMA_MODE_INTM_SHIFT) & EMAC_DMA_MODE_INTM_MASK) /* DMA System Bus Mode (DMA_SYSBUS_MODE) */ #define EMAC_DMA_SYSBUS_MODE_FB (1 << 0) /* Bit 0: Fixed Burst Length */ @@ -2664,25 +2664,25 @@ #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS (1 << 0) /* Bit 0: AHB Master Status */ #define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8) /* Bits 8-12: DMA Channel 0 Receive Process State */ #define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) -#define EMAC_DMA_DEBUG_STATUS0_RPS0(n) ((n << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) +#define EMAC_DMA_DEBUG_STATUS0_RPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) #define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12) /* Bits 12-16: DMA Channel 0 Transmit Process State */ #define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) -#define EMAC_DMA_DEBUG_STATUS0_TPS0(n) ((n << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) +#define EMAC_DMA_DEBUG_STATUS0_TPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) #define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16) /* Bits 16-20: DMA Channel 1 Receive Process State */ #define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) -#define EMAC_DMA_DEBUG_STATUS0_RPS1(n) ((n << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) +#define EMAC_DMA_DEBUG_STATUS0_RPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) #define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20) /* Bits 20-24: DMA Channel 1 Transmit Process State */ #define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) -#define EMAC_DMA_DEBUG_STATUS0_TPS1(n) ((n << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) +#define EMAC_DMA_DEBUG_STATUS0_TPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) /* DMA TBS Control (DMA_TBS_CTRL) */ #define EMAC_DMA_TBS_CTRL_FTOV (1 << 0) /* Bit 0: Fetch Time Offset Valid */ #define EMAC_DMA_TBS_CTRL_FGOS_SHIFT (4) /* Bits 4-7: Fetch GSN Offset */ #define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x7 << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) -#define EMAC_DMA_TBS_CTRL_FGOS(n) ((n << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK) +#define EMAC_DMA_TBS_CTRL_FGOS(n) (((n) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK) #define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8) /* Bits 8-32: Fetch Time Offset */ #define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) -#define EMAC_DMA_TBS_CTRL_FTOS(n) ((n << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK) +#define EMAC_DMA_TBS_CTRL_FTOS(n) (((n) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK) /* DMA Safety Interrupt Status (DMA_SAFETY_INTERRUPT_STATUS) */ #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS (1 << 0) /* Bit 0: DMA ECC Correctable Error Interrupt Status */ @@ -2695,17 +2695,17 @@ #define EMAC_DMA_CH0_CONTROL_PBLX8 (1 << 16) /* Bit 16: 8xPBL mode */ #define EMAC_DMA_CH0_CONTROL_DSL_SHIFT (18) /* Bits 18-21: Descriptor Skip Length */ #define EMAC_DMA_CH0_CONTROL_DSL_MASK (0x7 << EMAC_DMA_CH0_CONTROL_DSL_SHIFT) -#define EMAC_DMA_CH0_CONTROL_DSL(n) ((n << EMAC_DMA_CH0_CONTROL_DSL_SHIFT) & EMAC_DMA_CH0_CONTROL_DSL_MASK) +#define EMAC_DMA_CH0_CONTROL_DSL(n) (((n) << EMAC_DMA_CH0_CONTROL_DSL_SHIFT) & EMAC_DMA_CH0_CONTROL_DSL_MASK) /* DMA Channel Tx Control (DMA_CH0_TX_CONTROL) */ #define EMAC_DMA_CH0_TX_CONTROL_ST (1 << 0) /* Bit 0: Start or Stop Transmission Command */ #define EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT (1) /* Bits 1-4: Transmit Channel Weight */ #define EMAC_DMA_CH0_TX_CONTROL_TCW_MASK (0x7 << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) -#define EMAC_DMA_CH0_TX_CONTROL_TCW(n) ((n << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK) +#define EMAC_DMA_CH0_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK) #define EMAC_DMA_CH0_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */ #define EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */ #define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) -#define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) ((n << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK) +#define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK) #define EMAC_DMA_CH0_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */ #define EMAC_DMA_CH0_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */ @@ -2713,45 +2713,45 @@ #define EMAC_DMA_CH0_RX_CONTROL_SR (1 << 0) /* Bit 0: Start or Stop Receive */ #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT (1) /* Bits 1-3: Receive Buffer size Low */ #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK) +#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK) #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */ #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) -#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK) +#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK) #define EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */ #define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) -#define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK) +#define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK) #define EMAC_DMA_CH0_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */ #define EMAC_DMA_CH0_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */ /* DMA Channel 0 Tx Descriptor List Address (DMA_CH0_TXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */ #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) -#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) ((n << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK) +#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK) /* DMA Channel 0 Rx Descriptor List Address (DMA_CH0_RXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */ #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) -#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) ((n << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK) +#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK) /* DMA Channel 0 Tx Descriptor Tail Pointer (DMA_CH0_TXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */ #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) -#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) ((n << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK) +#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK) /* DMA Channeli 0 Rx Descriptor List Pointer (DMA_CH0_RXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */ #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) -#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) ((n << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK) +#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK) /* DMA Channel 0 Tx Descriptor Ring Length (DMA_CH0_TXDESC_RING_LENGTH) */ #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */ #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) -#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) ((n << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK) +#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK) /* DMA Channel 0 Rx Descriptor Ring Length (DMA_CH0_RXDESC_RING_LENGTH) */ #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */ #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) -#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) ((n << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK) +#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK) /* DMA Channel 0 Interrupt Enable (DMA_CH0_INTERRUPT_ENABLE) */ #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE (1 << 0) /* Bit 0: Transmit Interrupt Enable */ @@ -2774,10 +2774,10 @@ #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */ #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) ((n << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) +#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */ #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) -#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) ((n << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) +#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) /* DMA Channel 0 Slot Function Control Status * (DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS) @@ -2787,10 +2787,10 @@ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) ((n << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) +#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */ #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) -#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) ((n << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) +#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) /* DMA Channel 0 Current Application Transmit Descriptor * (DMA_CH0_CURRENT_APP_TXDESC) @@ -2798,7 +2798,7 @@ #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */ #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) -#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) +#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) /* DMA Channel 0 Current Application Receive Descriptor * (DMA_CH0_CURRENT_APP_RXDESC) @@ -2806,7 +2806,7 @@ #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */ #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) -#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) +#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) /* DMA Channel 0 Current Application Transmit Descriptor * (DMA_CH0_CURRENT_APP_TXBUFFER) @@ -2814,7 +2814,7 @@ #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */ #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) -#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) +#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) /* DMA Channel 0 Current Application Receive Buffer * (DMA_CH0_CURRENT_APP_RXBUFFER) @@ -2822,7 +2822,7 @@ #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */ #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) -#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) +#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) /* DMA Channel 0 Status (DMA_CH0_STATUS) */ #define EMAC_DMA_CH0_STATUS_TI (1 << 0) /* Bit 0: Transmit Interrupt */ @@ -2840,43 +2840,43 @@ #define EMAC_DMA_CH0_STATUS_NIS (1 << 15) /* Bit 15: Normal Interrupt Summary */ #define EMAC_DMA_CH0_STATUS_TEB_SHIFT (16) /* Bits 16-19: Tx DMA Error Bits */ #define EMAC_DMA_CH0_STATUS_TEB_MASK (0x7 << EMAC_DMA_CH0_STATUS_TEB_SHIFT) -#define EMAC_DMA_CH0_STATUS_TEB(n) ((n << EMAC_DMA_CH0_STATUS_TEB_SHIFT) & EMAC_DMA_CH0_STATUS_TEB_MASK) +#define EMAC_DMA_CH0_STATUS_TEB(n) (((n) << EMAC_DMA_CH0_STATUS_TEB_SHIFT) & EMAC_DMA_CH0_STATUS_TEB_MASK) #define EMAC_DMA_CH0_STATUS_REB_SHIFT (19) /* Bits 19-22: Rx DMA Error Bits */ #define EMAC_DMA_CH0_STATUS_REB_MASK (0x7 << EMAC_DMA_CH0_STATUS_REB_SHIFT) -#define EMAC_DMA_CH0_STATUS_REB(n) ((n << EMAC_DMA_CH0_STATUS_REB_SHIFT) & EMAC_DMA_CH0_STATUS_REB_MASK) +#define EMAC_DMA_CH0_STATUS_REB(n) (((n) << EMAC_DMA_CH0_STATUS_REB_SHIFT) & EMAC_DMA_CH0_STATUS_REB_MASK) /* DMA Channel 0 Miss Frame Counter (DMA_CH0_MISS_FRAME_CNT) */ #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programing RPF field in DMA_CH${i}_Rx_Control register */ #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) -#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) ((n << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) +#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */ /* DMA Channel 0 Rx Parser Accept Count (DMA_CH0_RXP_ACCEPT_CNT) */ #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */ #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) -#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) ((n << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK) +#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK) #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */ /* DMA Channel 0 Rx ERI Count (DMA_CH0_RX_ERI_CNT) */ #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */ #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) -#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) ((n << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK) +#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK) /* DMA Channel 1 Control (DMA_CH1_CONTROL) */ #define EMAC_DMA_CH1_CONTROL_PBLX8 (1 << 16) /* Bit 16: 8xPBL mode */ #define EMAC_DMA_CH1_CONTROL_DSL_SHIFT (18) /* Bits 18-21: Descriptor Skip Length */ #define EMAC_DMA_CH1_CONTROL_DSL_MASK (0x7 << EMAC_DMA_CH1_CONTROL_DSL_SHIFT) -#define EMAC_DMA_CH1_CONTROL_DSL(n) ((n << EMAC_DMA_CH1_CONTROL_DSL_SHIFT) & EMAC_DMA_CH1_CONTROL_DSL_MASK) +#define EMAC_DMA_CH1_CONTROL_DSL(n) (((n) << EMAC_DMA_CH1_CONTROL_DSL_SHIFT) & EMAC_DMA_CH1_CONTROL_DSL_MASK) /* DMA Channel 1 Tx Control (DMA_CH1_TX_CONTROL) */ #define EMAC_DMA_CH1_TX_CONTROL_ST (1 << 0) /* Bit 0: Start or Stop Transmission Command */ #define EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT (1) /* Bits 1-4: Transmit Channel Weight */ #define EMAC_DMA_CH1_TX_CONTROL_TCW_MASK (0x7 << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) -#define EMAC_DMA_CH1_TX_CONTROL_TCW(n) ((n << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK) +#define EMAC_DMA_CH1_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK) #define EMAC_DMA_CH1_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */ #define EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */ #define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) -#define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) ((n << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK) +#define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK) #define EMAC_DMA_CH1_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */ #define EMAC_DMA_CH1_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */ @@ -2884,45 +2884,45 @@ #define EMAC_DMA_CH1_RX_CONTROL_SR (1 << 0) /* Bit 0: Start or Stop Receive */ #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT (1) /* Bits 1-3: Receive Buffer size Low */ #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK) +#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK) #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */ #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) -#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK) +#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK) #define EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */ #define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) -#define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK) +#define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK) #define EMAC_DMA_CH1_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */ #define EMAC_DMA_CH1_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */ /* DMA Channel 1 Tx Descriptor List Address (DMA_CH1_TXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */ #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) -#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) ((n << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK) +#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK) /* DMA Channel 1 Rx Descriptor List Address (DMA_CH1_RXDESC_LIST_ADDRESS) */ #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */ #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) -#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) ((n << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK) +#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK) /* DMA Channel 1 Tx Descriptor Tail Pointer (DMA_CH1_TXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */ #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) -#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) ((n << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK) +#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK) /* DMA Channel 1 Rx Descriptor Tail Pointer (DMA_CH1_RXDESC_TAIL_POINTER) */ #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */ #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) -#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) ((n << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK) +#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK) /* DMA Channel 1 Tx Descriptor Ring Length (DMA_CH1_TXDESC_RING_LENGTH) */ #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */ #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) -#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) ((n << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK) +#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK) /* DMA Channel 1 Rx Descriptor Ring Length (DMA_CH1_RXDESC_RING_LENGTH) */ #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */ #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) -#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) ((n << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK) +#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK) /* DMA Channel 1 Interrupt Enable (DMA_CH1_INTERRUPT_ENABLE) */ #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE (1 << 0) /* Bit 0: Transmit Interrupt Enable */ @@ -2945,10 +2945,10 @@ #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */ #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) ((n << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) +#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */ #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) -#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) ((n << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) +#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) /* DMA Channel 1 Slot Function Control Status * (DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS) @@ -2958,10 +2958,10 @@ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) ((n << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) +#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */ #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) -#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) ((n << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) +#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) /* DMA Channel 1 Current Application Transmit Descriptor * (DMA_CH1_CURRENT_APP_TXDESC) @@ -2969,7 +2969,7 @@ #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */ #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) -#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) +#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) /* DMA Channel 1 Current Application Receive Descriptor * (DMA_CH1_CURRENT_APP_RXDESC) @@ -2977,7 +2977,7 @@ #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */ #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) -#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) +#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) /* DMA Channel 1 Current Application Transmit Buffer * (DMA_CH1_CURRENT_APP_TXBUFFER) @@ -2985,7 +2985,7 @@ #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */ #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) -#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) +#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) /* DMA Channel 1 Current Application Receive Buffer * (DMA_CH1_CURRENT_APP_RXBUFFER) @@ -2993,7 +2993,7 @@ #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */ #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) -#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) +#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) /* DMA Channel 1 Status (DMA_CH1_STATUS) */ #define EMAC_DMA_CH1_STATUS_TI (1 << 0) /* Bit 0: Transmit Interrupt */ @@ -3011,27 +3011,27 @@ #define EMAC_DMA_CH1_STATUS_NIS (1 << 15) /* Bit 15: Normal Interrupt Summary */ #define EMAC_DMA_CH1_STATUS_TEB_SHIFT (16) /* Bits 16-19: Tx DMA Error Bits */ #define EMAC_DMA_CH1_STATUS_TEB_MASK (0x7 << EMAC_DMA_CH1_STATUS_TEB_SHIFT) -#define EMAC_DMA_CH1_STATUS_TEB(n) ((n << EMAC_DMA_CH1_STATUS_TEB_SHIFT) & EMAC_DMA_CH1_STATUS_TEB_MASK) +#define EMAC_DMA_CH1_STATUS_TEB(n) (((n) << EMAC_DMA_CH1_STATUS_TEB_SHIFT) & EMAC_DMA_CH1_STATUS_TEB_MASK) #define EMAC_DMA_CH1_STATUS_REB_SHIFT (19) /* Bits 19-22: Rx DMA Error Bits */ #define EMAC_DMA_CH1_STATUS_REB_MASK (0x7 << EMAC_DMA_CH1_STATUS_REB_SHIFT) -#define EMAC_DMA_CH1_STATUS_REB(n) ((n << EMAC_DMA_CH1_STATUS_REB_SHIFT) & EMAC_DMA_CH1_STATUS_REB_MASK) +#define EMAC_DMA_CH1_STATUS_REB(n) (((n) << EMAC_DMA_CH1_STATUS_REB_SHIFT) & EMAC_DMA_CH1_STATUS_REB_MASK) /* DMA Channel 1 Miss Frame Counter (DMA_CH1_MISS_FRAME_CNT) */ #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters */ #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) -#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) ((n << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK) +#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK) #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */ /* DMA Channel 1 Rx Parser Accept Count (DMA_CH1_RXP_ACCEPT_CNT) */ #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */ #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) -#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) ((n << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK) +#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK) #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */ /* DMA Channel 1 Rx ERI Count (DMA_CH1_RX_ERI_CNT) */ #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */ #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) -#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) ((n << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK) +#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK) #define EMAC_TDES3_CPC(x) (((uint32_t)(((uint32_t)(x)) << 26U)) & 0x0C000000U) #define EMAC_TDES3_CIC(x) (((uint32_t)(((uint32_t)(x)) << 16U)) & 0x00030000U) diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c index 4ac3536c4f9..8f675dbcf20 100644 --- a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c +++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c @@ -31,14 +31,6 @@ #include "mr-canhubk3.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef OK -# define OK 0 -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c index e3dffda6726..e4b3fe1123b 100644 --- a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c +++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c @@ -65,21 +65,22 @@ void board_userled(int led, bool ledon) { uint32_t ledcfg; - if (led == BOARD_LED_R) + switch (ledcfg) { - ledcfg = GPIO_LED_R; - } - else if (led == BOARD_LED_G) - { - ledcfg = GPIO_LED_G; - } - else if (led == BOARD_LED_B) - { - ledcfg = GPIO_LED_B; - } - else - { - return; + case BOARD_LED_R: + ledcfg = GPIO_LED_R; + break; + + case BOARD_LED_G: + ledcfg = GPIO_LED_G; + break; + + case BOARD_LED_B: + ledcfg = GPIO_LED_B; + break; + + default: + return; } /* Invert output, an output of '0' illuminates the LED */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c index efbe5b9aa4f..e927f834b38 100644 --- a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c @@ -31,14 +31,6 @@ #include "s32k344evb.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef OK -# define OK 0 -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c index daceb4fb285..5919e96ffed 100644 --- a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c @@ -70,33 +70,34 @@ void board_userled(int led, bool ledon) { uint32_t ledcfg; - if (led == BOARD_LED0_R) + switch (ledcfg) { - ledcfg = GPIO_LED0_R; - } - else if (led == BOARD_LED0_G) - { - ledcfg = GPIO_LED0_G; - } - else if (led == BOARD_LED0_B) - { - ledcfg = GPIO_LED0_B; - } - else if (led == BOARD_LED1_R) - { - ledcfg = GPIO_LED1_R; - } - else if (led == BOARD_LED1_G) - { - ledcfg = GPIO_LED1_G; - } - else if (led == BOARD_LED1_B) - { - ledcfg = GPIO_LED1_B; - } - else - { - return; + case BOARD_LED0_R: + ledcfg = GPIO_LED0_R; + break; + + case BOARD_LED0_G: + ledcfg = GPIO_LED0_G; + break; + + case BOARD_LED0_B: + ledcfg = GPIO_LED0_B; + break; + + case BOARD_LED1_R: + ledcfg = GPIO_LED1_R; + break; + + case BOARD_LED1_G: + ledcfg = GPIO_LED1_G; + break; + + case BOARD_LED1_B: + ledcfg = GPIO_LED1_B; + break; + + default: + return; } /* An output of '1' illuminates the LED */ diff --git a/drivers/mtd/mx25rxx.c b/drivers/mtd/mx25rxx.c index ef1b36c6499..e9d0928cbb3 100644 --- a/drivers/mtd/mx25rxx.c +++ b/drivers/mtd/mx25rxx.c @@ -101,9 +101,9 @@ #define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */ #ifdef CONFIG_MX25RXX_LXX -#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */ +# define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */ #else -#define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */ +# define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */ #endif #define MX25R_JEDEC_MX25R6435F_CAPACITY 0x17 /* MX25R6435F memory capacity */ #define MX25R_JEDEC_MX25R8035F_CAPACITY 0x14 /* MX25R8035F memory capacity */ @@ -118,9 +118,9 @@ #define MX25R6435F_PAGE_SIZE (256) #ifdef CONFIG_MX25RXX_PAGE128 -#define MX25R6435F_PAGE_SHIFT (7) +# define MX25R6435F_PAGE_SHIFT (7) #else -#define MX25R6435F_PAGE_SHIFT (8) +# define MX25R6435F_PAGE_SHIFT (8) #endif /* Status register bit definitions */ diff --git a/net/can/can_input.c b/net/can/can_input.c index 7a073d566d7..d01a2d199f1 100644 --- a/net/can/can_input.c +++ b/net/can/can_input.c @@ -161,7 +161,7 @@ int can_input(struct net_driver_s *dev) { conn = can_nextconn(conn); - if (conn && (conn->dev == 0x0 || dev == conn->dev)) + if (conn && (conn->dev == NULL || dev == conn->dev)) { uint16_t flags;