diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index 12c02e63b22..d77e25ef6a3 100644 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -417,11 +417,37 @@ #define CP0_CONFIG2_M (1 << 31) /* Bit 31: Config3 register is present */ /* Register Number: 16 Sel: 3 Name: Config3 - * Function: Configuration register 3 + * Function: Configuration register 3 (Section 50: "CPU for Devices with MIPS32 + * microAptive and M-Class Cores") * Compliance Level: Optional. */ -#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */ -#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */ + +#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */ +#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */ +#define CP0_CONFIG3_CDMM (1 << 3) /* Bit 3: Common Device Memory Map */ +#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Small page bit */ +#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */ +#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */ +#define CP0_CONFIG3_ITL (1 << 8) /* Bit 8: Flowtrace® Hardware bit */ +#define CP0_CONFIG3_DSPP (1 << 10) /* Bit 10: MIPS DSP ASE Presence bit */ +#define CP0_CONFIG3_DSP2 (1 << 11) /* Bit 11: MIPS DSP ASE Revision 2 Presence bit */ +#define CP0_CONFIG3_RXI (1 << 12) /* Bit 12: RIE and XIE Implemented in PageGrain bit */ +#define CP0_CONFIG3_ULRI (1 << 13) /* Bit 13: UserLocal register implemented bit */ +#define CP0_CONFIG3_ISA_SHIFT (14) /* Bits 14-15: Indicates Instruction Set Availability */ +#define CP0_CONFIG3_ISA_MASK (3 << CP0_CONFIG3_ISA_SHIFT) +# define CP0_CONFIG3_ISA_MIPS32 (0 << CP0_CONFIG3_ISA_SHIFT) /* Only MIPS32 is implemented */ +# define CP0_CONFIG3_ISA_MICROMIPS (1 << CP0_CONFIG3_ISA_SHIFT) /* Only microMIPS is implemented */ +# define CP0_CONFIG3_ISA_BOTHMIP32 (2 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, MIPS32 on reset */ +# define CP0_CONFIG3_ISA_BOTHUMIPS (3 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, microMIPS on reset */ +#define CP0_CONFIG3_ISAONEXC (1 << 16) /* Bit 16: ISA on Exception bit */ +#define CP0_CONFIG3_MCU (1 << 17) /* Bit 17: MIPS MCU ASE Implemented bit */ +#define CP0_CONFIG3_MMAR_SHIFT (18) /* Bits 18-20: microMIPS Architecture Revision level bits */ +#define CP0_CONFIG3_MMAR_MASK (7 << CP0_CONFIG3_MMAR_SHIFT) +# define CP0_CONFIG3_MMAR_REL1 (0 << CP0_CONFIG3_MMAR_SHIFT) /* Release 1 */ +#define CP0_CONFIG3_IPLW_SHIFT (21) /* Bits 21-22: Width of the Status IPL and Cause RIPL bits */ +#define CP0_CONFIG3_IPLW_MASK (3 << CP0_CONFIG3_IPLW_SHIFT) +# define CP0_CONFIG3_IPLW_6BITS (0 << CP0_CONFIG3_IPLW_SHIFT) /* 6 bits */ +# define CP0_CONFIG3_IPLW_8BITS (1 << CP0_CONFIG3_IPLW_SHIFT) /* 8 bits */ #define CP0_CONFIG3_M (1 << 31) /* Bit 31: Config4 register is present */ /* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */ diff --git a/arch/mips/include/pic32mx/cp0.h b/arch/mips/include/pic32mx/cp0.h index 81e542cd07a..1007262a17c 100644 --- a/arch/mips/include/pic32mx/cp0.h +++ b/arch/mips/include/pic32mx/cp0.h @@ -299,10 +299,6 @@ * See arch/mips/include/mips32/cp0.h */ -#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */ -#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */ -#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */ - /* Register Number: 17-22 Reserved * Compliance Level: Optional. */ diff --git a/arch/mips/include/pic32mz/cp0.h b/arch/mips/include/pic32mz/cp0.h index 01ebbe21118..90d0ade0853 100644 --- a/arch/mips/include/pic32mz/cp0.h +++ b/arch/mips/include/pic32mz/cp0.h @@ -421,10 +421,6 @@ * See arch/mips/include/mips32/cp0.h */ -#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */ -#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */ -#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */ - /* Register Number: 16 Sel: 4 Name: Config4 * To be provided */ diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c index cce67178df3..5f7e2f3e588 100644 --- a/arch/mips/src/common/up_exit.c +++ b/arch/mips/src/common/up_exit.c @@ -190,10 +190,11 @@ void _exit(int status) up_fullcontextrestore(tcb->xcp.regs); - /* up_fullcontextrestore() should not return but could if the software - * interrupts are disabled. + /* up_fullcontextrestore() should not return but could if software + * interrupts are disabled. NOTE: Can't use DEBUGPANIC here because + * that results in a GCC compilation warning: "No return function does + * return" */ - DEBUGPANIC(); + PANIC(); } - diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index 424567074a7..bc631db9f70 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -544,9 +544,9 @@ __start: * config3ISAOnExc now that exception vectors have been [re]located. */ - mfc0 t0, MICROAPTIV_CP0_CONFIG3 /* Load CONFIG3 register */ + mfc0 t0, MIPS32_CP0_CONFIG3 /* Load CONFIG3 register */ or t0, t0, CP0_CONFIG3_ISAONEXC /* Specify microMIPS mode on exceptions */ - mtc0 t0, MICROAPTIV_CP0_CONFIG3 /* Update CONFIG3 register */ + mtc0 t0, MIPS32_CP0_CONFIG3 /* Update CONFIG3 register */ #endif /* Start NuttX. We do this via a thunk in the text section so that diff --git a/mm/iob/iob_free.c b/mm/iob/iob_free.c index 57d858ac856..c288ec660a5 100644 --- a/mm/iob/iob_free.c +++ b/mm/iob/iob_free.c @@ -54,20 +54,22 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_IOB_NOTIFIER_DIV) || CONFIG_IOB_NOTIFIER_DIV < 2 -# define IOB_DIVIDER 1 -#elif CONFIG_IOB_NOTIFIER_DIV < 4 -# define IOB_DIVIDER 2 -#elif CONFIG_IOB_NOTIFIER_DIV < 8 -# define IOB_DIVIDER 4 -#elif CONFIG_IOB_NOTIFIER_DIV < 16 -# define IOB_DIVIDER 8 -#elif CONFIG_IOB_NOTIFIER_DIV < 32 -# define IOB_DIVIDER 16 -#elif CONFIG_IOB_NOTIFIER_DIV < 64 -# define IOB_DIVIDER 32 -#else -# define IOB_DIVIDER 64 +#ifdef CONFIG_IOB_NOTIFIER +# if !defined(CONFIG_IOB_NOTIFIER_DIV) || CONFIG_IOB_NOTIFIER_DIV < 2 +# define IOB_DIVIDER 1 +# elif CONFIG_IOB_NOTIFIER_DIV < 4 +# define IOB_DIVIDER 2 +# elif CONFIG_IOB_NOTIFIER_DIV < 8 +# define IOB_DIVIDER 4 +# elif CONFIG_IOB_NOTIFIER_DIV < 16 +# define IOB_DIVIDER 8 +# elif CONFIG_IOB_NOTIFIER_DIV < 32 +# define IOB_DIVIDER 16 +# elif CONFIG_IOB_NOTIFIER_DIV < 64 +# define IOB_DIVIDER 32 +# else +# define IOB_DIVIDER 64 +# endif #endif #define IOB_MASK (IOB_DIVIDER - 1)