diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 0e5e451c692..de781cdb9b9 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -208,6 +208,7 @@ config ARCH_CHIP_SAMA5D2 select SAMA5_HAVE_FLEXCOM1 select SAMA5_HAVE_FLEXCOM2 select SAMA5_HAVE_FLEXCOM3 + select SAMA5_HAVE_FLEXCOM4 select SAMA5_HAVE_QSPI select SAMA5_HAVE_XDMA select SAMA5_HAVE_SAIC diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 04f7cfacf3d..65a203c45f0 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -133,7 +133,7 @@ CHIP_ASRCS = CHIP_CSRCS = sam_allocateheap.c sam_boot.c sam_clockconfig.c sam_irq.c CHIP_CSRCS += sam_lowputc.c sam_memories.c sam_memorymap.c sam_pck.c -CHIP_CSRCS += sam_pio.c sam_pmc.c sam_sckc.c sam_serial.c +CHIP_CSRCS += sam_pio.c sam_pmc.c sam_sckc.c sam_serial.c sam_serialinit.c # Configuration dependent C and assembly language files @@ -181,6 +181,10 @@ ifeq ($(CONFIG_SAMA5_TRNG),y) CHIP_CSRCS += sam_trng.c endif +ifeq ($(CONFIG_SAMA5_FLEXCOM_USART),y) +CHIP_CSRCS += sam_flexcom_serial.c +endif + ifeq ($(CONFIG_SAMA5_SPI0),y) CHIP_CSRCS += sam_spi.c else diff --git a/arch/arm/src/sama5/chip/sam_flexcom_usart.h b/arch/arm/src/sama5/chip/sam_flexcom_usart.h index 3089f53b4c7..f5fea0a6b58 100644 --- a/arch/arm/src/sama5/chip/sam_flexcom_usart.h +++ b/arch/arm/src/sama5/chip/sam_flexcom_usart.h @@ -502,7 +502,7 @@ # define FLEXUS_LINBRR_LINCD(n) ((uint32_t)(n) << FLEXUS_LINBRR_LINCD_SHIFT) #define FLEXUS_LINBRR_LINFP_SHIFT (16) /* Bits 16-18: Fractional Part after Synchronization */ #define FLEXUS_LINBRR_LINFP_MASK (7 << FLEXUS_LINBRR_LINFP_SHIFT) -# define FLEXUS_LINBRR_LINFP_MASK ((uint32_t)(n) << FLEXUS_LINBRR_LINFP_SHIFT) +# define FLEXUS_LINBRR_LINFP(n) ((uint32_t)(n) << FLEXUS_LINBRR_LINFP_SHIFT) /* USART Comparison Register */ diff --git a/arch/arm/src/sama5/sam_config.h b/arch/arm/src/sama5/sam_config.h index af25f9f7553..7d4b8a3f0dd 100644 --- a/arch/arm/src/sama5/sam_config.h +++ b/arch/arm/src/sama5/sam_config.h @@ -52,24 +52,29 @@ * for our purposes. */ -#ifndef CONFIG_SAMA5_USART0 -# undef CONFIG_USART0_ISUART +#ifndef CONFIG_USART0_ISUART +# undef CONFIG_SAMA5_USART0 +# undef CONFIG_SAMA5_FLEXCOM0_USART # undef CONFIG_USART0_SERIAL_CONSOLE #endif -#ifndef CONFIG_SAMA5_USART1 -# undef CONFIG_USART1_ISUART +#ifndef CONFIG_USART1_ISUART +# undef CONFIG_SAMA5_USART1 +# undef CONFIG_SAMA5_FLEXCOM1_USART # undef CONFIG_USART1_SERIAL_CONSOLE #endif -#ifndef CONFIG_SAMA5_USART2 -# undef CONFIG_USART2_ISUART +#ifndef CONFIG_USART2_ISUART +# undef CONFIG_SAMA5_USART2 +# undef CONFIG_SAMA5_FLEXCOM2_USART # undef CONFIG_USART2_SERIAL_CONSOLE #endif -#ifndef CONFIG_SAMA5_USART3 -# undef CONFIG_USART3_ISUART +#ifndef CONFIG_USART3_ISUART +# undef CONFIG_SAMA5_USART3 +# undef CONFIG_SAMA5_FLEXCOM3_USART # undef CONFIG_USART3_SERIAL_CONSOLE #endif -#ifndef CONFIG_SAMA5_USART4 -# undef CONFIG_USART4_ISUART +#ifndef CONFIG_USART4_ISUART +# undef CONFIG_SAMA4_USART4 +# undef CONFIG_SAMA5_FLEXCOM4_USART # undef CONFIG_USART4_SERIAL_CONSOLE #endif @@ -81,9 +86,9 @@ # define SAMA5_HAVE_UART #endif -#if defined(CONFIG_USART0_ISUART) || defined(CONFIG_USART1_ISUART) || \ - defined(CONFIG_USART2_ISUART) || defined(CONFIG_USART3_ISUART) || \ - defined(CONFIG_USART4_ISUART) +#if defined(CONFIG_SAMA0_USART4) || defined(CONFIG_SAMA1_USART4) || \ + defined(CONFIG_SAMA2_USART4) || defined(CONFIG_SAMA3_USART4) || \ + defined(CONFIG_SAMA4_USART4) # define SAMA5_HAVE_USART #endif @@ -101,22 +106,6 @@ # undef CONFIG_SAMA5_FLEXCOM4_USART #endif -#ifndef CONFIG_USART0_ISUART -# undef CONFIG_SAMA5_FLEXCOM0_USART -#endif -#ifndef CONFIG_USART1_ISUART -# undef CONFIG_SAMA5_FLEXCOM1_USART -#endif -#ifndef CONFIG_USART2_ISUART -# undef CONFIG_SAMA5_FLEXCOM2_USART -#endif -#ifndef CONFIG_USART3_ISUART -# undef CONFIG_SAMA5_FLEXCOM3_USART -#endif -#ifndef CONFIG_USART4_ISUART -# undef CONFIG_SAMA5_FLEXCOM4_USART -#endif - #if defined(CONFIG_SAMA5_FLEXCOM0_USART) || defined(CONFIG_SAMA5_FLEXCOM1_USART) || \ defined(CONFIG_SAMA5_FLEXCOM2_USART) || defined(CONFIG_SAMA5_FLEXCOM3_USART) || \ defined(CONFIG_SAMA5_FLEXCOM4_USART) @@ -135,150 +124,261 @@ /* Is there a serial console? It could be on UART0-4 or USART0-3 */ #if defined(CONFIG_SAMA5_DBGU_CONSOLE) && defined(CONFIG_SAMA5_DBGU) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef SAMA5_HAVE_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# define SAMA5_HAVE_DBGU_CONSOLE 1 +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART0) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# define SAMA5_HAVE_UART_CONSOLE 1 +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART1) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# define SAMA5_HAVE_UART_CONSOLE 1 +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART2) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# define SAMA5_HAVE_UART_CONSOLE 1 +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART3) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# define SAMA5_HAVE_UART_CONSOLE 1 +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_UART4) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# define SAMA5_HAVE_UART_CONSOLE 1 +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_USART0_ISUART) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# define SAMA5_HAVE_USART_CONSOLE 1 +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_ISUART) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# define SAMA5_HAVE_USART_CONSOLE 1 +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_ISUART) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# define SAMA5_HAVE_USART_CONSOLE 1 +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_ISUART) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# define SAMA5_HAVE_USART_CONSOLE 1 +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_USART4_ISUART) -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# define SAMA5_HAVE_SERIAL_CONSOLE 1 +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# define SAMA5_HAVE_USART_CONSOLE 1 +# undef SAMA5_HAVE_FLEXCOM_CONSOLE +#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_FLEXCOM0_USART) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# define SAMA5_HAVE_FLEXCOM_CONSOLE 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_FLEXCOM1_USART) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# define SAMA5_HAVE_FLEXCOM_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_FLEXCOM2_USART) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# define SAMA5_HAVE_FLEXCOM_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_FLEXCOM3_USART) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# define SAMA5_HAVE_FLEXCOM_CONSOLE 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_SAMA5_FLEXCOM4_USART) +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# define SAMA5_HAVE_FLEXCOM_CONSOLE 1 #else -# warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" -# undef CONFIG_SAMA5_DBGU_CONSOLE -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef CONFIG_UART4_SERIAL_CONSOLE -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART3_SERIAL_CONSOLE -# undef CONFIG_USART4_SERIAL_CONSOLE -# undef SAMA5_HAVE_SERIAL_CONSOLE +# warning "No valid CONFIG_UARTn/USARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_SAMA5_DBGU_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef SAMA5_HAVE_DBGU_CONSOLE +# undef SAMA5_HAVE_UART_CONSOLE +# undef SAMA5_HAVE_USART_CONSOLE +# undef SAMA5_HAVE_FLEXCOM_CONSOLE #endif #endif /* __ARCH_ARM_SRC_SAMA5_SAM_CONFIG_H */ diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c new file mode 100644 index 00000000000..74f3e409441 --- /dev/null +++ b/arch/arm/src/sama5/sam_flexcom_serial.c @@ -0,0 +1,1268 @@ +/**************************************************************************** + * arch/arm/src/sama5/sam_flexcom_serial.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip.h" +#include "chip/sam_flexcom.h" +#include "sam_config.h" +#include "sam_dbgu.h" +#include "sam_serial.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +#undef TTYFC0_DEV +#undef TTYFC1_DEV +#undef TTYFC2_DEV +#undef TTYFC3_DEV +#undef TTYFC4_DEV + +#undef USART0_ASSIGNED +#undef USART1_ASSIGNED +#undef USART2_ASSIGNED +#undef USART3_ASSIGNED +#undef USART4_ASSIGNED + +#ifdef SAMA5_HAVE_FLEXCOM_USART + +/* Which Flexcom with be ttyFC0/console and which ttyFC1? ttyFC2? ttyFC3? + * ttyFC4? ttyFC5? + */ + +/* First pick the console and ttyFC0. This could be any of FLEXUS0-4 */ + +#if defined(CONFIG_USART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_flexus0port /* FLEXUS0 is console */ +# define TTYFC0_DEV g_flexus0port /* FLEXUS0 is ttyFC0 */ +# define FLEXUS0_ASSIGNED 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_flexus1port /* FLEXUS1 is console */ +# define TTYFC0_DEV g_flexus1port /* FLEXUS1 is ttyFC0 */ +# define FLEXUS1_ASSIGNED 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_flexus2port /* FLEXUS2 is console */ +# define TTYFC0_DEV g_flexus2port /* FLEXUS2 is ttyFC0 */ +# define FLEXUS2_ASSIGNED 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_flexus3port /* FLEXUS3 is console */ +# define TTYFC0_DEV g_flexus3port /* FLEXUS3 is ttyFC0 */ +# define FLEXUS3_ASSIGNED 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_flexus4port /* FLEXUS4 is console */ +# define TTYFC0_DEV g_flexus4port /* FLEXUS4 is ttyFC0 */ +# define FLEXUS4_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_USART0_ISUART) +# define TTYFC0_DEV g_flexus0port /* FLEXUS0 is ttyFC0 */ +# define FLEXUS0_ASSIGNED 1 +# elif defined(CONFIG_USART1_ISUART) +# define TTYFC0_DEV g_flexus1port /* FLEXUS1 is ttyFC0 */ +# define FLEXUS1_ASSIGNED 1 +# elif defined(CONFIG_USART2_ISUART) +# define TTYFC0_DEV g_flexus2port /* FLEXUS2 is ttyFC0 */ +# define FLEXUS2_ASSIGNED 1 +# elif defined(CONFIG_USART3_ISUART) +# define TTYFC0_DEV g_flexus3port /* FLEXUS3 is ttyFC0 */ +# define FLEXUS3_ASSIGNED 1 +# elif defined(CONFIG_USART4_ISUART) +# define TTYFC0_DEV g_flexus4port /* FLEXUS4 is ttyFC0 */ +# define FLEXUS4_ASSIGNED 4 +# endif +#endif + +/* Pick ttyFC1. This could be any of USART0-4 excluding the console UART. */ + +#if defined(CONFIG_USART0_ISUART) && !defined(FLEXUS0_ASSIGNED) +# define TTYFC1_DEV g_flexus0port /* FLEXUS0 is ttyFC1 */ +# define FLEXUS0_ASSIGNED 1 +#elif defined(CONFIG_USART1_ISUART) && !defined(FLEXUS1_ASSIGNED) +# define TTYFC1_DEV g_flexus1port /* FLEXUS1 is ttyFC1 */ +# define FLEXUS1_ASSIGNED 1 +#elif defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED) +# define TTYFC1_DEV g_flexus2port /* FLEXUS2 is ttyFC1 */ +# define FLEXUS2_ASSIGNED 1 +#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED) +# define TTYFC1_DEV g_flexus3port /* FLEXUS3 is ttyFC1 */ +# define FLEXUS3_ASSIGNED 1 +#elif defined(CONFIG_USART4_ISUART) && !defined(FLEXUS4_ASSIGNED) +# define TTYFC1_DEV g_flexus4port /* FLEXUS4 is ttyFC1 */ +# define FLEXUS4_ASSIGNED 1 +#endif + +/* Pick ttyFC2. This could be one of FLEXUS1-4. It can't be FLEXUS0 + * because that was either assigned as ttyFC0 or ttyFC1. One of these + * could also be the console. + */ + +#if defined(CONFIG_USART1_ISUART) && !defined(FLEXUS1_ASSIGNED) +# define TTYFC2_DEV g_flexus1port /* FLEXUS1 is ttyFC2 */ +# define FLEXUS1_ASSIGNED 1 +#elif defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED) +# define TTYFC2_DEV g_flexus2port /* FLEXUS2 is ttyFC2 */ +# define FLEXUS2_ASSIGNED 1 +#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED) +# define TTYFC2_DEV g_flexus3port /* FLEXUS3 is ttyFC2 */ +# define FLEXUS3_ASSIGNED 1 +#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED) +# define TTYFC2_DEV g_flexus4port /* FLEXUS4 is ttyFC2 */ +# define FLEXUS4_ASSIGNED 1 +#endif + +/* Pick ttyFC3. This could be one of FLEXUS2-4. It can't be FLEXUS0-1 + * UART0-1; those have already been assigned to ttyFC0, 1, or 2. One of + * FLEXUS2-4 could also be the console. + */ + +#if defined(CONFIG_USART2_ISUART) && !defined(FLEXUS2_ASSIGNED) +# define TTYFC3_DEV g_flexus2port /* FLEXUS2 is ttyFC3 */ +# define FLEXUS2_ASSIGNED 1 +#elif defined(CONFIG_USART3_ISUART) && !defined(FLEXUS3_ASSIGNED) +# define TTYFC3_DEV g_flexus3port /* FLEXUS3 is ttyFC3 */ +# define FLEXUS3_ASSIGNED 1 +#elif defined(CONFIG_USART4_ISUART) && !defined(FLEXUS4_ASSIGNED) +# define TTYFC3_DEV g_flexus4port /* FLEXUS4 is ttyFC3 */ +# define FLEXUS4_ASSIGNED 1 +#endif + +/* Pick ttyFC4. This could be one of USART3-4. It can't be one of + * USART0-2; those have already been assigned to ttyFC0-3. One of + * USART3-4 could also be the console. + */ + +#if defined(CONFIG_USART3_ISUART) && !defined(USART3_ASSIGNED) +# define TTYFC4_DEV g_flexus3port /* USART3 is ttyFC4 */ +# define USART3_ASSIGNED 1 +#elif defined(CONFIG_USART4_ISUART) && !defined(USART4_ASSIGNED) +# define TTYFC4_DEV g_flexus4port /* USART4 is ttyFC4 */ +# define USART4_ASSIGNED 1 +#endif + +/* The Flexcom modules are driven by the peripheral clock (MCK or MCK2). */ + +#define SAM_USART_CLOCK BOARD_FLEXCOM_FREQUENCY /* Frequency of the FLEXCOM clock */ +#define SAM_MR_USCLKS FLEXUS_MR_USCLKS_MCK /* Source = Main clock */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct flexus_dev_s +{ + xcpt_t handler; /* Interrupt handler */ + uint32_t usartbase; /* Base address of USART registers */ + uint32_t baud; /* Configured baud */ + uint32_t sr; /* Saved status bits */ + uint8_t irq; /* IRQ associated with this USART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; /* input flow control (RTS) enabled */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int flexus_interrupt(struct uart_dev_s *dev); +#ifdef CONFIG_USART0_ISUART +static int flexus0_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART1_ISUART +static int flexus1_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART2_ISUART +static int flexus2_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART3_ISUART +static int flexus3_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART4_ISUART +static int flexus4_interrupt(int irq, void *context); +#endif + +static int flexus_setup(struct uart_dev_s *dev); +static void flexus_shutdown(struct uart_dev_s *dev); +static int flexus_attach(struct uart_dev_s *dev); +static void flexus_detach(struct uart_dev_s *dev); +static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg); +static int flexus_receive(struct uart_dev_s *dev, uint32_t *status); +static void flexus_rxint(struct uart_dev_s *dev, bool enable); +static bool flexus_rxavailable(struct uart_dev_s *dev); +static void flexus_send(struct uart_dev_s *dev, int ch); +static void flexus_txint(struct uart_dev_s *dev, bool enable); +static bool flexus_txready(struct uart_dev_s *dev); +static bool flexus_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +static const struct uart_ops_s g_flexus_ops = +{ + .setup = flexus_setup, + .shutdown = flexus_shutdown, + .attach = flexus_attach, + .detach = flexus_detach, + .ioctl = flexus_ioctl, + .receive = flexus_receive, + .rxint = flexus_rxint, + .rxavailable = flexus_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = flexus_send, + .txint = flexus_txint, + .txready = flexus_txready, + .txempty = flexus_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_USART0_ISUART +static char g_flexus0rxbuffer[CONFIG_USART0_RXBUFSIZE]; +static char g_flexus0txbuffer[CONFIG_USART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_USART1_ISUART +static char g_flexus1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_flexus1txbuffer[CONFIG_USART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_USART2_ISUART +static char g_flexus2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_flexus2txbuffer[CONFIG_USART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_USART3_ISUART +static char g_flexus3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_flexus3txbuffer[CONFIG_USART3_TXBUFSIZE]; +#endif +#ifdef CONFIG_USART4_ISUART +static char g_flexus4rxbuffer[CONFIG_USART4_RXBUFSIZE]; +static char g_flexus4txbuffer[CONFIG_USART4_TXBUFSIZE]; +#endif + +/* This describes the state of the USART0 port. */ + +#ifdef CONFIG_USART0_ISUART +static struct flexus_dev_s g_flexus0priv = +{ + .handler = flexus0_interrupt, + .usartbase = SAM_FLEXUS0_VBASE, + .baud = CONFIG_USART0_BAUD, + .irq = SAM_IRQ_FLEXCOM0, + .parity = CONFIG_USART0_PARITY, + .bits = CONFIG_USART0_BITS, + .stopbits2 = CONFIG_USART0_2STOP, +#if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL) + .flowc = true, +#endif +}; + +static uart_dev_t g_flexus0port = +{ + .recv = + { + .size = CONFIG_USART0_RXBUFSIZE, + .buffer = g_flexus0rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART0_TXBUFSIZE, + .buffer = g_flexus0txbuffer, + }, + .ops = &g_flexus_ops, + .priv = &g_flexus0priv, +}; +#endif + +/* This describes the state of the USART1 port. */ + +#ifdef CONFIG_USART1_ISUART +static struct flexus_dev_s g_flexus1priv = +{ + .handler = flexus1_interrupt, + .usartbase = SAM_FLEXUS1_VBASE, + .baud = CONFIG_USART1_BAUD, + .irq = SAM_IRQ_FLEXCOM1, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .stopbits2 = CONFIG_USART1_2STOP, +#if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL) + .flowc = true, +#endif +}; + +static uart_dev_t g_flexus1port = +{ + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_flexus1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_flexus1txbuffer, + }, + .ops = &g_flexus_ops, + .priv = &g_flexus1priv, +}; +#endif + +/* This describes the state of the USART2 port. */ + +#ifdef CONFIG_USART2_ISUART +static struct flexus_dev_s g_flexus2priv = +{ + .handler = flexus2_interrupt, + .usartbase = SAM_FLEXUS2_VBASE, + .baud = CONFIG_USART2_BAUD, + .irq = SAM_IRQ_FLEXCOM2, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .stopbits2 = CONFIG_USART2_2STOP, +#if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL) + .flowc = true, +#endif +}; + +static uart_dev_t g_flexus2port = +{ + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_flexus2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_flexus2txbuffer, + }, + .ops = &g_flexus_ops, + .priv = &g_flexus2priv, +}; +#endif + +/* This describes the state of the USART3 port. */ + +#ifdef CONFIG_USART3_ISUART +static struct flexus_dev_s g_flexus3priv = +{ + .handler = flexus3_interrupt, + .usartbase = SAM_FLEXUS3_VBASE, + .baud = CONFIG_USART3_BAUD, + .irq = SAM_IRQ_FLEXCOM3, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .stopbits2 = CONFIG_USART3_2STOP, +#if defined(CONFIG_USART3_OFLOWCONTROL) || defined(CONFIG_USART3_IFLOWCONTROL) + .flowc = true, +#endif +}; + +static uart_dev_t g_flexus3port = +{ + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_flexus3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_flexus3txbuffer, + }, + .ops = &g_flexus_ops, + .priv = &g_flexus3priv, +}; +#endif + +/* This describes the state of the USART4 port. */ + +#ifdef CONFIG_USART4_ISUART +static struct flexus_dev_s g_flexus4priv = +{ + .handler = flexus4_interrupt, + .usartbase = SAM_FLEXUS4_VBASE, + .baud = CONFIG_USART4_BAUD, + .irq = SAM_IRQ_FLEXCOM4, + .parity = CONFIG_USART4_PARITY, + .bits = CONFIG_USART4_BITS, + .stopbits2 = CONFIG_USART4_2STOP, +#if defined(CONFIG_USART4_OFLOWCONTROL) || defined(CONFIG_USART4_IFLOWCONTROL) + .flowc = true, +#endif +}; + +static uart_dev_t g_flexus4port = +{ + .recv = + { + .size = CONFIG_USART4_RXBUFSIZE, + .buffer = g_flexus4rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART4_TXBUFSIZE, + .buffer = g_flexus4txbuffer, + }, + .ops = &g_flexus_ops, + .priv = &g_flexus4priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: flexus_serialin + ****************************************************************************/ + +static inline uint32_t flexus_serialin(struct flexus_dev_s *priv, int offset) +{ + return getreg32(priv->usartbase + offset); +} + +/**************************************************************************** + * Name: flexus_serialout + ****************************************************************************/ + +static inline void flexus_serialout(struct flexus_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->usartbase + offset); +} + +/**************************************************************************** + * Name: flexus_restoreusartint + ****************************************************************************/ + +static inline void flexus_restoreusartint(struct flexus_dev_s *priv, + uint32_t imr) +{ + /* Restore the previous interrupt state (assuming all interrupts disabled) */ + + flexus_serialout(priv, SAM_FLEXUS_IER_OFFSET, imr); +} + +/**************************************************************************** + * Name: flexus_disableallints + ****************************************************************************/ + +static void flexus_disableallints(struct flexus_dev_s *priv, uint32_t *imr) +{ + irqstate_t flags; + + /* The following must be atomic */ + + flags = irqsave(); + + /* Return the current interrupt state */ + + if (imr) + { + *imr = flexus_serialin(priv, SAM_FLEXUS_IMR_OFFSET); + } + + /* Disable all interrupts */ + + flexus_serialout(priv, SAM_FLEXUS_IDR_OFFSET, FLEXUS_INT_ALLINTS); + irqrestore(flags); +} + +/**************************************************************************** + * Name: flexus_interrupt + * + * Description: + * This is the common USART interrupt handler. It should call + * uart_transmitchars or uart_receivechar to perform the appropriate + * data transfers. + * + ****************************************************************************/ + +static int flexus_interrupt( struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv; + uint32_t pending; + uint32_t imr; + int passes; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct flexus_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, until we have + * been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ + + priv->sr = flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET); /* Save for error reporting */ + imr = flexus_serialin(priv, SAM_FLEXUS_IMR_OFFSET); /* Interrupt mask */ + pending = priv->sr & imr; /* Mask out disabled interrupt sources */ + + /* Handle an incoming, receive byte. RXRDY: At least one complete character + * has been received and US_RHR has not yet been read. + */ + + if ((pending & FLEXUS_INT_RXRDY) != 0) + { + /* Received data ready... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes. XRDY: There is no character in the + * US_THR. + */ + + if ((pending & FLEXUS_INT_TXRDY) != 0) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: flexus*_interrupt + * + * Description: + * This is the specific UART/USART interrupt handler. These simply map + * the interrupt to the device-specific data and passes control to the + * common interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_USART0_ISUART +static int flexus0_interrupt(int irq, void *context) +{ + return flexus_interrupt(&g_flexus0port); +} +#endif +#ifdef CONFIG_USART1_ISUART +static int flexus1_interrupt(int irq, void *context) +{ + return flexus_interrupt(&g_flexus1port); +} +#endif +#ifdef CONFIG_USART2_ISUART +static int flexus2_interrupt(int irq, void *context) +{ + return flexus_interrupt(&g_flexus2port); +} +#endif +#ifdef CONFIG_USART3_ISUART +static int flexus3_interrupt(int irq, void *context) +{ + return flexus_interrupt(&g_flexus3port); +} +#endif +#ifdef CONFIG_USART4_ISUART +static int flexus4_interrupt(int irq, void *context) +{ + return flexus_interrupt(&g_flexus4port); +} +#endif + +/**************************************************************************** + * Name: flexus_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int flexus_setup(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t regval; + + /* Note: The logic here depends on the fact that that the USART module + * was enabled and the pins were configured in sam_lowsetup(). + */ + + /* The shutdown method will put the UART in a known, disabled state */ + + flexus_shutdown(dev); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + /* "Setting the USART to operate with hardware handshaking is performed by + * writing the USART_MODE field in the Mode Register (US_MR) to the value + * 0x2. ... Using this mode requires using the PDC or DMAC channel for + * reception. The transmitter can handle hardware handshaking in any case." + */ + + if (priv->flowc) + { + /* Enable hardware flow control and MCK as the timing source */ + + regval = (FLEXUS_MR_MODE_HWHS | SAM_MR_USCLKS | FLEXUS_MR_CHMODE_NORMAL); + } + else +#endif + { + /* Set up the mode register. Start with normal UART mode and the MCK + * as the timing source + */ + + regval = (FLEXUS_MR_MODE_NORMAL | SAM_MR_USCLKS | FLEXUS_MR_CHMODE_NORMAL); + } + + /* OR in settings for the selected number of bits */ + + if (priv->bits == 5) + { + regval |= FLEXUS_MR_CHRL_5BITS; /* 5 bits */ + } + else if (priv->bits == 6) + { + regval |= FLEXUS_MR_CHRL_6BITS; /* 6 bits */ + } + else if (priv->bits == 7) + { + regval |= FLEXUS_MR_CHRL_7BITS; /* 7 bits */ + } + else if (priv->bits == 9) + { + regval |= FLEXUS_MR_MODE9; /* 9 bits */ + } + else /* if (priv->bits == 8) */ + { + regval |= FLEXUS_MR_CHRL_8BITS; /* 8 bits (default) */ + } + + /* OR in settings for the selected parity */ + + if (priv->parity == 1) + { + regval |= FLEXUS_MR_PAR_ODD; + } + else if (priv->parity == 2) + { + regval |= FLEXUS_MR_PAR_EVEN; + } + else + { + regval |= FLEXUS_MR_PAR_NONE; + } + + /* OR in settings for the number of stop bits */ + + if (priv->stopbits2) + { + regval |= FLEXUS_MR_NBSTOP_2; + } + else + { + regval |= FLEXUS_MR_NBSTOP_1; + } + + /* And save the new mode register value */ + + flexus_serialout(priv, SAM_FLEXUS_MR_OFFSET, regval); + + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ + + regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); + flexus_serialout(priv, SAM_FLEXUS_BRGR_OFFSET, regval); + + /* Enable receiver & transmitter */ + + flexus_serialout(priv, SAM_FLEXUS_CR_OFFSET, (FLEXUS_CR_RXEN|FLEXUS_CR_TXEN)); +#endif + return OK; +} + +/**************************************************************************** + * Name: flexus_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void flexus_shutdown(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + + /* Reset and disable receiver and transmitter */ + + flexus_serialout(priv, SAM_FLEXUS_CR_OFFSET, + (FLEXUS_CR_RSTRX|FLEXUS_CR_RSTTX|FLEXUS_CR_RXDIS|FLEXUS_CR_TXDIS)); + + /* Disable all interrupts */ + + flexus_disableallints(priv, NULL); +} + +/**************************************************************************** + * Name: flexus_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int flexus_attach(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, priv->handler); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the USART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: flexus_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void flexus_detach(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: flexus_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int flexus_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct flexus_dev_s *user = (struct flexus_dev_s*)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct flexus_dev_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios*)arg; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0; +#endif + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + + case 9: + termiosp->c_cflag |= CS8 /* CS9 */; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios*)arg; + struct flexus_dev_s *priv = (struct flexus_dev_s *)dev->priv; + uint32_t baud; + uint32_t imr; + uint8_t parity; + uint8_t nbits; + bool stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; +#endif + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; +#if 0 + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Decode flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0; +#endif + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + priv->flowc = flowc; +#endif + /* Effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flexus_disableallints(priv, &imr); + ret = flexus_setup(dev); + + /* Restore the interrupt state */ + + flexus_restoreusartint(priv, imr); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: flexus_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int flexus_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + + /* Return the error information in the saved status */ + + *status = priv->sr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return (int)(flexus_serialin(priv, SAM_FLEXUS_RHR_OFFSET) & 0xff); +} + +/**************************************************************************** + * Name: flexus_rxint + * + * Description: + * Call to enable or disable RXRDY interrupts + * + ****************************************************************************/ + +static void flexus_rxint(struct uart_dev_s *dev, bool enable) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + flexus_serialout(priv, SAM_FLEXUS_IER_OFFSET, FLEXUS_INT_RXRDY); +#endif + } + else + { + flexus_serialout(priv, SAM_FLEXUS_IDR_OFFSET, FLEXUS_INT_RXRDY); + } +} + +/**************************************************************************** + * Name: flexus_rxavailable + * + * Description: + * Return true if the receive holding register is not empty + * + ****************************************************************************/ + +static bool flexus_rxavailable(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_RXRDY) != 0); +} + +/**************************************************************************** + * Name: flexus_send + * + * Description: + * This method will send one byte on the UART/USART + * + ****************************************************************************/ + +static void flexus_send(struct uart_dev_s *dev, int ch) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + flexus_serialout(priv, SAM_FLEXUS_THR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: flexus_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void flexus_txint(struct uart_dev_s *dev, bool enable) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + irqstate_t flags; + + flags = irqsave(); + if (enable) + { + /* Set to receive an interrupt when the TX holding register register + * is empty + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + flexus_serialout(priv, SAM_FLEXUS_IER_OFFSET, FLEXUS_INT_TXRDY); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + +#endif + } + else + { + /* Disable the TX interrupt */ + + flexus_serialout(priv, SAM_FLEXUS_IDR_OFFSET, FLEXUS_INT_TXRDY); + } + + irqrestore(flags); +} + +/**************************************************************************** + * Name: flexus_txready + * + * Description: + * Return true if the transmit holding register is empty (TXRDY) + * + ****************************************************************************/ + +static bool flexus_txready(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_TXRDY) != 0); + } + +/**************************************************************************** + * Name: flexus_txempty + * + * Description: + * Return true if the transmit holding and shift registers are empty + * + ****************************************************************************/ + +static bool flexus_txempty(struct uart_dev_s *dev) +{ + struct flexus_dev_s *priv = (struct flexus_dev_s*)dev->priv; + return ((flexus_serialin(priv, SAM_FLEXUS_CSR_OFFSET) & FLEXUS_INT_TXEMPTY) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: flexus_earlyserialinit + * + * Description: + * Performs the low level Flexcom USART initialization early so that the + * Flexcom serial console will be available during bootup. This must be + * called before flexus_serialinit. + * + ****************************************************************************/ + +void flexus_earlyserialinit(void) +{ + /* NOTE: All PIO configuration for the USARTs was performed in + * sam_lowsetup + */ + + /* Disable all USARTS */ + +#ifdef TTYFC0_DEV + flexus_disableallints(TTYFC0_DEV.priv, NULL); +#endif +#ifdef TTYFC1_DEV + flexus_disableallints(TTYFC1_DEV.priv, NULL); +#endif +#ifdef TTYFC2_DEV + flexus_disableallints(TTYFC2_DEV.priv, NULL); +#endif +#ifdef TTYFC3_DEV + flexus_disableallints(TTYFC3_DEV.priv, NULL); +#endif +#ifdef TTYFC4_DEV + flexus_disableallints(TTYFC4_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef SAMA5_HAVE_FLEXCOM_CONSOLE + CONSOLE_DEV.isconsole = true; + flexus_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: flexus_serialinit + * + * Description: + * Register Flexcom serial console and serial ports. This assumes that + * flexus_earlyserialinit was called previously. + * + ****************************************************************************/ + +void flexus_serialinit(void) +{ + /* Register the console */ + +#ifdef SAMA5_HAVE_FLEXCOM_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs/USARTs */ + +#ifdef TTYFC0_DEV + (void)uart_register("/dev/ttyFC0", &TTYFC0_DEV); +#endif +#ifdef TTYFC1_DEV + (void)uart_register("/dev/ttyFC1", &TTYFC1_DEV); +#endif +#ifdef TTYFC2_DEV + (void)uart_register("/dev/ttyFC2", &TTYFC2_DEV); +#endif +#ifdef TTYFC3_DEV + (void)uart_register("/dev/ttyFC3", &TTYFC3_DEV); +#endif +#ifdef TTYFC4_DEV + (void)uart_register("/dev/ttyFC4", &TTYFC4_DEV); +#endif +} + +#endif /* USE_SERIALDRIVER */ +#endif /* SAMA5_HAVE_FLEXCOM_USART */ diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index d37a3685b45..5259d56bb4f 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -54,6 +54,7 @@ #include "sam_lowputc.h" #include "chip/sam_uart.h" +#include "chip/sam_flexcom.h" #include "chip/sam_dbgu.h" #include "chip/sam_pinmap.h" @@ -63,8 +64,13 @@ /* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */ -#define SAM_USART_CLOCK BOARD_USART_FREQUENCY /* Frequency of the USART clock */ -#define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +#ifdef SAMA5_HAVE_FLEXCOM_CONSOLE +# define SAM_USART_CLOCK BOARD_FLEXCOM_FREQUENCY /* Frequency of the FLEXCOM clock */ +# define SAM_MR_USCLKS FLEXUS_MR_USCLKS_MCK /* Source = Main clock */ +#else +# define SAM_USART_CLOCK BOARD_USART_FREQUENCY /* Frequency of the USART clock */ +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +#endif /* Select USART parameters for the selected console */ @@ -81,84 +87,93 @@ # define SAM_CONSOLE_BAUD CONFIG_SAMA5_DBGU_BAUD # define SAM_CONSOLE_PARITY CONFIG_SAMA5_DBGU_PARITY # endif -# undef SAM_CONSOLE_ISUART #elif defined(CONFIG_UART0_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_UART0_VBASE # define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD # define SAM_CONSOLE_BITS CONFIG_UART0_BITS # define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP -# define SAM_CONSOLE_ISUART 1 #elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_UART1_VBASE # define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD # define SAM_CONSOLE_BITS CONFIG_UART1_BITS # define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP -# define SAM_CONSOLE_ISUART 1 #elif defined(CONFIG_UART2_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_UART2_VBASE # define SAM_CONSOLE_BAUD CONFIG_UART2_BAUD # define SAM_CONSOLE_BITS CONFIG_UART2_BITS # define SAM_CONSOLE_PARITY CONFIG_UART2_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART2_2STOP -# define SAM_CONSOLE_ISUART 1 #elif defined(CONFIG_UART3_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_UART3_VBASE # define SAM_CONSOLE_BAUD CONFIG_UART3_BAUD # define SAM_CONSOLE_BITS CONFIG_UART3_BITS # define SAM_CONSOLE_PARITY CONFIG_UART3_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART3_2STOP -# define SAM_CONSOLE_ISUART 1 #elif defined(CONFIG_UART4_SERIAL_CONSOLE) # define SAM_CONSOLE_VBASE SAM_UART4_VBASE # define SAM_CONSOLE_BAUD CONFIG_UART4_BAUD # define SAM_CONSOLE_BITS CONFIG_UART4_BITS # define SAM_CONSOLE_PARITY CONFIG_UART4_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART4_2STOP -# define SAM_CONSOLE_ISUART 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) -# define SAM_CONSOLE_VBASE SAM_USART0_VBASE +# ifdef CONFIG_SAMA5_FLEXCOM0_USART +# define SAM_CONSOLE_VBASE SAM_FLEXUS0_VBASE +# else +# define SAM_CONSOLE_VBASE SAM_USART0_VBASE +# endif # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD # define SAM_CONSOLE_BITS CONFIG_USART0_BITS # define SAM_CONSOLE_PARITY CONFIG_USART0_PARITY # define SAM_CONSOLE_2STOP CONFIG_USART0_2STOP -# undef SAM_CONSOLE_ISUART #elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define SAM_CONSOLE_VBASE SAM_USART1_VBASE +# ifdef CONFIG_SAMA5_FLEXCOM1_USART +# define SAM_CONSOLE_VBASE SAM_FLEXUS1_VBASE +# else +# define SAM_CONSOLE_VBASE SAM_USART1_VBASE +# endif # define SAM_CONSOLE_BAUD CONFIG_USART1_BAUD # define SAM_CONSOLE_BITS CONFIG_USART1_BITS # define SAM_CONSOLE_PARITY CONFIG_USART1_PARITY # define SAM_CONSOLE_2STOP CONFIG_USART1_2STOP -# undef SAM_CONSOLE_ISUART #elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define SAM_CONSOLE_VBASE SAM_USART2_VBASE +# ifdef CONFIG_SAMA5_FLEXCOM2_USART +# define SAM_CONSOLE_VBASE SAM_FLEXUS2_VBASE +# else +# define SAM_CONSOLE_VBASE SAM_USART2_VBASE +# endif # define SAM_CONSOLE_BAUD CONFIG_USART2_BAUD # define SAM_CONSOLE_BITS CONFIG_USART2_BITS # define SAM_CONSOLE_PARITY CONFIG_USART2_PARITY # define SAM_CONSOLE_2STOP CONFIG_USART2_2STOP -# undef SAM_CONSOLE_ISUART #elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define SAM_CONSOLE_VBASE SAM_USART3_VBASE +# ifdef CONFIG_SAMA5_FLEXCOM3_USART +# define SAM_CONSOLE_VBASE SAM_FLEXUS3_VBASE +# else +# define SAM_CONSOLE_VBASE SAM_USART3_VBASE +# endif # define SAM_CONSOLE_BAUD CONFIG_USART3_BAUD # define SAM_CONSOLE_BITS CONFIG_USART3_BITS # define SAM_CONSOLE_PARITY CONFIG_USART3_PARITY # define SAM_CONSOLE_2STOP CONFIG_USART3_2STOP -# undef SAM_CONSOLE_ISUART #elif defined(CONFIG_USART4_SERIAL_CONSOLE) -# define SAM_CONSOLE_VBASE SAM_USART4_VBASE +# ifdef CONFIG_SAMA5_FLEXCOM4_USART +# define SAM_CONSOLE_VBASE SAM_FLEXUS4_VBASE +# else +# define SAM_CONSOLE_VBASE SAM_USART4_VBASE +# endif # define SAM_CONSOLE_BAUD CONFIG_USART4_BAUD # define SAM_CONSOLE_BITS CONFIG_USART4_BITS # define SAM_CONSOLE_PARITY CONFIG_USART4_PARITY # define SAM_CONSOLE_2STOP CONFIG_USART4_2STOP -# undef SAM_CONSOLE_ISUART #else # error "No CONFIG_U[S]ARTn_SERIAL_CONSOLE Setting" #endif /* Select the settings for the mode register */ -#if defined(SAM_CONSOLE_ISUART) +#if defined(SAMA5_HAVE_UART_CONSOLE) # if SAM_CONSOLE_BITS == 8 && SAM_CONSOLE_PARITY == 0 # elif SAM_CONSOLE_BITS == 7 && SAM_CONSOLE_PARITY != 0 # else @@ -222,7 +237,7 @@ void up_lowputc(char ch) { -#if defined(SAMA5_HAVE_SERIAL_CONSOLE) +#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) irqstate_t flags; for (;;) @@ -249,6 +264,35 @@ void up_lowputc(char ch) irqrestore(flags); } + +#elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) + irqstate_t flags; + + for (;;) + { + /* Wait for the transmitter to be available */ + + while ((getreg32(SAM_CONSOLE_VBASE + SAM_FLEXUS_CSR_OFFSET) & + FLEXUS_INT_TXEMPTY) == 0); + + /* Disable interrupts so that the test and the transmission are + * atomic. + */ + + flags = irqsave(); + if ((getreg32(SAM_CONSOLE_VBASE + SAM_FLEXUS_CSR_OFFSET) & + FLEXUS_INT_TXEMPTY) != 0) + { + /* Send the character */ + + putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_FLEXUS_THR_OFFSET); + irqrestore(flags); + return; + } + + irqrestore(flags); + } + #elif defined(CONFIG_SAMA5_DBGU_CONSOLE) irqstate_t flags; @@ -287,7 +331,8 @@ void up_lowputc(char ch) int up_putc(int ch) { -#if defined(SAMA5_HAVE_SERIAL_CONSOLE) || defined(CONFIG_SAMA5_DBGU_CONSOLE) +#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) || \ + defined(SAMA5_HAVE_FLEXCOM_CONSOLE) || defined(CONFIG_SAMA5_DBGU_CONSOLE) /* Check for LF */ if (ch == '\n') @@ -432,7 +477,8 @@ void sam_lowsetup(void) /* Configure the console (only) */ -#if defined(SAMA5_HAVE_SERIAL_CONSOLE) && !defined(SUPPRESS_CONSOLE_CONFIG) +#if (defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE)) && \ + !defined(SUPPRESS_CONSOLE_CONFIG) /* Reset and disable receiver and transmitter */ putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS), @@ -457,6 +503,33 @@ void sam_lowsetup(void) putreg32((UART_CR_RXEN | UART_CR_TXEN), SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET); + +#elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) && !defined(SUPPRESS_CONSOLE_CONFIG) + /* Reset and disable receiver and transmitter */ + + putreg32((FLEXUS_CR_RSTRX | FLEXUS_CR_RSTTX | FLEXUS_CR_RXDIS | FLEXUS_CR_TXDIS), + SAM_CONSOLE_VBASE + SAM_FLEXUS_CR_OFFSET); + + /* Disable all interrupts */ + + putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_FLEXUS_IDR_OFFSET); + + /* Set up the mode register */ + + putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_FLEXUS_MR_OFFSET); + + /* Configure the console baud. NOTE: Oversampling by 8 is not supported. + * This may limit BAUD rates for lower USART clocks. + */ + + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), + SAM_CONSOLE_VBASE + SAM_FLEXUS_BRGR_OFFSET); + + /* Enable receiver & transmitter */ + + putreg32((FLEXUS_CR_RXEN | FLEXUS_CR_TXEN), + SAM_CONSOLE_VBASE + SAM_FLEXUS_CR_OFFSET); + #endif #ifdef CONFIG_SAMA5_DBGU diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 6d75afec354..e7e15ab85c5 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_serial.c * - * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -78,6 +78,7 @@ #ifdef USE_SERIALDRIVER +#undef TTYS0_DEV #undef TTYS1_DEV #undef TTYS2_DEV #undef TTYS3_DEV @@ -101,9 +102,13 @@ #if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART) -/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? ... tty9? */ +/* Which UART/USART with be ttyS0/console and which ttyS1? ttyS2? ttyS3? ... + * ttyS9? + */ -/* First pick the console and ttyS0. This could be any of UART0-4, USART0-4 */ +/* First pick the console and ttyS0. This could be any of UART0-4, + * USART0-4. + */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart0port /* UART0 is console */ @@ -249,7 +254,7 @@ #endif /* Pick ttyS3. This could be one of UART2-4 or USART0-4. It can't be - * UART0-1; those have already been assigned to ttsyS0, 1, or 2. One of + * UART0-1; those have already been assigned to ttyS0, 1, or 2. One of * UART2-4 or USART0-4 could also be the console. */ @@ -280,7 +285,7 @@ #endif /* Pick ttyS4. This could be one of UART3-4 or USART0-4. It can't be - * UART0-2; those have already been assigned to ttsyS0-3. One of + * UART0-2; those have already been assigned to ttyS0-3. One of * UART3-4 or USART0-4 could also be the console. */ @@ -308,7 +313,7 @@ #endif /* Pick ttyS5. This could be one of UART4 or USART0-4. It can't be - * UART0-3; those have already been assigned to ttsyS0-4. One of + * UART0-3; those have already been assigned to ttyS0-4. One of * UART4 or USART0-4 could also be the console. */ @@ -333,7 +338,7 @@ #endif /* Pick ttyS6. This could be one of USART0-4. It can't be UART0-4; - * those have already been assigned to ttsyS0-5. One of USART0-4 + * those have already been assigned to ttyS0-5. One of USART0-4 * could also be the console. */ @@ -355,7 +360,7 @@ #endif /* Pick ttyS7. This could be one of USART1-4. It can't be UART0-4 - * or USART0; those have already been assigned to ttsyS0-5. One of + * or USART0; those have already been assigned to ttyS0-5. One of * USART1-4 could also be the console. */ @@ -374,7 +379,7 @@ #endif /* Pick ttyS8. This could be one of USART2-4. It can't be UART0-4 - * or USART0-1; those have already been assigned to ttsyS0-5. One of + * or USART0-1; those have already been assigned to ttyS0-5. One of * USART2-4 could also be the console. */ @@ -390,7 +395,7 @@ #endif /* Pick ttyS9. This could be one of USART3-4. It can't be UART0-4 - * or USART0-2; those have already been assigned to ttsyS0-8. One of + * or USART0-2; those have already been assigned to ttyS0-8. One of * USART3-4 could also be the console. */ @@ -402,7 +407,7 @@ # define USART4_ASSIGNED 1 #endif - /* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */ +/* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */ #define SAM_USART_CLOCK BOARD_USART_FREQUENCY /* Frequency of the USART clock */ #define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ @@ -413,6 +418,7 @@ struct up_dev_s { + xcpt_t handler; /* Interrupt handler */ uint32_t usartbase; /* Base address of USART registers */ uint32_t baud; /* Configured baud */ uint32_t sr; /* Saved status bits */ @@ -429,11 +435,42 @@ struct up_dev_s * Private Function Prototypes ****************************************************************************/ +static int up_interrupt(struct uart_dev_s *dev); +#ifdef CONFIG_SAMA5_UART0 +static int up_uart0_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMA5_UART1 +static int up_uart1_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMA5_UART2 +static int up_uart2_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMA5_UART3 +static int up_uart3_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_SAMA5_UART4 +static int up_uart4_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART0_ISUART +static int up_usart0_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART1_ISUART +static int up_usart1_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART2_ISUART +static int up_usart2_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART3_ISUART +static int up_usart3_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_USART4_ISUART +static int up_usart4_interrupt(int irq, void *context); +#endif + static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); @@ -524,6 +561,7 @@ static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; static struct up_dev_s g_uart0priv = { + .handler = up_uart0_interrupt, .usartbase = SAM_UART0_VBASE, .baud = CONFIG_UART0_BAUD, .irq = SAM_IRQ_UART0, @@ -564,6 +602,7 @@ static uart_dev_t g_uart0port = static struct up_dev_s g_uart1priv = { + .handler = up_uart1_interrupt, .usartbase = SAM_UART1_VBASE, .baud = CONFIG_UART1_BAUD, .irq = SAM_IRQ_UART1, @@ -604,6 +643,7 @@ static uart_dev_t g_uart1port = static struct up_dev_s g_uart2priv = { + .handler = up_uart2_interrupt, .usartbase = SAM_UART2_VBASE, .baud = CONFIG_UART2_BAUD, .irq = SAM_IRQ_UART2, @@ -644,6 +684,7 @@ static uart_dev_t g_uart2port = static struct up_dev_s g_uart3priv = { + .handler = up_uart3_interrupt, .usartbase = SAM_UART3_VBASE, .baud = CONFIG_UART3_BAUD, .irq = SAM_IRQ_UART3, @@ -684,6 +725,7 @@ static uart_dev_t g_uart3port = static struct up_dev_s g_uart4priv = { + .handler = up_uart4_interrupt, .usartbase = SAM_UART4_VBASE, .baud = CONFIG_UART4_BAUD, .irq = SAM_IRQ_UART4, @@ -714,6 +756,7 @@ static uart_dev_t g_uart4port = #ifdef CONFIG_USART0_ISUART static struct up_dev_s g_usart0priv = { + .handler = up_usart0_interrupt, .usartbase = SAM_USART0_VBASE, .baud = CONFIG_USART0_BAUD, .irq = SAM_IRQ_USART0, @@ -747,6 +790,7 @@ static uart_dev_t g_usart0port = #ifdef CONFIG_USART1_ISUART static struct up_dev_s g_usart1priv = { + .handler = up_usart1_interrupt, .usartbase = SAM_USART1_VBASE, .baud = CONFIG_USART1_BAUD, .irq = SAM_IRQ_USART1, @@ -780,6 +824,7 @@ static uart_dev_t g_usart1port = #ifdef CONFIG_USART2_ISUART static struct up_dev_s g_usart2priv = { + .handler = up_usart2_interrupt, .usartbase = SAM_USART2_VBASE, .baud = CONFIG_USART2_BAUD, .irq = SAM_IRQ_USART2, @@ -813,6 +858,7 @@ static uart_dev_t g_usart2port = #ifdef CONFIG_USART3_ISUART static struct up_dev_s g_usart3priv = { + .handler = up_usart3_interrupt, .usartbase = SAM_USART3_VBASE, .baud = CONFIG_USART3_BAUD, .irq = SAM_IRQ_USART3, @@ -846,6 +892,7 @@ static uart_dev_t g_usart3port = #ifdef CONFIG_USART4_ISUART static struct up_dev_s g_usart4priv = { + .handler = up_uart4_interrupt, .usartbase = SAM_USART4_VBASE, .baud = CONFIG_USART4_BAUD, .irq = SAM_IRQ_USART4, @@ -932,6 +979,131 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr) irqrestore(flags); } +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the common USART interrupt handler. It should call + * uart_transmitchars or uart_receivechar to perform the appropriate + * data transfers. + * + ****************************************************************************/ + +static int up_interrupt(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + uint32_t pending; + uint32_t imr; + int passes; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct up_dev_s*)dev->priv; + + /* Loop until there are no characters to be transferred or, until we have + * been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ + + priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET); /* Save for error reporting */ + imr = up_serialin(priv, SAM_UART_IMR_OFFSET); /* Interrupt mask */ + pending = priv->sr & imr; /* Mask out disabled interrupt sources */ + + /* Handle an incoming, receive byte. RXRDY: At least one complete character + * has been received and US_RHR has not yet been read. + */ + + if ((pending & UART_INT_RXRDY) != 0) + { + /* Received data ready... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes. XRDY: There is no character in the + * US_THR. + */ + + if ((pending & UART_INT_TXRDY) != 0) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +#ifdef CONFIG_SAMA5_UART0 +static int up_uart0_interrupt(int irq, void *context) +{ + return up_interrupt(&g_uart0port); +} +#endif +#ifdef CONFIG_SAMA5_UART1 +static int up_uart1_interrupt(int irq, void *context) +{ + return up_interrupt(&g_uart1port); +} +#endif +#ifdef CONFIG_SAMA5_UART2 +static int up_uart2_interrupt(int irq, void *context) +{ + return up_interrupt(&g_uart2port); +} +#endif +#ifdef CONFIG_SAMA5_UART3 +static int up_uart3_interrupt(int irq, void *context) +{ + return up_interrupt(&g_uart3port); +} +#endif +#ifdef CONFIG_SAMA5_UART4 +static int up_uart4_interrupt(int irq, void *context) +{ + return up_interrupt(&g_uart4port); +} +#endif +#ifdef CONFIG_USART0_ISUART +static int up_usart0_interrupt(int irq, void *context) +{ + return up_interrupt(&g_usart0port); +} +#endif +#ifdef CONFIG_USART1_ISUART +static int up_usart1_interrupt(int irq, void *context) +{ + return up_interrupt(&g_usart1port); +} +#endif +#ifdef CONFIG_USART2_ISUART +static int up_usart2_interrupt(int irq, void *context) +{ + return up_interrupt(&g_usart2port); +} +#endif +#ifdef CONFIG_USART3_ISUART +static int up_usart3_interrupt(int irq, void *context) +{ + return up_interrupt(&g_usart3port); +} +#endif +#ifdef CONFIG_USART4_ISUART +static int up_usart4_interrupt(int irq, void *context) +{ + return up_interrupt(&g_usart4port); +} +#endif + /**************************************************************************** * Name: up_setup * @@ -1121,7 +1293,7 @@ static int up_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, up_interrupt); + ret = irq_attach(priv->irq, priv->handler); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -1151,146 +1323,6 @@ static void up_detach(struct uart_dev_s *dev) irq_detach(priv->irq); } -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the USART interrupt handler. It will be invoked when an - * interrupt received on the 'irq' It should call uart_transmitchars or - * uart_receivechar to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'irq' number into the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context) -{ - struct uart_dev_s *dev = NULL; - struct up_dev_s *priv; - uint32_t pending; - uint32_t imr; - int passes; - bool handled; - -#ifdef CONFIG_SAMA5_UART0 - if (g_uart0priv.irq == irq) - { - dev = &g_uart0port; - } - else -#endif -#ifdef CONFIG_SAMA5_UART1 - if (g_uart1priv.irq == irq) - { - dev = &g_uart1port; - } - else -#endif -#ifdef CONFIG_SAMA5_UART2 - if (g_uart2priv.irq == irq) - { - dev = &g_uart2port; - } - else -#endif -#ifdef CONFIG_SAMA5_UART3 - if (g_uart3priv.irq == irq) - { - dev = &g_uart3port; - } - else -#endif -#ifdef CONFIG_SAMA5_UART4 - if (g_uart4priv.irq == irq) - { - dev = &g_uart4port; - } - else -#endif -#ifdef CONFIG_USART0_ISUART - if (g_usart0priv.irq == irq) - { - dev = &g_usart0port; - } - else -#endif -#ifdef CONFIG_USART1_ISUART - if (g_usart1priv.irq == irq) - { - dev = &g_usart1port; - } - else -#endif -#ifdef CONFIG_USART2_ISUART - if (g_usart2priv.irq == irq) - { - dev = &g_usart2port; - } - else -#endif -#ifdef CONFIG_USART3_ISUART - if (g_usart3priv.irq == irq) - { - dev = &g_usart3port; - } - else -#endif -#ifdef CONFIG_USART4_ISUART - if (g_usart4priv.irq == irq) - { - dev = &g_usart4port; - } - else -#endif - { - PANIC(); - } - - priv = (struct up_dev_s*)dev->priv; - - /* Loop until there are no characters to be transferred or, until we have - * been looping for a long time. - */ - - handled = true; - for (passes = 0; passes < 256 && handled; passes++) - { - handled = false; - - /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ - - priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET); /* Save for error reporting */ - imr = up_serialin(priv, SAM_UART_IMR_OFFSET); /* Interrupt mask */ - pending = priv->sr & imr; /* Mask out disabled interrupt sources */ - - /* Handle an incoming, receive byte. RXRDY: At least one complete character - * has been received and US_RHR has not yet been read. - */ - - if ((pending & UART_INT_RXRDY) != 0) - { - /* Received data ready... process incoming bytes */ - - uart_recvchars(dev); - handled = true; - } - - /* Handle outgoing, transmit bytes. XRDY: There is no character in the - * US_THR. - */ - - if ((pending & UART_INT_TXRDY) != 0) - { - /* Transmit data register empty ... process outgoing bytes */ - - uart_xmitchars(dev); - handled = true; - } - } - - return OK; -} - /**************************************************************************** * Name: up_ioctl * @@ -1641,14 +1673,12 @@ static bool up_txempty(struct uart_dev_s *dev) return ((up_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); } -#endif /* SAMA5_HAVE_UART || SAMA5_HAVE_USART */ - /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: sam_earlyserialinit + * Name: uart_earlyserialinit * * Description: * Performs the low level USART initialization early in debug so that the @@ -1657,7 +1687,7 @@ static bool up_txempty(struct uart_dev_s *dev) * ****************************************************************************/ -void sam_earlyserialinit(void) +void uart_earlyserialinit(void) { /* NOTE: All PIO configuration for the USARTs was performed in * sam_lowsetup @@ -1698,26 +1728,26 @@ void sam_earlyserialinit(void) /* Configuration whichever one is the console */ -#ifdef SAMA5_HAVE_SERIAL_CONSOLE +#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) CONSOLE_DEV.isconsole = true; up_setup(&CONSOLE_DEV); #endif } /**************************************************************************** - * Name: up_serialinit + * Name: uart_serialinit * * Description: - * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. + * Register UART/USART serial console and serial ports. This assumes that + * uart_earlyserialinit was called previously. * ****************************************************************************/ -void up_serialinit(void) +void uart_serialinit(void) { /* Register the console */ -#ifdef SAMA5_HAVE_SERIAL_CONSOLE +#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) (void)uart_register("/dev/console", &CONSOLE_DEV); #endif @@ -1753,12 +1783,7 @@ void up_serialinit(void) #ifdef TTYS9_DEV (void)uart_register("/dev/ttyS9", &TTYS9_DEV); #endif - -/* Register the DBGU as well */ - -#ifdef CONFIG_SAMA5_DBGU - sam_dbgu_register(); -#endif } +#endif /* SAMA5_HAVE_UART || SAMA5_HAVE_USART */ #endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/sama5/sam_serial.h b/arch/arm/src/sama5/sam_serial.h index 68cde323158..63cb5ab792f 100644 --- a/arch/arm/src/sama5/sam_serial.h +++ b/arch/arm/src/sama5/sam_serial.h @@ -43,6 +43,7 @@ #include #include "up_internal.h" +#include "sam_config.h" /**************************************************************************** * Pre-processor Definitions @@ -89,6 +90,60 @@ extern "C" void sam_earlyserialinit(void); #endif +/**************************************************************************** + * Name: uart_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) && (defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART)) +void uart_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: flexus_earlyserialinit + * + * Description: + * Performs the low level Flexcom USART initialization early so that the + * Flexcom serial console will be available during bootup. This must be + * called before flexus_serialinit. + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) && defined(SAMA5_HAVE_FLEXCOM_USART) +void flexus_earlyserialinit(void); +#endif + +/**************************************************************************** + * Name: uart_serialinit + * + * Description: + * Register UART/USART serial console and serial ports. This assumes that + * uart_earlyserialinit was called previously. + * + ****************************************************************************/ + +#if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART) +void uart_serialinit(void); +#endif + +/**************************************************************************** + * Name: flexus_serialinit + * + * Description: + * Register Flexcom serial console and serial ports. This assumes that + * flexus_earlyserialinit was called previously. + * + ****************************************************************************/ + +#if defined(USE_EARLYSERIALINIT) && defined(SAMA5_HAVE_FLEXCOM_USART) +void flexus_serialinit(void); +#endif + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/sama5/sam_serialinit.c b/arch/arm/src/sama5/sam_serialinit.c new file mode 100644 index 00000000000..53b25b906b2 --- /dev/null +++ b/arch/arm/src/sama5/sam_serialinit.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * arch/arm/src/sama5/sam_serialinit.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "sam_config.h" +#include "sam_dbgu.h" +#include "sam_serial.h" + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_earlyserialinit + * + * Description: + * Performs the low level serial initialization early so that the serial + * console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +void sam_earlyserialinit(void) +{ + /* NOTE: All PIO configuration for the USARTs was performed in + * sam_lowsetup + */ + +#if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART) + /* Initialize UART/USART drivers */ + + uart_serialinit(); +#endif + +#ifdef SAMA5_HAVE_FLEXCOM_USART + /* Initialize Flexcom USARTs */ + + flexus_earlyserialinit(); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register all serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#if defined(SAMA5_HAVE_UART) || defined(SAMA5_HAVE_USART) + /* Register UART/USART drivers */ + + uart_serialinit(); +#endif + +#ifdef SAMA5_HAVE_FLEXCOM_USART + /* Register Flexcom USARTs */ + + flexus_earlyserialinit(); +#endif + +/* Register the DBGU as well */ + +#ifdef CONFIG_SAMA5_DBGU + sam_dbgu_register(); +#endif +} + +#endif /* USE_SERIALDRIVER */