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boards/xtensa/esp32: Update some old information in README.txt files.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
committed by
Xiang Xiao
parent
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commit
b198c63512
@@ -619,13 +619,6 @@ OpenOCD for the ESP32
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will be written. ROM bootloader expects to find an application (or second stage
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will be written. ROM bootloader expects to find an application (or second stage
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bootloader) image at offset 0x1000, so we are writing the binary there.
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bootloader) image at offset 0x1000, so we are writing the binary there.
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Clocking
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--------
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Right now, the NuttX port depends on the bootloader to initialize hardware,
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including basic (slow) clocking. If I had the clock configuration logic,
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would I be able to run directly out of IRAM without a bootloader? That
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might be a simpler bring-up.
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Sample OpenOCD Debug Steps
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Sample OpenOCD Debug Steps
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--------------------------
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--------------------------
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I did the initial bring-up using the IRAM configuration and OpenOCD. Here
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I did the initial bring-up using the IRAM configuration and OpenOCD. Here
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@@ -886,12 +879,7 @@ A new image "esp32_qemu_image.bin" will be created. It can be run as:
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Things to Do
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Things to Do
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============
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============
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1. There is no clock initialization logic in place. This depends on logic in
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1. I did not implement the lazy co-processor save logic supported by Xtensa.
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Espressif libraries. The board comes up using that basic 40 MHz crystal
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for clocking. Getting to 80 MHz will require clocking initialization in
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esp32_clockconfig.c.
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2. I did not implement the lazy co-processor save logic supported by Xtensa.
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That logic works like this:
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That logic works like this:
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a. CPENABLE is set to zero on each context switch, disabling all co-
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a. CPENABLE is set to zero on each context switch, disabling all co-
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@@ -905,14 +893,14 @@ Things to Do
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be saved and restored even if the co-processor was never used, and (2)
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be saved and restored even if the co-processor was never used, and (2)
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tasks must explicitly enable and disable co-processors.
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tasks must explicitly enable and disable co-processors.
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3. Currently the Xtensa port copies register state save information from
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2. Currently the Xtensa port copies register state save information from
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the stack into the TCB. A more efficient alternative would be to just
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the stack into the TCB. A more efficient alternative would be to just
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save a pointer to a register state save area in the TCB. This would
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save a pointer to a register state save area in the TCB. This would
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add some complexity to signal handling and also also the
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add some complexity to signal handling and also also the
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up_initialstate(). But the performance improvement might be worth
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up_initialstate(). But the performance improvement might be worth
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the effort.
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the effort.
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4. See SMP-related issues above
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3. See SMP-related issues above
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5. See OpenOCD for the ESP32 above
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4. See OpenOCD for the ESP32 above
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@@ -63,10 +63,6 @@ Ethernet
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ESP32 GPIO PHY Chip GPIO
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ESP32 GPIO PHY Chip GPIO
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IO5 <--> Reset_N
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IO5 <--> Reset_N
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Espressif has an official Ethernet development board:
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https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-ethernet-kit.html
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Using QEMU:
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Using QEMU:
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==========
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==========
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@@ -99,4 +99,3 @@ External devices:
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------
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------
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When using BMP180 (enabling CONFIG_SENSORS_BMP180), it's expected this device is wired to I2C0 bus.
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When using BMP180 (enabling CONFIG_SENSORS_BMP180), it's expected this device is wired to I2C0 bus.
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The current bring-up routines doesn't allow BMP180 device to be used in I2C1 bus.
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