Xtensa ESP32: Fix a duplicate in Kconfig files. Level 1 should return via RFE.

arch/xtensa/Kconfig

@@ -22,6 +22,10 @@ config ARCH_CHIP_ESP32
 		of two CPUs is symmetric, meaning they use the same addresses to
 		access the same memory.
 
+		The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
+		"application"), however for most purposes the two CPUs are
+		interchangeable.
+
 endchoice # XTENSA chip selection
 
 config ARCH_FAMILY_LX6

arch/xtensa/src/common/xtensa_context.S

@@ -371,10 +371,15 @@ xtensa_context_restore:
 	l32i	a0, a2, (4 * REG_PS)			/* Restore PS */
 	wsr		a0, PS
 	l32i	a0, a2, (4 * REG_PC)			/* Set up for RFE */
-	rsr		a0, EPC
+	rsr		a0, EPC_1
 	l32i	a0, a2, (4 * REG_A0)			/* Restore a0 */
 	l32i	a2, a2, (4 * REG_A2)			/* Restore A2 */
 
+	/* Return from exception. RFE returns from either the UserExceptionVector
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
+	 */
+
 	rfe										/* And return from "exception" */
 
 	.size	xtensa_context_restore, . - xtensa_context_restore

arch/xtensa/src/common/xtensa_int_handlers.S

@@ -292,11 +292,12 @@ _xtensa_level1_handler:
 	l32i	a2, a2, (4 * REG_A2)			/* Retrieve interruptee's A2 */
 	rsync									/* Ensure EPS and EPC written */
 
-	/* Return from interrupt.  RFI  restores the PS from EPS_1 and jumps to
+	/* Return from exception. RFE returns from either the UserExceptionVector
-	 * the address in EPC_1.
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
 	 */
 
-	rfi		1
+	rfe										/* And return from "exception" */
 
 /****************************************************************************
  * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS.

arch/xtensa/src/common/xtensa_user_handler.S

@@ -372,9 +372,9 @@ _xtensa_syscall_handler:
 	l32i	a2, a2, (4 * REG_A2)			/* Retrieve interruptee's A2 */
 	rsync									/* Ensure EPS and EPC written */
 
-	/* Return from exception.  RFE returns from either the UserExceptionVector
+	/* Return from exception. RFE returns from either the UserExceptionVector
-	 * or the KernelExceptionVector. RFE sets PS.EXCM back to 0 and then jumps
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
-	 * to the address in EPC[1].
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
 	 */
 
 	rfe

arch/xtensa/src/lx6/Kconfig

@@ -5,27 +5,4 @@
 
 if ARCH_CHIP_LX6
 
-choice
-	prompt "LX6 implementation"
-	default ARCH_CHIP_ESP32
-
-config ARCH_CHIP_ESP32
-	bool "Expressif ESP32"
-	---help---
-		The ESP32 is a dual-core system with two Harvard Architecture Xtensa
-		LX6 CPUs. All embedded memory, external memory and peripherals are
-		located on the data bus and/or the instruction bus of these CPUs.
-		With some minor exceptions the address mapping of two CPUs is
-		symmetric, meaning they use the same addresses to access the same
-		memory. Multiple peripherals in the system can access embedded
-		memory via DMA.
-
-		The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
-		"application"), however for most purposes the two CPUs are
-		interchangeable.
-
-endchoice # LX6 implementation
-
-source arch/xtensa/src/esp32/Kconfig
-
 endif # ARCH_CHIP_LX6