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SAMA5 UDPHS: Support USPHS clock configuration

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This commit is contained in:
Gregory Nutt
2013-09-01 11:29:51 -06:00
parent 27d6d3045d
commit ad6c760522
2 changed files with 10 additions and 4 deletions
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configs/sama5d3x-ek/include/board_384mhz.h
+6 -3
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@@ -100,7 +100,9 @@
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
#ifdef CONFIG_SAMA5_OHCI #if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* For OHCI Full-speed operations, the user has to perform the following: /* For OHCI Full-speed operations, the user has to perform the following:
* *
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER
@@ -132,8 +134,9 @@
* frame rate. I cannot explain the factor of 2 difference. * frame rate. I cannot explain the factor of 2 difference.
*/ */
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA # undef BOARD_USE_UPLL /* Use PLLA as source clock */
# define BOARD_OHCI_DIVIDER (7) # define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */
# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */
#endif #endif
/* Resulting frequencies */ /* Resulting frequencies */
configs/sama5d3x-ek/include/board_396mhz.h
+4 -1
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@@ -106,7 +106,9 @@
#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */ #define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */
#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */ #define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
#ifdef CONFIG_SAMA5_EHCI #if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
defined(CONFIG_SAMA5_UDPHS)
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded /* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
@@ -132,6 +134,7 @@
* driver is initialized. * driver is initialized.
*/ */
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
#endif #endif