Trivial stylistic changes from review of last PR

This commit is contained in:
Gregory Nutt
2016-10-14 11:12:49 -06:00
parent e3c553e58d
commit ad6856c931
2 changed files with 25 additions and 26 deletions
+8 -11
View File
@@ -128,7 +128,7 @@ struct stm32l4_pwmchan_s
uint8_t channel; /* Timer output channel: {1,..4} */ uint8_t channel; /* Timer output channel: {1,..4} */
uint32_t pincfg; /* Output pin configuration */ uint32_t pincfg; /* Output pin configuration */
enum stm32l4_chanmode_e mode; enum stm32l4_chanmode_e mode;
uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/ uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/
}; };
/* This structure represents the state of one PWM timer */ /* This structure represents the state of one PWM timer */
@@ -996,10 +996,10 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
/* Handle channel specific setup */ /* Handle channel specific setup */
ccenable = 0; ccenable = 0;
ccnenable = 0; ccnenable = 0;
ocmode1 = 0; ocmode1 = 0;
ocmode2 = 0; ocmode2 = 0;
#ifdef CONFIG_PWM_MULTICHAN #ifdef CONFIG_PWM_MULTICHAN
for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
@@ -1104,7 +1104,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
/* Conditionnaly enable the complementary output */ /* Conditionnaly enable the complementary output */
if(compout) if (compout)
{ {
ccnenable |= ATIM_CCER_CC1NE; ccnenable |= ATIM_CCER_CC1NE;
} }
@@ -1134,7 +1134,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
/* Conditionnaly enable the complementary output */ /* Conditionnaly enable the complementary output */
if(compout) if (compout)
{ {
ccnenable |= ATIM_CCER_CC2NE; ccnenable |= ATIM_CCER_CC2NE;
} }
@@ -1164,7 +1164,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
/* Conditionnaly enable the complementary output */ /* Conditionnaly enable the complementary output */
if(compout) if (compout)
{ {
ccnenable |= ATIM_CCER_CC3NE; ccnenable |= ATIM_CCER_CC3NE;
} }
@@ -1289,14 +1289,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv,
*/ */
ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP); ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP);
ccer |= ccnenable; ccer |= ccnenable;
} }
else else
#endif #endif
#endif #endif
{ {
ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); //Not sure why ?? ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); /* Not sure why? */
} }
/* Save the modified register values */ /* Save the modified register values */
@@ -1783,7 +1782,6 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
pwminfo("pincfg: %08x\n", pincfg); pwminfo("pincfg: %08x\n", pincfg);
pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
pincfg |= GPIO_INPUT | GPIO_FLOAT; pincfg |= GPIO_INPUT | GPIO_FLOAT;
stm32l4_configgpio(pincfg); stm32l4_configgpio(pincfg);
@@ -1795,7 +1793,6 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
pwminfo("npincfg: %08x\n", pincfg); pwminfo("npincfg: %08x\n", pincfg);
pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
pincfg |= GPIO_INPUT | GPIO_FLOAT; pincfg |= GPIO_INPUT | GPIO_FLOAT;
stm32l4_configgpio(pincfg); stm32l4_configgpio(pincfg);
+17 -15
View File
@@ -96,14 +96,15 @@ int board_pwm_setup(void)
if (!initialized) if (!initialized)
{ {
/* Call stm32l4_pwminitialize() to get an instance of the PWM interface */ /* Call stm32l4_pwminitialize() to get an instance of the PWM interface */
/* PWM
*
* The Nucleo-l476rg has no real on-board PWM devices, but the board can be
* configured to output a pulse train using TIM1 or 8, or others (see board.h).
* Let's figure out which the user has configured.
*/
# if defined(CONFIG_STM32L4_TIM1_PWM) /* PWM
*
* The Nucleo-l476rg has no real on-board PWM devices, but the board can be
* configured to output a pulse train using TIM1 or 8, or others (see board.h).
* Let's figure out which the user has configured.
*/
#if defined(CONFIG_STM32L4_TIM1_PWM)
pwm = stm32l4_pwminitialize(1); pwm = stm32l4_pwminitialize(1);
if (!pwm) if (!pwm)
{ {
@@ -121,7 +122,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM2_PWM) #if defined(CONFIG_STM32L4_TIM2_PWM)
pwm = stm32l4_pwminitialize(2); pwm = stm32l4_pwminitialize(2);
if (!pwm) if (!pwm)
{ {
@@ -139,7 +140,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM3_PWM) #if defined(CONFIG_STM32L4_TIM3_PWM)
pwm = stm32l4_pwminitialize(3); pwm = stm32l4_pwminitialize(3);
if (!pwm) if (!pwm)
{ {
@@ -157,7 +158,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM4_PWM) #if defined(CONFIG_STM32L4_TIM4_PWM)
pwm = stm32l4_pwminitialize(4); pwm = stm32l4_pwminitialize(4);
if (!pwm) if (!pwm)
{ {
@@ -175,7 +176,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM5_PWM) #if defined(CONFIG_STM32L4_TIM5_PWM)
pwm = stm32l4_pwminitialize(5); pwm = stm32l4_pwminitialize(5);
if (!pwm) if (!pwm)
{ {
@@ -193,7 +194,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM8_PWM) #if defined(CONFIG_STM32L4_TIM8_PWM)
pwm = stm32l4_pwminitialize(8); pwm = stm32l4_pwminitialize(8);
if (!pwm) if (!pwm)
{ {
@@ -211,7 +212,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM15_PWM) #if defined(CONFIG_STM32L4_TIM15_PWM)
pwm = stm32l4_pwminitialize(15); pwm = stm32l4_pwminitialize(15);
if (!pwm) if (!pwm)
{ {
@@ -229,7 +230,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM16_PWM) #if defined(CONFIG_STM32L4_TIM16_PWM)
pwm = stm32l4_pwminitialize(16); pwm = stm32l4_pwminitialize(16);
if (!pwm) if (!pwm)
{ {
@@ -247,7 +248,7 @@ int board_pwm_setup(void)
} }
#endif #endif
# if defined(CONFIG_STM32L4_TIM17_PWM) #if defined(CONFIG_STM32L4_TIM17_PWM)
pwm = stm32l4_pwminitialize(17); pwm = stm32l4_pwminitialize(17);
if (!pwm) if (!pwm)
{ {
@@ -273,3 +274,4 @@ int board_pwm_setup(void)
} }
#endif /* CONFIG_PWM */ #endif /* CONFIG_PWM */