diff --git a/arch/arm/src/stm32f0/chip/stm32f0_dma.h b/arch/arm/src/stm32f0/chip/stm32f0_dma.h index b362d24d593..a0d82628fba 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_dma.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_dma.h @@ -434,7 +434,7 @@ #define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN1, 5) #define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32F0_DMA1_CHAN7, 5) -/* UART */ +/* USARTs */ #define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32F0_DMA1_CHAN5, 2) #define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32F0_DMA2_CHAN7, 2) @@ -447,10 +447,10 @@ #define DMACHAN_USART3_RX DMACHAN_SETTING(STM32F0_DMA1_CHAN3, 1) #define DMACHAN_USART3_TX DMACHAN_SETTING(STM32F0_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2) +#define DMACHAN_USART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2) +#define DMACHAN_USART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN3, 2) +#define DMACHAN_USART5_RX DMACHAN_SETTING(STM32F0_DMA2_CHAN2, 2) +#define DMACHAN_USART5_TX DMACHAN_SETTING(STM32F0_DMA2_CHAN1, 2) #endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_DMA_H */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h index aed20d16081..613020b8300 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_rcc.h @@ -222,8 +222,8 @@ #define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ #define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ #define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ -#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */ -#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */ +#define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */ +#define RCC_APB1RSTR_USART5RST (1 << 20) /* Bit 20: USART 5 reset */ #define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ #define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ #define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */ @@ -275,8 +275,8 @@ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ #define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ #define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ -#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */ -#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */ +#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */ +#define RCC_APB1ENR_USART5EN (1 << 20) /* Bit 20: USART 5 clock enable */ #define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ #define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ #define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */ diff --git a/arch/arm/src/stm32f0/chip/stm32f0_uart.h b/arch/arm/src/stm32f0/chip/stm32f0_uart.h index 3b7ff61da9f..62af4d5ca19 100644 --- a/arch/arm/src/stm32f0/chip/stm32f0_uart.h +++ b/arch/arm/src/stm32f0/chip/stm32f0_uart.h @@ -108,73 +108,31 @@ #endif #if STM32F0_NUSART > 3 -# define STM32F0_UART4_CR1 (STM32F0_UART4_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_UART4_CR2 (STM32F0_UART4_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_UART4_CR3 (STM32F0_UART4_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_UART4_BRR (STM32F0_UART4_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_UART4_GTPR (STM32F0_UART4_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_UART4_RTOR (STM32F0_UART4_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_UART4_RQR (STM32F0_UART4_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_UART4_ISR (STM32F0_UART4_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_UART4_ICR (STM32F0_UART4_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_UART4_RDR (STM32F0_UART4_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_UART4_TDR (STM32F0_UART4_BASE+STM32F0_USART_TDR_OFFSET) +# define STM32F0_USART4_CR1 (STM32F0_USART4_BASE+STM32F0_USART_CR1_OFFSET) +# define STM32F0_USART4_CR2 (STM32F0_USART4_BASE+STM32F0_USART_CR2_OFFSET) +# define STM32F0_USART4_CR3 (STM32F0_USART4_BASE+STM32F0_USART_CR3_OFFSET) +# define STM32F0_USART4_BRR (STM32F0_USART4_BASE+STM32F0_USART_BRR_OFFSET) +# define STM32F0_USART4_GTPR (STM32F0_USART4_BASE+STM32F0_USART_GTPR_OFFSET) +# define STM32F0_USART4_RTOR (STM32F0_USART4_BASE+STM32F0_USART_RTOR_OFFSET) +# define STM32F0_USART4_RQR (STM32F0_USART4_BASE+STM32F0_USART_RQR_OFFSET) +# define STM32F0_USART4_ISR (STM32F0_USART4_BASE+STM32F0_USART_ISR_OFFSET) +# define STM32F0_USART4_ICR (STM32F0_USART4_BASE+STM32F0_USART_ICR_OFFSET) +# define STM32F0_USART4_RDR (STM32F0_USART4_BASE+STM32F0_USART_RDR_OFFSET) +# define STM32F0_USART4_TDR (STM32F0_USART4_BASE+STM32F0_USART_TDR_OFFSET) #endif #if STM32F0_NUSART > 4 -# define STM32F0_UART5_CR1 (STM32F0_UART5_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_UART5_CR2 (STM32F0_UART5_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_UART5_CR3 (STM32F0_UART5_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_UART5_BRR (STM32F0_UART5_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_UART5_GTPR (STM32F0_UART5_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_UART5_RTOR (STM32F0_UART5_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_UART5_RQR (STM32F0_UART5_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_UART5_ISR (STM32F0_UART5_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_UART5_ICR (STM32F0_UART5_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_UART5_RDR (STM32F0_UART5_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_UART5_TDR (STM32F0_UART5_BASE+STM32F0_USART_TDR_OFFSET) -#endif - -#if STM32F0_NUSART > 5 -# define STM32F0_UART6_CR1 (STM32F0_UART6_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_UART6_CR2 (STM32F0_UART6_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_UART6_CR3 (STM32F0_UART6_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_UART6_BRR (STM32F0_UART6_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_UART6_GTPR (STM32F0_UART6_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_UART6_RTOR (STM32F0_UART6_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_UART6_RQR (STM32F0_UART6_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_UART6_ISR (STM32F0_UART6_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_UART6_ICR (STM32F0_UART6_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_UART6_RDR (STM32F0_UART6_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_UART6_TDR (STM32F0_UART6_BASE+STM32F0_USART_TDR_OFFSET) -#endif - -#if STM32F0_NUSART > 6 -# define STM32F0_UART7_CR1 (STM32F0_UART7_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_UART7_CR2 (STM32F0_UART7_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_UART7_CR3 (STM32F0_UART7_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_UART7_BRR (STM32F0_UART7_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_UART7_GTPR (STM32F0_UART7_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_UART7_RTOR (STM32F0_UART7_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_UART7_RQR (STM32F0_UART7_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_UART7_ISR (STM32F0_UART7_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_UART7_ICR (STM32F0_UART7_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_UART7_RDR (STM32F0_UART7_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_UART7_TDR (STM32F0_UART7_BASE+STM32F0_USART_TDR_OFFSET) -#endif - -#if STM32F0_NUSART > 7 -# define STM32F0_UART8_CR1 (STM32F0_UART8_BASE+STM32F0_USART_CR1_OFFSET) -# define STM32F0_UART8_CR2 (STM32F0_UART8_BASE+STM32F0_USART_CR2_OFFSET) -# define STM32F0_UART8_CR3 (STM32F0_UART8_BASE+STM32F0_USART_CR3_OFFSET) -# define STM32F0_UART8_BRR (STM32F0_UART8_BASE+STM32F0_USART_BRR_OFFSET) -# define STM32F0_UART8_GTPR (STM32F0_UART8_BASE+STM32F0_USART_GTPR_OFFSET) -# define STM32F0_UART8_RTOR (STM32F0_UART8_BASE+STM32F0_USART_RTOR_OFFSET) -# define STM32F0_UART8_RQR (STM32F0_UART8_BASE+STM32F0_USART_RQR_OFFSET) -# define STM32F0_UART8_ISR (STM32F0_UART8_BASE+STM32F0_USART_ISR_OFFSET) -# define STM32F0_UART8_ICR (STM32F0_UART8_BASE+STM32F0_USART_ICR_OFFSET) -# define STM32F0_UART8_RDR (STM32F0_UART8_BASE+STM32F0_USART_RDR_OFFSET) -# define STM32F0_UART8_TDR (STM32F0_UART8_BASE+STM32F0_USART_TDR_OFFSET) +# define STM32F0_USART5_CR1 (STM32F0_USART5_BASE+STM32F0_USART_CR1_OFFSET) +# define STM32F0_USART5_CR2 (STM32F0_USART5_BASE+STM32F0_USART_CR2_OFFSET) +# define STM32F0_USART5_CR3 (STM32F0_USART5_BASE+STM32F0_USART_CR3_OFFSET) +# define STM32F0_USART5_BRR (STM32F0_USART5_BASE+STM32F0_USART_BRR_OFFSET) +# define STM32F0_USART5_GTPR (STM32F0_USART5_BASE+STM32F0_USART_GTPR_OFFSET) +# define STM32F0_USART5_RTOR (STM32F0_USART5_BASE+STM32F0_USART_RTOR_OFFSET) +# define STM32F0_USART5_RQR (STM32F0_USART5_BASE+STM32F0_USART_RQR_OFFSET) +# define STM32F0_USART5_ISR (STM32F0_USART5_BASE+STM32F0_USART_ISR_OFFSET) +# define STM32F0_USART5_ICR (STM32F0_USART5_BASE+STM32F0_USART_ICR_OFFSET) +# define STM32F0_USART5_RDR (STM32F0_USART5_BASE+STM32F0_USART_RDR_OFFSET) +# define STM32F0_USART5_TDR (STM32F0_USART5_BASE+STM32F0_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ diff --git a/arch/arm/src/stm32f0/stm32f0_lowputc.c b/arch/arm/src/stm32f0/stm32f0_lowputc.c index 16de07e8f28..3fbfe67d249 100644 --- a/arch/arm/src/stm32f0/stm32f0_lowputc.c +++ b/arch/arm/src/stm32f0/stm32f0_lowputc.c @@ -63,14 +63,10 @@ # if defined(CONFIG_USART1_SERIAL_CONSOLE) # define STM32F0_CONSOLE_BASE STM32F0_USART1_BASE # define STM32F0_APBCLOCK STM32F0_PCLK2_FREQUENCY -# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB2ENR -# define STM32F0_CONSOLE_APBEN RCC_APB2ENR_USART1EN # define STM32F0_CONSOLE_BAUD CONFIG_USART1_BAUD # define STM32F0_CONSOLE_BITS CONFIG_USART1_BITS # define STM32F0_CONSOLE_PARITY CONFIG_USART1_PARITY # define STM32F0_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32F0_CONSOLE_TX GPIO_USART1_TX -# define STM32F0_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 # define STM32F0_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) @@ -82,14 +78,10 @@ # elif defined(CONFIG_USART2_SERIAL_CONSOLE) # define STM32F0_CONSOLE_BASE STM32F0_USART2_BASE # define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1 -# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_USART2EN # define STM32F0_CONSOLE_BAUD CONFIG_USART2_BAUD # define STM32F0_CONSOLE_BITS CONFIG_USART2_BITS # define STM32F0_CONSOLE_PARITY CONFIG_USART2_PARITY # define STM32F0_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32F0_CONSOLE_TX GPIO_USART2_TX -# define STM32F0_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 # define STM32F0_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) @@ -101,14 +93,10 @@ # elif defined(CONFIG_USART3_SERIAL_CONSOLE) # define STM32F0_CONSOLE_BASE STM32F0_USART3_BASE # define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1 -# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_USART3EN # define STM32F0_CONSOLE_BAUD CONFIG_USART3_BAUD # define STM32F0_CONSOLE_BITS CONFIG_USART3_BITS # define STM32F0_CONSOLE_PARITY CONFIG_USART3_PARITY # define STM32F0_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32F0_CONSOLE_TX GPIO_USART3_TX -# define STM32F0_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 # define STM32F0_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) @@ -117,39 +105,31 @@ # define STM32F0_CONSOLE_RS485_DIR_POLARITY true # endif # endif -# elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_UART4_BASE +# elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define STM32F0_CONSOLE_BASE STM32F0_USART4_BASE # define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1 -# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32F0_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32F0_CONSOLE_TX GPIO_UART4_TX -# define STM32F0_CONSOLE_RX GPIO_UART4_RX -# ifdef CONFIG_UART4_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) +# define STM32F0_CONSOLE_BAUD CONFIG_USART4_BAUD +# define STM32F0_CONSOLE_BITS CONFIG_USART4_BITS +# define STM32F0_CONSOLE_PARITY CONFIG_USART4_PARITY +# define STM32F0_CONSOLE_2STOP CONFIG_USART4_2STOP +# ifdef CONFIG_USART4_RS485 +# define STM32F0_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) # define STM32F0_CONSOLE_RS485_DIR_POLARITY false # else # define STM32F0_CONSOLE_RS485_DIR_POLARITY true # endif # endif -# elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32F0_CONSOLE_BASE STM32F0_UART5_BASE +# elif defined(CONFIG_USART5_SERIAL_CONSOLE) +# define STM32F0_CONSOLE_BASE STM32F0_USART5_BASE # define STM32F0_APBCLOCK STM32F0_PCLK1_FREQUENCY -# define STM32F0_CONSOLE_APBREG STM32F0_RCC_APB1ENR1 -# define STM32F0_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32F0_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32F0_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32F0_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32F0_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32F0_CONSOLE_TX GPIO_UART5_TX -# define STM32F0_CONSOLE_RX GPIO_UART5_RX -# ifdef CONFIG_UART5_RS485 -# define STM32F0_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) +# define STM32F0_CONSOLE_BAUD CONFIG_USART5_BAUD +# define STM32F0_CONSOLE_BITS CONFIG_USART5_BITS +# define STM32F0_CONSOLE_PARITY CONFIG_USART5_PARITY +# define STM32F0_CONSOLE_2STOP CONFIG_USART5_2STOP +# ifdef CONFIG_USART5_RS485 +# define STM32F0_CONSOLE_RS485_DIR GPIO_USART5_RS485_DIR +# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) # define STM32F0_CONSOLE_RS485_DIR_POLARITY false # else # define STM32F0_CONSOLE_RS485_DIR_POLARITY true @@ -298,22 +278,86 @@ void stm32f0_lowsetup(void) uint32_t cr; #endif -#if defined(HAVE_CONSOLE) - /* Enable USART APB1/2 clock */ + /* Setup clocking and GPIO pins for all configured USARTs */ - modifyreg32(STM32F0_CONSOLE_APBREG, 0, STM32F0_CONSOLE_APBEN); +#ifdef CONFIG_STM32F0_USART1 + /* Enable USART APB2 clock */ + + modifyreg32(STM32F0_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); + + /* Configure RX/TX pins */ + + stm32f0_configgpio(GPIO_USART1_TX); + stm32f0_configgpio(GPIO_USART1_RX); + +#ifdef CONFIG_USART1_RS485 + stm32f0_configgpio(GPIO_USART1_RS485_DIR); + stm32f0_gpiowrite(GPIO_USART1_RS485_DIR, !CONFIG_USART1_RS485_DIR_POLARITY); +#endif #endif -#ifdef STM32F0_CONSOLE_TX - stm32f0_configgpio(STM32F0_CONSOLE_TX); +#ifdef CONFIG_STM32F0_USART2 + /* Enable USART APB1 clock */ + + modifyreg32(STM32F0_RCC_APB1ENR1, 0, RCC_APB1ENR1_USART2EN); + + /* Configure RX/TX pins */ + + stm32f0_configgpio(GPIO_USART2_TX); + stm32f0_configgpio(GPIO_USART2_RX); + +#ifdef CONFIG_USART2_RS485 + stm32f0_configgpio(GPIO_USART2_RS485_DIR); + stm32f0_gpiowrite(GPIO_USART2_RS485_DIR, !CONFIG_USART2_RS485_DIR_POLARITY); #endif -#ifdef STM32F0_CONSOLE_RX - stm32f0_configgpio(STM32F0_CONSOLE_RX); #endif -#ifdef STM32F0_CONSOLE_RS485_DIR - stm32f0_configgpio(STM32F0_CONSOLE_RS485_DIR); - stm32f0_gpiowrite(STM32F0_CONSOLE_RS485_DIR, !STM32F0_CONSOLE_RS485_DIR_POLARITY); +#ifdef CONFIG_STM32F0_USART3 + /* Enable USART APB1 clock */ + + modifyreg32(STM32F0_RCC_APB1ENR1, 0, RCC_APB1ENR1_USART3EN); + + /* Configure RX/TX pins */ + + stm32f0_configgpio(GPIO_USART3_TX); + stm32f0_configgpio(GPIO_USART3_RX); + +#ifdef CONFIG_USART3_RS485 + stm32f0_configgpio(GPIO_USART3_RS485_DIR); + stm32f0_gpiowrite(GPIO_USART3_RS485_DIR, !CONFIG_USART3_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32F0_USART4 + /* Enable USART APB1 clock */ + + modifyreg32(STM32F0_RCC_APB1ENR1, 0, RCC_APB1ENR1_USART4EN); + + /* Configure RX/TX pins */ + + stm32f0_configgpio(GPIO_USART4_TX); + stm32f0_configgpio(GPIO_USART4_RX); + +#ifdef CONFIG_USART4_RS485 + stm32f0_configgpio(GPIO_USART4_RS485_DIR); + stm32f0_gpiowrite(GPIO_USART4_RS485_DIR, !CONFIG_USART4_RS485_DIR_POLARITY); +#endif +#endif + +#ifdef CONFIG_STM32F0_USART5 + /* Enable USART APB1 clock */ + + modifyreg32(STM32F0_RCC_APB1ENR1, 0, RCC_APB1ENR1_USART5EN); + + /* Configure RX/TX pins */ + + stm32f0_configgpio(GPIO_USART5_TX); + stm32f0_configgpio(GPIO_USART5_RX); + +#ifdef CONFIG_USART5_RS485 + stm32f0_configgpio(GPIO_USART5_RS485_DIR); + stm32f0_gpiowrite(GPIO_USART5_RS485_DIR, !CONFIG_USART5_RS485_DIR_POLARITY); +#endif #endif /* Enable and configure the selected console device */ diff --git a/arch/arm/src/stm32f0/stm32f0_serial.c b/arch/arm/src/stm32f0/stm32f0_serial.c index 0423b9ff94f..2d5cd1b996a 100644 --- a/arch/arm/src/stm32f0/stm32f0_serial.c +++ b/arch/arm/src/stm32f0/stm32f0_serial.c @@ -105,7 +105,7 @@ # if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) # ifndef CONFIG_STM32F0_DMA2 -# error STM32F0 UART4/5 receive DMA requires CONFIG_STM32F0_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0_DMA2 # endif # endif @@ -387,18 +387,18 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; #endif #ifdef CONFIG_STM32F0_USART4 -static char g_uart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; -static char g_uart4txbuffer[CONFIG_USART4_TXBUFSIZE]; +static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; +static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; # ifdef CONFIG_USART4_RXDMA -static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; +static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif #ifdef CONFIG_STM32F0_USART5 -static char g_uart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; -static char g_uart5txbuffer[CONFIG_USART5_TXBUFSIZE]; +static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; +static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; # ifdef CONFIG_USART5_RXDMA -static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; +static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif @@ -585,10 +585,10 @@ static struct stm32f0_serial_s g_usart3priv = }; #endif -/* This describes the state of the STM32 UART4 port. */ +/* This describes the state of the STM32 USART4 port. */ #ifdef CONFIG_STM32F0_USART4 -static struct stm32f0_serial_s g_uart4priv = +static struct stm32f0_serial_s g_usart4priv = { .dev = { @@ -598,19 +598,19 @@ static struct stm32f0_serial_s g_uart4priv = .recv = { .size = CONFIG_USART4_RXBUFSIZE, - .buffer = g_uart4rxbuffer, + .buffer = g_usart4rxbuffer, }, .xmit = { .size = CONFIG_USART4_TXBUFSIZE, - .buffer = g_uart4txbuffer, + .buffer = g_usart4txbuffer, }, #ifdef CONFIG_USART4_RXDMA .ops = &g_uart_dma_ops, #else .ops = &g_uart_ops, #endif - .priv = &g_uart4priv, + .priv = &g_usart4priv, }, .irq = STM32F0_IRQ_USART4, @@ -636,7 +636,7 @@ static struct stm32f0_serial_s g_uart4priv = #endif #ifdef CONFIG_USART4_RXDMA .rxdma_channel = DMAMAP_USART4_RX, - .rxfifo = g_uart4rxfifo, + .rxfifo = g_usart4rxfifo, #endif #ifdef CONFIG_USART4_RS485 @@ -650,10 +650,10 @@ static struct stm32f0_serial_s g_uart4priv = }; #endif -/* This describes the state of the STM32 UART5 port. */ +/* This describes the state of the STM32 USART5 port. */ #ifdef CONFIG_STM32F0_USART5 -static struct stm32f0_serial_s g_uart5priv = +static struct stm32f0_serial_s g_usart5priv = { .dev = { @@ -663,19 +663,19 @@ static struct stm32f0_serial_s g_uart5priv = .recv = { .size = CONFIG_USART5_RXBUFSIZE, - .buffer = g_uart5rxbuffer, + .buffer = g_usart5rxbuffer, }, .xmit = { .size = CONFIG_USART5_TXBUFSIZE, - .buffer = g_uart5txbuffer, + .buffer = g_usart5txbuffer, }, #ifdef CONFIG_USART5_RXDMA .ops = &g_uart_dma_ops, #else .ops = &g_uart_ops, #endif - .priv = &g_uart5priv, + .priv = &g_usart5priv, }, .irq = STM32F0_IRQ_USART5, @@ -701,7 +701,7 @@ static struct stm32f0_serial_s g_uart5priv = #endif #ifdef CONFIG_USART5_RXDMA .rxdma_channel = DMAMAP_USART5_RX, - .rxfifo = g_uart5rxfifo, + .rxfifo = g_usart5rxfifo, #endif #ifdef CONFIG_USART5_RS485 @@ -729,10 +729,10 @@ FAR static struct stm32f0_serial_s * const uart_devs[STM32F0_NUSART] = [2] = &g_usart3priv, #endif #ifdef CONFIG_STM32F0_USART4 - [3] = &g_uart4priv, + [3] = &g_usart4priv, #endif #ifdef CONFIG_STM32F0_USART5 - [4] = &g_uart5priv, + [4] = &g_usart5priv, #endif }; @@ -2489,16 +2489,16 @@ void stm32f0serial_dmapoll(void) #endif #ifdef CONFIG_USART4_RXDMA - if (g_uart4priv.rxdma != NULL) + if (g_usart4priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_uart4priv.rxdma, 0, &g_uart4priv); + stm32f0serial_dmarxcallback(g_usart4priv.rxdma, 0, &g_usart4priv); } #endif #ifdef CONFIG_USART5_RXDMA - if (g_uart5priv.rxdma != NULL) + if (g_usart5priv.rxdma != NULL) { - stm32f0serial_dmarxcallback(g_uart5priv.rxdma, 0, &g_uart5priv); + stm32f0serial_dmarxcallback(g_usart5priv.rxdma, 0, &g_usart5priv); } #endif diff --git a/arch/arm/src/stm32f0/stm32f0_uart.h b/arch/arm/src/stm32f0/stm32f0_uart.h index 80229a28312..9785d5e94ac 100644 --- a/arch/arm/src/stm32f0/stm32f0_uart.h +++ b/arch/arm/src/stm32f0/stm32f0_uart.h @@ -54,22 +54,22 @@ * device. */ -#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_UART8) +#if STM32F0_NUSART < 8 || !defined(CONFIG_STM32F0_HAVE_USART8) # undef CONFIG_STM32F0_USART8 #endif -#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_UART7) +#if STM32F0_NUSART < 7 || !defined(CONFIG_STM32F0_HAVE_USART7) # undef CONFIG_STM32F0_USART7 #endif -#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_UART6) +#if STM32F0_NUSART < 6 || !defined(CONFIG_STM32F0_HAVE_USART6) # undef CONFIG_STM32F0_USART6 #endif -#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_UART5) +#if STM32F0_NUSART < 5 || !defined(CONFIG_STM32F0_HAVE_USART5) # undef CONFIG_STM32F0_USART5 #endif -#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_UART4) +#if STM32F0_NUSART < 4 || !defined(CONFIG_STM32F0_HAVE_USART4) # undef CONFIG_STM32F0_USART4 #endif -#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_UART3) +#if STM32F0_NUSART < 3 || !defined(CONFIG_STM32F0_HAVE_USART3) # undef CONFIG_STM32F0_USART3 #endif #if STM32F0_NUSART < 2