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Merge remote-tracking branch 'origin/master' into composite

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This commit is contained in:
Gregory Nutt
2017-06-26 11:56:11 -06:00
parent 4eb548226b 8cb4636bb1
commit aaa81ce497
81 changed files with 4929 additions and 1859 deletions
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9
Kconfig
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@@ -848,15 +848,6 @@ config DEBUG_SYSCALL_INFO
endif # DEBUG_SYSCALL
config DEBUG_WIRELESS
bool "Wireless Device Debug Output"
default n
depends on WIRELESS
---help---
Enable low level debug SYSLOG output from the wireless subsystem and
device drivers. (disabled by default). Support for this debug option
is architecture-specific and may not be available for some MCUs.
comment "OS Function Debug Options"
config DEBUG_DMA

626
arch/arm/src/kinetis/kinetis_i2c.c
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File diff suppressed because it is too large Load Diff

2
arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
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@@ -344,7 +344,7 @@
# define RCC_CFGR3_USART1SW_HSI (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */
#define RCC_CFGR3_I2C1SW (1 << 4) /* Bit 4: I2C1 clock source selection */
#define RCC_CFGR3_TIM1SW (1 << 8) /* Bit 8: TIM1 clock source selection */
#define RCC_CFGR3_HRTIM1SW (1 << 9) /* Bit 9: HRTIM clock source selection */
#define RCC_CFGR3_HRTIM1SW (1 << 12) /* Bit 12: HRTIM clock source selection */
#define RCC_CFGR3_USART2SW_SHIFT (16) /* Bits 16-17: USART2 clock source selection */
#define RCC_CFGR3_USART2SW_MASK (3 << RCC_CFGR3_USART2SW_SHIFT)
# define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */

10
arch/arm/src/stm32/stm32_hrtim.c
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@@ -437,10 +437,8 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
/* HRTIM Register access */
#ifdef HRTIM_HAVE_CLK_FROM_PLL
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits);
#endif
static uint32_t hrtim_cmn_getreg(FAR struct stm32_hrtim_s *priv, int offset);
static void hrtim_cmn_putreg(FAR struct stm32_hrtim_s *priv, int offset,
uint32_t value);
@@ -954,13 +952,11 @@ static int stm32_hrtim_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
#ifdef HRTIM_HAVE_CLK_FROM_PLL
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
uint32_t setbits)
{
putreg32((getreg32(addr) & ~clrbits) | setbits, addr);
}
#endif
/****************************************************************************
* Name: hrtim_cmn_getreg
@@ -2921,12 +2917,6 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
int ret;
uint32_t regval = 0;
/* Configure PLL VCO output as HRTIM clock source */
#ifdef HRTIM_HAVE_CLK_FROM_PLL
stm32_modifyreg32(STM32_RCC_CFGR3, 0, RCC_CFGR3_HRTIM1SW);
#endif
/* HRTIM DLL calibration */
ret = hrtim_dll_cal(priv);

2
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@@ -299,7 +299,7 @@
#define EP0 (0)
/* The set of all enpoints available to the class implementation (1-3) */
/* The set of all endpoints available to the class implementation (1-3) */
#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */

52
arch/arm/src/stm32/stm32_pwr.c
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@@ -64,19 +64,20 @@ static uint16_t g_bkp_writable_counter = 0;
* Private Functions
************************************************************************************/
static inline uint16_t stm32_pwr_getreg(uint8_t offset)
static inline uint32_t stm32_pwr_getreg(uint8_t offset)
{
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
return getreg32(STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
static inline void stm32_pwr_putreg(uint8_t offset, uint32_t value)
{
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
static inline void stm32_pwr_modifyreg(uint8_t offset, uint32_t clearbits,
uint32_t setbits)
{
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits);
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
}
/************************************************************************************
@@ -372,4 +373,43 @@ void stm32_pwr_disablepvd(void)
#endif /* CONFIG_STM32_ENERGYLITE */
/************************************************************************************
* Name: stm32_pwr_enableoverdrive
*
* Description:
* Enable or disable the overdrive mode, allowing clock rates up to 180 MHz.
* If not enabled, the max allowed frequency is 168 MHz.
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
void stm32_pwr_enableoverdrive(bool state)
{
/* Switch overdrive state */
if (state)
{
stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_ODEN);
}
else
{
stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, PWR_CR_ODEN, 0);
}
/* Wait for overdrive ready */
while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_ODRDY) == 0);
/* Set ODSWEN to switch to this new state*/
stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_ODSWEN);
/* Wait for completion */
while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_ODSWRDY) == 0);
}
#endif
#endif /* CONFIG_STM32_PWR */

14
arch/arm/src/stm32/stm32_pwr.h
View File

@@ -215,6 +215,20 @@ void stm32_pwr_disablepvd(void);
#endif /* CONFIG_STM32_ENERGYLITE */
/************************************************************************************
* Name: stm32_pwr_enableoverdrive
*
* Description:
* Enable or disable the overdrive mode, allowing clock rates up to 180 MHz.
* If not enabled, the max allowed frequency is 168 MHz.
*
************************************************************************************/
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
void stm32_pwr_enableoverdrive(bool state);
#endif
#undef EXTERN
#if defined(__cplusplus)
}

149
arch/arm/src/stm32/stm32f33xxx_rcc.c
View File

@@ -342,129 +342,13 @@ static inline void rcc_enableapb2(void)
* Name: stm32_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h. This
* version is for the Connectivity Line parts.
* Called to change to new clock based on settings in board.h.
*
* NOTE: This logic would need to be extended if you need to select low-
* power clocking modes!
****************************************************************************/
#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE)
static void stm32_stdclockconfig(void)
{
uint32_t regval;
/* Enable HSE */
regval = getreg32(STM32_RCC_CR);
regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Set flash wait states
* Sysclk runs with 72MHz -> 2 waitstates.
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
regval = getreg32(STM32_RCC_CFGR2);
regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK |
RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK);
regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL |
RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1);
putreg32(regval, STM32_RCC_CFGR2);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
regval |= STM32_RCC_CFGR_PPRE2;
regval |= RCC_CFGR_HPRE_SYSCLK;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* Enable PLL2 */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLL2ON;
putreg32(regval, STM32_RCC_CR);
/* Wait for PLL2 ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
/* Setup PLL3 for MII/RMII clock on MCO */
#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
regval = getreg32(STM32_RCC_CFGR2);
regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
regval |= STM32_PLL_PLL3MUL;
putreg32(regval, STM32_RCC_CFGR2);
/* Switch PLL3 on */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLL3ON;
putreg32(regval, STM32_RCC_CR);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
#endif
/* Set main PLL source and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Switch main PLL on */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
/* Select PLL as system clock source */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until PLL is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
}
#endif
/****************************************************************************
* Name: stm32_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h. This
* version is for the non-Connectivity Line parts.
*
* NOTE: This logic would need to be extended if you need to select low-
* power clocking modes!
****************************************************************************/
#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \
!defined(CONFIG_STM32_CONNECTIVITYLINE)
#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
static void stm32_stdclockconfig(void)
{
uint32_t regval;
@@ -507,29 +391,6 @@ static void stm32_stdclockconfig(void)
}
}
# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
/* If this is a value-line part and we are using the HSE as the PLL */
# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
# endif
#endif
#ifndef CONFIG_STM32_VALUELINE
/* Value-line devices don't implement flash prefetch/waitstates */
/* Enable FLASH prefetch buffer and 2 wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
/* Set the HCLK source/divider */
@@ -607,6 +468,12 @@ static void stm32_stdclockconfig(void)
stm32_rcc_enablelse();
#endif
#ifdef CONFIG_STM32_HRTIM_CLK_FROM_PLL
regval = getreg32(STM32_RCC_CFGR3);
regval |= RCC_CFGR3_HRTIM1SW;
putreg32(regval, STM32_RCC_CFGR3);
#endif
}
#endif

12
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
View File

@@ -552,12 +552,12 @@
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN11)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN12)
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)

18
arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
View File

@@ -622,15 +622,15 @@
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN11)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN12)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11)
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)

12
arch/arm/src/stm32l4/Kconfig
View File

@@ -3414,6 +3414,18 @@ config UART5_RXDMA
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config STM32L4_SERIAL_RXDMA_BUFFER_SIZE
int "Rx DMA buffer size"
default 32
depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA
---help---
The DMA buffer size when using RX DMA to emulate a FIFO.
When streaming data, the generic serial layer will be called
every time the FIFO receives half this number of bytes.
Value given here will be rounded up to next multiple of 32 bytes.
config SERIAL_DISABLE_REORDERING
bool "Disable reordering of ttySx devices."
depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5

2
arch/arm/src/stm32l4/chip/stm32l4_i2c.h
View File

@@ -259,5 +259,5 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32F30XXX_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_I2C_H */

2
arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
View File

@@ -449,7 +449,7 @@
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2)

40
arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
View File

@@ -160,34 +160,34 @@
/* I2C */
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTA|GPIO_PIN1)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTA|GPIO_PIN14)
#define GPIO_I2C1_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN4)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTA|GPIO_PIN7)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN7)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN14)
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN11)

2
arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
View File

@@ -109,7 +109,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

32
arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h
View File

@@ -257,28 +257,28 @@
* I2C1-3 that are not defined here.
*/
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN15)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN6)

2
arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h
View File

@@ -107,7 +107,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

2
arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
View File

@@ -489,7 +489,7 @@
#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2)
#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1)
#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2)
#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2)
#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2)

52
arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h
View File

@@ -299,41 +299,41 @@
* I2C1-3 that are not defined here.
*/
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2C1_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN13)
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
#define GPIO_I2C1_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN14)
#define GPIO_I2C1_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C1_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN15)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN14)
#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0)
#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1)
#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN2)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN8)
#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTG|GPIO_PIN7)
#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_PORTB|GPIO_PIN2)
#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTG|GPIO_PIN6)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_5 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
#define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN1)
#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN13)
#define GPIO_I2C4_SDA_5 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN15)
#define GPIO_I2C4_SCL_1 (GPIO_ALT|GPIO_AF5 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2C4_SCL_2 (GPIO_ALT|GPIO_AF3 |GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C4_SCL_3 (GPIO_ALT|GPIO_AF2 |GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN0)
#define GPIO_I2C4_SCL_4 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTD|GPIO_PIN12)
#define GPIO_I2C4_SCL_5 (GPIO_ALT|GPIO_AF4 |GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN14)
#define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF5 |GPIO_PORTA|GPIO_PIN14)
#define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_PORTD|GPIO_PIN11)
#define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_PORTF|GPIO_PIN13)

2
arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
View File

@@ -109,7 +109,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

30
arch/arm/src/stm32l4/stm32l4_i2c.c
View File

@@ -1273,7 +1273,7 @@ static inline void stm32l4_i2c_sendstop(FAR struct stm32l4_i2c_priv_s *priv)
* Name: stm32l4_i2c_getstatus
*
* Description:
* Get 32-bit status (SR1 and SR2 combined)
* Get 32-bit status (ISR register)
*
************************************************************************************/
@@ -1556,9 +1556,20 @@ static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv)
/* Enable power and reset the peripheral */
modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0);
#ifdef CONFIG_STM32L4_I2C4
if (priv->config->base == STM32L4_I2C4_BASE)
{
modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0);
}
else
#endif
{
modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0);
}
/* Configure pins */
@@ -1631,7 +1642,16 @@ static int stm32l4_i2c_deinit(FAR struct stm32l4_i2c_priv_s *priv)
/* Disable clocking */
modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0);
#ifdef CONFIG_STM32L4_I2C4
if (priv->config->base == STM32L4_I2C4_BASE)
{
modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0);
}
else
#endif
{
modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0);
}
return OK;
}

11
arch/arm/src/stm32l4/stm32l4_serial.c
View File

@@ -133,9 +133,18 @@
*
* When streaming data, the generic serial layer will be called
* every time the FIFO receives half this number of bytes.
*
* If there ever is a STM32L4 with D-cache, the buffer size
* should be an even multiple of ARMV7M_DCACHE_LINESIZE, so that it
* can be individually invalidated.
*/
# define RXDMA_BUFFER_SIZE 32
# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \
CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0
# define RXDMA_BUFFER_SIZE 32
# else
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31)
# endif
/* DMA priority */

41
configs/c5471evm/nettest/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_RRLOAD_BINARY=y
# CONFIG_MOTOROLA_SREC is not set
# CONFIG_RAW_BINARY is not set
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -123,7 +124,6 @@ CONFIG_ARCH_ARM7TDMI=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="c5471"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
@@ -170,6 +170,8 @@ CONFIG_C5471_AUTONEGOTIATION=y
# CONFIG_C5471_BASET100 is not set
# CONFIG_C5471_BASET10 is not set
CONFIG_C5471_HPWORK=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_TOOLCHAIN_GNU is not set
#
# Architecture Options
@@ -190,6 +192,7 @@ CONFIG_ARCH_HAVE_VFORK=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
CONFIG_ARCH_STACKDUMP=y
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_IDLE_CUSTOM is not set
@@ -353,14 +356,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -466,7 +461,9 @@ CONFIG_OTHER_SERIAL_CONSOLE=y
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -619,6 +616,15 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -627,6 +633,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -773,9 +780,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -787,7 +794,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -898,3 +906,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

98
configs/clicker2-stm32/README.txt
View File

@@ -447,12 +447,100 @@ Configurations
The ifconfig command will show the IP address of the server. Then on
the client node use this IP address to start the client:
nsh> udpserver <server-ip> &
nsh> udpclient <server-ip> &
Where <server-ip> is the IP address of the server that you got above.
NOTE: There is no way to stop the UDP test once it has been started
other than by resetting the board.
Cheat Sheet. Here is a concise summary of all all the steps needed to
run the UDP test (C=Coordinator; E=Endpoint):
C: nsh> i8 /dev/ieee0 startpan
C: nsh> 8 acceptassoc
E: nsh> i8 assoc
C: nsh> ifup wpan0
C: nsh> ifconfig <-- To get the <server-ip>
E: nsh> ifup wpan0
C: nsh> udpserver &
E: nsh> udpclient <server-ip> &
E: nsh> dmesg
6. examples/nettest is enabled. This will allow two MRF24J40 nodes to
exchange TCP packets. Basic instructions:
On the server node:
nsh> ifconfig wpan0
nsh> tcpserver &
The ifconfig command will show the IP address of the server. Then on
the client node use this IP address to start the client:
nsh> tcpclient <server-ip> &
Where <server-ip> is the IP address of the server that you got above.
NOTE: There is no way to stop the UDP test once it has been started
other than by resetting the board.
Cheat Sheet. Here is a concise summary of all all the steps needed to
run the UDP test (C=Coordinator; E=Endpoint):
C: nsh> i8 /dev/ieee0 startpan
C: nsh> 8 acceptassoc
E: nsh> i8 assoc
C: nsh> ifup wpan0
C: nsh> ifconfig <-- To get the <server-ip>
E: nsh> ifup wpan0
C: nsh> tcpserver &
E: nsh> tcpclient <server-ip> &
E: nsh> dmesg
STATUS:
2017-06-19: The Telnet Daemon does not start. This is simply because
the daemon is started too early in the sequence... before the network
has been brought up:
telnetd_daemon: ERROR: socket failure: 106
2017-06-21: Basic UDP functionality has been achieved with HC06
compression and short address. Additional testing is required for
other configurations (see text matrix below).
2017-06-23: Added test for TCP functionality. As of yet unverified.
2017-06-24: There are significant problems with the 6LoWPAN TCP send
logic. A major redesign was done to better handle ACKs and
retransmissions, and to work with TCP dynamic windowing.
2017-05-25: After some rather extensive debug, the TCP test was made
to with (HC06 and short addressing).
2017-06-26: Verified with HC06 and extended addressing and HC1 with
both addressing modes.
Test Matrix:
The following configurations have been tested:
TEST DATE
COMPRESSION ADDRESSING UDP TCP
----------- ---------- ---- ----
hc06 short 6/21 6/25
extended 6/22 6/26
hc1 short 6/23 6/26
extended 6/23 6/26
ipv6 short --- ---
extended --- ---
Other configuration options have not been specifically addressed
(such non-compressable ports, non-MAC based IPv6 addresses, etc.)
One limitation of this test is that it only tests NuttX 6LoWPAN
against NuttX 6LoWPAN. It does not prove that NuttX 6LoWPAN is
compatible with other implementations of 6LoWPAN. The tests could
potentially be verifying only that the design is implemented
incorrectly in compatible way on both the client and server sides.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. This
@@ -509,10 +597,10 @@ Configurations
emptied and dumped to the system logging device (USART3 in this
configuration):
CONFIG_USBDEV_TRACE=y : Enable USB trace feature
CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
CONFIG_USBDEV_TRACE=y : Enable USB trace feature
CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
CONFIG_USBMONITOR=y : Enable the USB monitor daemon
CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority

51
configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
View File

@@ -717,7 +717,11 @@ CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SCHED_HPWORKPERIOD=50000
CONFIG_SCHED_HPWORKSTACKSIZE=2048
# CONFIG_SCHED_LPWORK is not set
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_LPNTHREADS=1
CONFIG_SCHED_LPWORKPRIORITY=160
CONFIG_SCHED_LPWORKPERIOD=50000
CONFIG_SCHED_LPWORKSTACKSIZE=2048
#
# Stack and heap information
@@ -1076,6 +1080,7 @@ CONFIG_NET_HOSTNAME="MRF24J40"
# CONFIG_PSEUDOFS_SOFTLINKS is not set
CONFIG_FS_READABLE=y
CONFIG_FS_WRITABLE=y
# CONFIG_FS_AIO is not set
# CONFIG_FS_NAMED_SEMAPHORES is not set
CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
# CONFIG_FS_RAMMAP is not set
@@ -1138,14 +1143,17 @@ CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y
CONFIG_IEEE802154_DEFAULT_EADDR=0x00fade00deadbeef
CONFIG_MAC802154_HPWORK=y
CONFIG_IEEE802154_NTXDESC=3
CONFIG_IEEE802154_IND_PREALLOC=20
# CONFIG_MAC802154_LPWORK is not set
CONFIG_MAC802154_NTXDESC=32
CONFIG_MAC802154_NNOTIF=48
CONFIG_IEEE802154_IND_PREALLOC=32
CONFIG_IEEE802154_IND_IRQRESERVE=10
CONFIG_IEEE802154_MACDEV=y
CONFIG_IEEE802154_MACDEV_RECVRPRIO=0
CONFIG_IEEE802154_NETDEV=y
CONFIG_IEEE802154_NETDEV_RECVRPRIO=1
CONFIG_IEEE802154_NETDEV_HPWORK=y
# CONFIG_IEEE802154_NETDEV_HPWORK is not set
CONFIG_IEEE802154_NETDEV_LPWORK=y
# CONFIG_IEEE802154_LOOPBACK is not set
#
@@ -1321,7 +1329,36 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
# CONFIG_EXAMPLES_MM is not set
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
# CONFIG_EXAMPLES_NETTEST is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
# CONFIG_EXAMPLES_NETTEST_SERVER1 is not set
CONFIG_EXAMPLES_NETTEST_TARGET2=y
CONFIG_EXAMPLES_NETTEST_PRIORITY2=100
CONFIG_EXAMPLES_NETTEST_STACKSIZE2=2048
CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_DEAMON_PRIORITY=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv6=y
# CONFIG_EXAMPLES_NETTEST_INIT is not set
#
# Target IPv6 address
#
#
# Server IPv6 address
#
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_2=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_3=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_4=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_5=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
@@ -1364,7 +1401,7 @@ CONFIG_EXAMPLES_UDP_DEVNAME="wpan0"
CONFIG_EXAMPLES_UDP_IPv6=y
#
# Server IPv6 address
# Default Server IPv6 address
#
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_2=0x0000
@@ -1374,6 +1411,8 @@ CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_5=0x0000
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617
# CONFIG_EXAMPLES_UDPBLASTER is not set
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_WATCHDOG is not set

6
configs/clicker2-stm32/mrf24j40-mac/defconfig
View File

@@ -984,7 +984,9 @@ CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y
CONFIG_IEEE802154_DEFAULT_EADDR=0x00fade00deadbeef
CONFIG_MAC802154_HPWORK=y
CONFIG_IEEE802154_NTXDESC=3
CONFIG_MAC802154_NTXDESC=3
CONFIG_MAC802154_NNOTIF=6
CONFIG_MAC802154_NPANDESC=5
CONFIG_IEEE802154_IND_PREALLOC=20
CONFIG_IEEE802154_IND_IRQRESERVE=10
CONFIG_IEEE802154_MACDEV=y
@@ -1166,10 +1168,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXFFS is not set
# CONFIG_EXAMPLES_NXHELLO is not set
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NX is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTERM is not set
# CONFIG_EXAMPLES_NXTEXT is not set

42
configs/eagle100/nettest/defconfig
View File

@@ -34,6 +34,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -129,8 +130,6 @@ CONFIG_ARCH_CORTEXM3=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="tiva"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -271,6 +270,8 @@ CONFIG_TIVA_BOARDMAC=y
#
CONFIG_SSI_POLLWAIT=y
CONFIG_SSI_TXLIMIT=4
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
@@ -291,6 +292,7 @@ CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
CONFIG_ARCH_HAVE_RESET=y
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
@@ -458,14 +460,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -600,7 +594,9 @@ CONFIG_UART0_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -753,6 +749,15 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -761,6 +766,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -906,9 +912,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -920,7 +926,8 @@ CONFIG_EXAMPLES_NETTEST_INIT=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1031,3 +1038,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

40
configs/ez80f910200zco/nettest/defconfig
View File

@@ -34,6 +34,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
# CONFIG_RAW_BINARY is not set
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -152,6 +153,8 @@ CONFIG_EZ80_TXPOLLTIMERMS=10
# CONFIG_ARCH_MCFILTER is not set
CONFIG_EZ80_EMAC_HPWORK=y
CONFIG_ARCH_TIMERHOOK=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_TOOLCHAIN_GNU is not set
#
# Architecture Options
@@ -172,6 +175,7 @@ CONFIG_ARCH_TIMERHOOK=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_STACKDUMP is not set
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_IDLE_CUSTOM is not set
@@ -337,14 +341,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -498,7 +494,9 @@ CONFIG_UART0_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -653,6 +651,15 @@ CONFIG_HEAP2_BASE=0x00000000
CONFIG_HEAP2_SIZE=0
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -661,6 +668,7 @@ CONFIG_HEAP2_SIZE=0
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -801,9 +809,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -815,7 +823,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -926,3 +935,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

48
configs/misoc/hello/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -111,6 +112,8 @@ CONFIG_MISOC_UART_RX_BUF_SIZE=64
CONFIG_MISOC_UART_TX_BUF_SIZE=64
# CONFIG_LM32_TOOLCHAIN_BUILDROOT is not set
CONFIG_LM32_TOOLCHAIN_GNUL=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
@@ -131,6 +134,7 @@ CONFIG_LM32_TOOLCHAIN_GNUL=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
CONFIG_ARCH_STACKDUMP=y
CONFIG_ENDIAN_BIG=y
# CONFIG_ARCH_IDLE_CUSTOM is not set
@@ -318,16 +322,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=8
# CONFIG_IOB_DEBUG is not set
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -486,7 +480,9 @@ CONFIG_UART1_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -643,6 +639,16 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=8
# CONFIG_IOB_DEBUG is not set
#
# Audio Support
#
@@ -651,6 +657,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -774,7 +781,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
#
# CONFIG_C99_BOOL8 is not set
CONFIG_HAVE_CXX=y
# CONFIG_HAVE_CXXINITIALIZE is not set
# CONFIG_CXX_NEWLONG is not set
#
@@ -825,9 +831,9 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -839,7 +845,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80132
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80101
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8023b
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1053,6 +1060,7 @@ CONFIG_NSH_CONSOLE=y
# Networking Configuration
#
CONFIG_NSH_NETINIT=y
# CONFIG_NSH_NETLOCAL is not set
CONFIG_NSH_NETINIT_THREAD=y
CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568
CONFIG_NSH_NETINIT_THREAD_PRIORITY=80
@@ -1090,6 +1098,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
# Platform-specific Support
#
# CONFIG_PLATFORM_CONFIGDATA is not set
# CONFIG_HAVE_CXXINITIALIZE is not set
#
# System Libraries and NSH Add-Ons
@@ -1097,11 +1106,13 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
CONFIG_SYSTEM_CLE=y
CONFIG_SYSTEM_CLE_DEBUGLEVEL=0
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_DHCPC_RENEW is not set
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_NETDB is not set
# CONFIG_SYSTEM_NTPC is not set
# CONFIG_SYSTEM_RAMTEST is not set
CONFIG_READLINE_HAVE_EXTMATCH=y
CONFIG_SYSTEM_READLINE=y
@@ -1118,3 +1129,10 @@ CONFIG_READLINE_ECHO=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

41
configs/ntosd-dm320/nettest/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -123,7 +124,6 @@ CONFIG_ARCH_ARM926EJS=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="dm320"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
@@ -149,6 +149,8 @@ CONFIG_ARM_TOOLCHAIN_CODESOURCERYL=y
#
CONFIG_DM320_UART0=y
CONFIG_DM320_UART1=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_TOOLCHAIN_GNU is not set
#
# Architecture Options
@@ -169,6 +171,7 @@ CONFIG_ARCH_HAVE_MMU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
CONFIG_ARCH_USE_MMU=y
# CONFIG_PAGING is not set
# CONFIG_ARCH_STACKDUMP is not set
@@ -335,14 +338,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -505,7 +500,9 @@ CONFIG_UART1_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -659,6 +656,15 @@ CONFIG_MM_REGIONS=1
# CONFIG_GRAN is not set
# CONFIG_MM_PGALLOC is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -667,6 +673,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -813,9 +820,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -827,7 +834,8 @@ CONFIG_EXAMPLES_NETTEST_INIT=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -938,3 +946,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

2
configs/ntosd-dm320/udp/defconfig
View File

@@ -928,7 +928,7 @@ CONFIG_NETUTILS_NETLIB=y
#
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_DHCPC is not set
# CONFIG_SYSTEM_DHCPC_RENEW is not set
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set

42
configs/olimex-lpc1766stk/nettest/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_INTELHEX_BINARY=y
# CONFIG_MOTOROLA_SREC is not set
# CONFIG_RAW_BINARY is not set
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -123,8 +124,6 @@ CONFIG_ARCH_CORTEXM3=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="lpc17xx"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -237,6 +236,8 @@ CONFIG_NET_NRXDESC=6
# CONFIG_NET_HASH is not set
# CONFIG_LPC17_MULTICAST is not set
CONFIG_LPC17_ETHERNET_HPWORK=y
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
# Architecture Options
@@ -257,6 +258,7 @@ CONFIG_ARCH_HAVE_MPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
CONFIG_ARCH_HAVE_RESET=y
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_USE_MPU is not set
# CONFIG_ARCH_IRQPRIO is not set
CONFIG_ARCH_STACKDUMP=y
@@ -427,14 +429,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -588,7 +582,9 @@ CONFIG_UART0_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -741,6 +737,15 @@ CONFIG_MM_REGIONS=2
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -749,6 +754,7 @@ CONFIG_MM_REGIONS=2
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -895,9 +901,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -909,7 +915,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1020,3 +1027,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

41
configs/olimex-strp711/nettest/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
CONFIG_RAW_BINARY=y
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -123,7 +124,6 @@ CONFIG_ARCH_ARM7TDMI=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="arm"
CONFIG_ARCH_CHIP="str71x"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_HAVE_FPU is not set
# CONFIG_ARCH_HAVE_DPFPU is not set
# CONFIG_ARCH_HAVE_TRUSTZONE is not set
@@ -178,6 +178,8 @@ CONFIG_STR71X_XTI=y
# CONFIG_STR71X_BANK2 is not set
# CONFIG_STR71X_BANK3 is not set
# CONFIG_STR71X_HAVE_EXTMEM is not set
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_TOOLCHAIN_GNU is not set
#
# Architecture Options
@@ -198,6 +200,7 @@ CONFIG_ARCH_HAVE_VFORK=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
# CONFIG_ARCH_HAVE_POWEROFF is not set
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
CONFIG_ARCH_STACKDUMP=y
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_IDLE_CUSTOM is not set
@@ -381,14 +384,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -551,7 +546,9 @@ CONFIG_UART1_2STOP=0
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -705,6 +702,15 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -713,6 +719,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -860,9 +867,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -874,7 +881,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -985,3 +993,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

2
configs/pic32mx7mmb/nsh/defconfig
View File

@@ -1338,7 +1338,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512
#
# CONFIG_SYSTEM_CLE is not set
# CONFIG_SYSTEM_CUTERM is not set
# CONFIG_SYSTEM_DHCPC is not set
# CONFIG_SYSTEM_DHCPC_RENEW is not set
# CONFIG_SYSTEM_FLASH_ERASEALL is not set
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_HEX2BIN is not set

2
configs/sim/README.txt
View File

@@ -810,7 +810,7 @@ sixlowpan
This configuration includes apps/examples/nettest and apps/examples/udpblaster.
Neither are truly functional. The only intent of this configuration
is to verify that the 6LoWPAN stack correctly encodes IEEE802.15.4
packets on output to the loopback device and correct decodes the
packets on output to the loopback device and correctly decodes the
returned packet.
touchscreen

40
configs/sim/nettest/defconfig
View File

@@ -28,6 +28,7 @@ CONFIG_BUILD_FLAT=y
# CONFIG_MOTOROLA_SREC is not set
# CONFIG_RAW_BINARY is not set
# CONFIG_UBOOT_UIMAGE is not set
# CONFIG_DFU_BINARY is not set
#
# Customize Header Files
@@ -83,6 +84,8 @@ CONFIG_SIM_NET_HOST_ROUTE=y
# CONFIG_SIM_FRAMEBUFFER is not set
# CONFIG_SIM_SPIFLASH is not set
# CONFIG_SIM_QSPIFLASH is not set
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARCH_TOOLCHAIN_GNU is not set
#
# Architecture Options
@@ -103,6 +106,7 @@ CONFIG_ARCH_HAVE_MULTICPU=y
# CONFIG_ARCH_HAVE_EXTCLK is not set
CONFIG_ARCH_HAVE_POWEROFF=y
# CONFIG_ARCH_HAVE_RESET is not set
# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
# CONFIG_ARCH_STACKDUMP is not set
# CONFIG_ENDIAN_BIG is not set
# CONFIG_ARCH_IDLE_CUSTOM is not set
@@ -279,14 +283,6 @@ CONFIG_DEV_NULL=y
#
# Buffering
#
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
# CONFIG_DRVR_WRITEBUFFER is not set
# CONFIG_DRVR_READAHEAD is not set
# CONFIG_RAMDISK is not set
@@ -388,7 +384,9 @@ CONFIG_SERIAL_CONSOLE=y
# System Logging
#
# CONFIG_ARCH_SYSLOG is not set
CONFIG_SYSLOG_WRITE=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_BUFFER is not set
# CONFIG_SYSLOG_INTBUFFER is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
CONFIG_SYSLOG_SERIAL_CONSOLE=y
@@ -555,6 +553,15 @@ CONFIG_MM_REGIONS=1
# CONFIG_ARCH_HAVE_HEAP2 is not set
# CONFIG_GRAN is not set
#
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
#
@@ -563,6 +570,7 @@ CONFIG_MM_REGIONS=1
#
# Wireless Support
#
# CONFIG_WIRELESS is not set
#
# Binary Loader
@@ -716,9 +724,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -730,7 +738,8 @@ CONFIG_EXAMPLES_NETTEST_INIT=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -843,3 +852,10 @@ CONFIG_NETUTILS_NETLIB=y
#
# Wireless Libraries and NSH Add-Ons
#
#
# IEEE 802.15.4 applications
#
# CONFIG_IEEE802154_LIBMAC is not set
# CONFIG_IEEE802154_LIBUTILS is not set
# CONFIG_IEEE802154_I8SAK is not set

43
configs/sim/sixlowpan/defconfig
View File

@@ -694,8 +694,8 @@ CONFIG_MM_REGIONS=1
# Common I/O Buffer Support
#
CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=36
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NBUFFERS=48
CONFIG_IOB_BUFSIZE=128
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=8
@@ -711,7 +711,8 @@ CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y
CONFIG_IEEE802154_DEFAULT_EADDR=0x00fade00deadbeef
CONFIG_MAC802154_HPWORK=y
CONFIG_IEEE802154_NTXDESC=3
CONFIG_MAC802154_NTXDESC=3
CONFIG_MAC802154_NNOTIF=3
CONFIG_IEEE802154_IND_PREALLOC=20
CONFIG_IEEE802154_IND_IRQRESERVE=10
# CONFIG_IEEE802154_MACDEV is not set
@@ -893,11 +894,12 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=2048
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=4096
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=4096
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_LOOPBACK=y
CONFIG_EXAMPLES_NETTEST_SERVER_STACKSIZE=4096
CONFIG_EXAMPLES_NETTEST_SERVER_PRIORITY=100
CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=4096
CONFIG_EXAMPLES_NETTEST_DAEMON_PRIORITY=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv6=y
@@ -906,16 +908,17 @@ CONFIG_EXAMPLES_NETTEST_IPv6=y
#
#
# Client IPv6 address
# Server IPv6 address
#
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_2=0x0000
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_3=0x0000
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_4=0x0000
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_5=0x0000
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_CLIENTIPv6ADDR_8=0x1034
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_2=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_3=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_4=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_5=0x0000
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0xcda9
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
# CONFIG_EXAMPLES_NRF24L01TERM is not set
CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NULL is not set
@@ -1165,13 +1168,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
# CONFIG_SYSTEM_FREE is not set
# CONFIG_SYSTEM_HEX2BIN is not set
# CONFIG_SYSTEM_HEXED is not set
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_I2CTOOL_MINBUS=0
CONFIG_I2CTOOL_MAXBUS=0
CONFIG_I2CTOOL_MINADDR=0x03
CONFIG_I2CTOOL_MAXADDR=0x77
CONFIG_I2CTOOL_MAXREGADDR=0xff
CONFIG_I2CTOOL_DEFFREQ=400000
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_MDIO is not set
# CONFIG_SYSTEM_NETDB is not set

15
configs/stm3220g-eval/nettest/defconfig
View File

@@ -131,7 +131,6 @@ CONFIG_ARCH_CORTEXM3=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -403,6 +402,7 @@ CONFIG_STM32_HAVE_I2C2=y
CONFIG_STM32_HAVE_I2C3=y
CONFIG_STM32_HAVE_SPI2=y
CONFIG_STM32_HAVE_SPI3=y
# CONFIG_STM32_HAVE_I2S3 is not set
# CONFIG_STM32_HAVE_SPI4 is not set
# CONFIG_STM32_HAVE_SPI5 is not set
# CONFIG_STM32_HAVE_SPI6 is not set
@@ -552,6 +552,7 @@ CONFIG_STM32_ETHMAC_HPWORK=y
#
# USB Device Configuration
#
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
@@ -1061,6 +1062,7 @@ CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
@@ -1187,7 +1189,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
#
# CONFIG_C99_BOOL8 is not set
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_CXX_NEWLONG is not set
#
@@ -1231,9 +1232,9 @@ CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -1245,7 +1246,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1334,6 +1336,7 @@ CONFIG_NETUTILS_NETLIB=y
# Platform-specific Support
#
# CONFIG_PLATFORM_CONFIGDATA is not set
CONFIG_HAVE_CXXINITIALIZE=y
#
# System Libraries and NSH Add-Ons

16
configs/stm3240g-eval/nettest/defconfig
View File

@@ -131,7 +131,6 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -404,6 +403,7 @@ CONFIG_STM32_HAVE_I2C2=y
CONFIG_STM32_HAVE_I2C3=y
CONFIG_STM32_HAVE_SPI2=y
CONFIG_STM32_HAVE_SPI3=y
CONFIG_STM32_HAVE_I2S3=y
# CONFIG_STM32_HAVE_SPI4 is not set
# CONFIG_STM32_HAVE_SPI5 is not set
# CONFIG_STM32_HAVE_SPI6 is not set
@@ -442,6 +442,7 @@ CONFIG_STM32_ETHMAC=y
# CONFIG_STM32_SPI1 is not set
# CONFIG_STM32_SPI2 is not set
# CONFIG_STM32_SPI3 is not set
# CONFIG_STM32_I2S3 is not set
CONFIG_STM32_SYSCFG=y
# CONFIG_STM32_TIM1 is not set
# CONFIG_STM32_TIM2 is not set
@@ -556,6 +557,7 @@ CONFIG_STM32_ETHMAC_HPWORK=y
#
# USB Device Configuration
#
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
@@ -1065,6 +1067,7 @@ CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
@@ -1191,7 +1194,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
#
# CONFIG_C99_BOOL8 is not set
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_CXX_NEWLONG is not set
#
@@ -1235,9 +1237,9 @@ CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -1249,7 +1251,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1338,6 +1341,7 @@ CONFIG_NETUTILS_NETLIB=y
# Platform-specific Support
#
# CONFIG_PLATFORM_CONFIGDATA is not set
CONFIG_HAVE_CXXINITIALIZE=y
#
# System Libraries and NSH Add-Ons

18
configs/stm3240g-eval/webserver/defconfig
View File

@@ -125,7 +125,6 @@ CONFIG_ARCH_CORTEXM4=y
# CONFIG_ARCH_CORTEXR7F is not set
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARCH_CHIP="stm32"
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
# CONFIG_ARMV7M_USEBASEPRI is not set
CONFIG_ARCH_HAVE_CMNVECTOR=y
# CONFIG_ARMV7M_CMNVECTOR is not set
@@ -394,6 +393,7 @@ CONFIG_STM32_HAVE_I2C2=y
CONFIG_STM32_HAVE_I2C3=y
CONFIG_STM32_HAVE_SPI2=y
CONFIG_STM32_HAVE_SPI3=y
CONFIG_STM32_HAVE_I2S3=y
# CONFIG_STM32_HAVE_SPI4 is not set
# CONFIG_STM32_HAVE_SPI5 is not set
# CONFIG_STM32_HAVE_SPI6 is not set
@@ -432,6 +432,7 @@ CONFIG_STM32_PWR=y
# CONFIG_STM32_SPI1 is not set
# CONFIG_STM32_SPI2 is not set
# CONFIG_STM32_SPI3 is not set
# CONFIG_STM32_I2S3 is not set
CONFIG_STM32_SYSCFG=y
# CONFIG_STM32_TIM1 is not set
# CONFIG_STM32_TIM2 is not set
@@ -563,6 +564,7 @@ CONFIG_STM32_ETHMAC_HPWORK=y
#
# USB Device Configuration
#
# CONFIG_ARCH_TOOLCHAIN_IAR is not set
CONFIG_ARCH_TOOLCHAIN_GNU=y
#
@@ -1154,6 +1156,7 @@ CONFIG_MM_IOB=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_BUFSIZE=196
CONFIG_IOB_NCHAINS=8
CONFIG_IOB_THROTTLE=0
#
# Audio Support
@@ -1289,7 +1292,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512
#
# CONFIG_C99_BOOL8 is not set
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_CXX_NEWLONG is not set
#
@@ -1335,9 +1337,9 @@ CONFIG_HAVE_CXXINITIALIZE=y
# CONFIG_EXAMPLES_MODBUS is not set
# CONFIG_EXAMPLES_MOUNT is not set
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_STACKSIZE=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY=100
# CONFIG_EXAMPLES_NETTEST_SERVER is not set
CONFIG_EXAMPLES_NETTEST_STACKSIZE1=2048
CONFIG_EXAMPLES_NETTEST_PRIORITY1=100
CONFIG_EXAMPLES_NETTEST_DEVNAME="eth0"
# CONFIG_EXAMPLES_NETTEST_PERFORMANCE is not set
CONFIG_EXAMPLES_NETTEST_IPv4=y
CONFIG_EXAMPLES_NETTEST_INIT=y
@@ -1349,7 +1351,8 @@ CONFIG_EXAMPLES_NETTEST_NOMAC=y
CONFIG_EXAMPLES_NETTEST_IPADDR=0x0a000002
CONFIG_EXAMPLES_NETTEST_DRIPADDR=0x0a000001
CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVERIP=0x0a000001
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=5471
# CONFIG_EXAMPLES_NSH is not set
# CONFIG_EXAMPLES_NULL is not set
# CONFIG_EXAMPLES_NX is not set
@@ -1551,6 +1554,7 @@ CONFIG_NSH_CONSOLE=y
# Networking Configuration
#
CONFIG_NSH_NETINIT=y
# CONFIG_NSH_NETLOCAL is not set
# CONFIG_NSH_NETINIT_THREAD is not set
#
@@ -1590,6 +1594,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# Platform-specific Support
#
# CONFIG_PLATFORM_CONFIGDATA is not set
CONFIG_HAVE_CXXINITIALIZE=y
#
# System Libraries and NSH Add-Ons
@@ -1602,6 +1607,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512
# CONFIG_SYSTEM_I2CTOOL is not set
# CONFIG_SYSTEM_INSTALL is not set
# CONFIG_SYSTEM_NETDB is not set
# CONFIG_SYSTEM_NTPC is not set
# CONFIG_SYSTEM_RAMTEST is not set
CONFIG_READLINE_HAVE_EXTMATCH=y
CONFIG_SYSTEM_READLINE=y

6
drivers/net/tun.c
View File

@@ -667,8 +667,9 @@ static int tun_ifup(struct net_driver_s *dev)
static int tun_ifdown(struct net_driver_s *dev)
{
FAR struct tun_device_s *priv = (FAR struct tun_device_s *)dev->d_private;
irqstate_t flags;
tun_lock(priv);
flags = enter_critical_section();
/* Cancel the TX poll timer */
@@ -677,7 +678,8 @@ static int tun_ifdown(struct net_driver_s *dev)
/* Mark the device "down" */
priv->bifup = false;
tun_unlock(priv);
leave_critical_section(flags);
return OK;
}

10
drivers/wireless/ieee802154/at86rf23x.c
View File

@@ -1533,22 +1533,22 @@ FAR struct ieee802154_radio_s *at86rf23x_init(FAR struct spi_dev_s *spi,
/* Configure the Pan id */
//at86rf23x_setpanid (&dev->ieee, IEEE802154_PAN_DEFAULT);
//at86rf23x_setpanid(&dev->ieee, IEEE802154_PAN_DEFAULT);
/* Configure the Short Addr */
//at86rf23x_setsaddr (&dev->ieee, IEEE802154_SADDR_UNSPEC);
//at86rf23x_setsaddr(&dev->ieee, IEEE802154_SADDR_UNSPEC);
/* Configure the IEEE Addr */
//at86rf23x_seteaddr (&dev->ieee, IEEE802154_EADDR_UNSPEC);
//at86rf23x_seteaddr(&dev->ieee, IEEE802154_EADDR_UNSPEC);
/* Default device params at86rf23x defaults to energy detect only */
cca.use_ed = 1;
cca.use_cs = 0;
cca.edth = 0x60; /* CCA mode ED, no carrier sense, recommenced ED
* threshold -69 dBm */
cca.edth = 0x60; /* CCA mode ED, no carrier sense, recommenced ED
* threshold -69 dBm */
at86rf23x_setcca(&dev->ieee, &cca);
/* Put the Device to RX ON Mode */

412
drivers/wireless/ieee802154/mrf24j40.c
View File

File diff suppressed because it is too large Load Diff

125
drivers/wireless/ieee802154/mrf24j40.h
View File

@@ -118,41 +118,41 @@
#define MRF24J40_SLPCAL1 (MRF24J40_LONGREG_BASE + 0x0A)
#define MRF24J40_SLPCAL2 (MRF24J40_LONGREG_BASE + 0x0B)
#define MRF24J40_RFSTATE (MRF24J40_LONGREG_BASE + 0x0F)
#define MRF24J40_RSSI 0x80000210
#define MRF24J40_SLPCON0 0x80000211
#define MRF24J40_SLPCON1 0x80000220
#define MRF24J40_WAKETIMEL 0x80000222
#define MRF24J40_WAKETIMEH 0x80000223
#define MRF24J40_REMCNTL 0x80000224
#define MRF24J40_REMCNTH 0x80000225
#define MRF24J40_MAINCNT0 0x80000226
#define MRF24J40_MAINCNT1 0x80000227
#define MRF24J40_MAINCNT2 0x80000228
#define MRF24J40_MAINCNT3 0x80000229
#define MRF24J40_TESTMODE 0x8000022F
#define MRF24J40_ASSOEADR0 0x80000230
#define MRF24J40_ASSOEADR1 0x80000231
#define MRF24J40_ASSOEADR2 0x80000232
#define MRF24J40_ASSOEADR3 0x80000233
#define MRF24J40_ASSOEADR4 0x80000234
#define MRF24J40_ASSOEADR5 0x80000235
#define MRF24J40_ASSOEADR6 0x80000236
#define MRF24J40_ASSOEADR7 0x80000237
#define MRF24J40_ASSOSADR0 0x80000238
#define MRF24J40_ASSOSADR1 0x80000239
#define MRF24J40_UPNONCE0 0x80000240
#define MRF24J40_UPNONCE1 0x80000241
#define MRF24J40_UPNONCE2 0x80000242
#define MRF24J40_UPNONCE3 0x80000243
#define MRF24J40_UPNONCE4 0x80000244
#define MRF24J40_UPNONCE5 0x80000245
#define MRF24J40_UPNONCE6 0x80000246
#define MRF24J40_UPNONCE7 0x80000247
#define MRF24J40_UPNONCE8 0x80000248
#define MRF24J40_UPNONCE9 0x80000249
#define MRF24J40_UPNONCE10 0x8000024A
#define MRF24J40_UPNONCE11 0x8000024B
#define MRF24J40_UPNONCE12 0x8000024C
#define MRF24J40_RSSI (MRF24J40_LONGREG_BASE + 0x10)
#define MRF24J40_SLPCON0 (MRF24J40_LONGREG_BASE + 0x11)
#define MRF24J40_SLPCON1 (MRF24J40_LONGREG_BASE + 0x20)
#define MRF24J40_WAKETIMEL (MRF24J40_LONGREG_BASE + 0x22)
#define MRF24J40_WAKETIMEH (MRF24J40_LONGREG_BASE + 0x23)
#define MRF24J40_REMCNTL (MRF24J40_LONGREG_BASE + 0x24)
#define MRF24J40_REMCNTH (MRF24J40_LONGREG_BASE + 0x25)
#define MRF24J40_MAINCNT0 (MRF24J40_LONGREG_BASE + 0x26)
#define MRF24J40_MAINCNT1 (MRF24J40_LONGREG_BASE + 0x27)
#define MRF24J40_MAINCNT2 (MRF24J40_LONGREG_BASE + 0x28)
#define MRF24J40_MAINCNT3 (MRF24J40_LONGREG_BASE + 0x29)
#define MRF24J40_TESTMODE (MRF24J40_LONGREG_BASE + 0x2F)
#define MRF24J40_ASSOEADR0 (MRF24J40_LONGREG_BASE + 0x30)
#define MRF24J40_ASSOEADR1 (MRF24J40_LONGREG_BASE + 0x31)
#define MRF24J40_ASSOEADR2 (MRF24J40_LONGREG_BASE + 0x32)
#define MRF24J40_ASSOEADR3 (MRF24J40_LONGREG_BASE + 0x33)
#define MRF24J40_ASSOEADR4 (MRF24J40_LONGREG_BASE + 0x34)
#define MRF24J40_ASSOEADR5 (MRF24J40_LONGREG_BASE + 0x35)
#define MRF24J40_ASSOEADR6 (MRF24J40_LONGREG_BASE + 0x36)
#define MRF24J40_ASSOEADR7 (MRF24J40_LONGREG_BASE + 0x37)
#define MRF24J40_ASSOSADR0 (MRF24J40_LONGREG_BASE + 0x38)
#define MRF24J40_ASSOSADR1 (MRF24J40_LONGREG_BASE + 0x39)
#define MRF24J40_UPNONCE0 (MRF24J40_LONGREG_BASE + 0x40)
#define MRF24J40_UPNONCE1 (MRF24J40_LONGREG_BASE + 0x41)
#define MRF24J40_UPNONCE2 (MRF24J40_LONGREG_BASE + 0x42)
#define MRF24J40_UPNONCE3 (MRF24J40_LONGREG_BASE + 0x43)
#define MRF24J40_UPNONCE4 (MRF24J40_LONGREG_BASE + 0x44)
#define MRF24J40_UPNONCE5 (MRF24J40_LONGREG_BASE + 0x45)
#define MRF24J40_UPNONCE6 (MRF24J40_LONGREG_BASE + 0x46)
#define MRF24J40_UPNONCE7 (MRF24J40_LONGREG_BASE + 0x47)
#define MRF24J40_UPNONCE8 (MRF24J40_LONGREG_BASE + 0x48)
#define MRF24J40_UPNONCE9 (MRF24J40_LONGREG_BASE + 0x49)
#define MRF24J40_UPNONCE10 (MRF24J40_LONGREG_BASE + 0x4A)
#define MRF24J40_UPNONCE11 (MRF24J40_LONGREG_BASE + 0x4B)
#define MRF24J40_UPNONCE12 (MRF24J40_LONGREG_BASE + 0x4C)
/* INTSTAT bits */
@@ -226,4 +226,59 @@
#define MRF24J40_TXSTAT_X_SHIFT 6
#define MRF24J40_TXSTAT_X_MASK (3 << MRF24J40_TXSTAT_X_SHIFT)
/* TXBCON1 bits */
#define MRF24J40_TXBCON1_RSSINUM 0x30
#define MRF24J40_TXBCON1_NWU_BCN 0x40
#define MRF24J40_TXBCON1_TXBMSK 0x80
/* WAKECON bits */
#define MRF24J40_WAKECON_INTL 0x3F
#define MRF24J40_WAKECON_REGWAKE 0x40
#define MRF24J40_WAKECON_IMMWAKE 0x80
/* WAKECON bits */
#define MRF24J40_WAKECON_INTL 0x3F
#define MRF24J40_WAKECON_REGWAKE 0x40
#define MRF24J40_WAKECON_IMMWAKE 0x80
/* ESLOTG1 bits */
#define MRF24J40_ESLOTG1_CAP 0x0F
#define MRF24J40_ESLOTG1_GTS1 0xF0
/* SLPCAL2 bits */
#define MRF24J40_SLPCAL2_SLPCAL 0x0F
#define MRF24J40_SLPCAL2_SLPCALEN 0x10
#define MRF24J40_SLPCAL2_SLPCALRDY 0x80
/* RFCON7 bits */
#define MRF24J40_RFCON7_SEL_32KHZ 0x40
#define MRF24J40_RFCON7_SEL_100KHZ 0x80
/* SLPACK bits */
#define MRF24J40_SLPACK_WAKECNT0_6 0x7F
#define MRF24J40_SLPACK_SLPACK 0x80
/* RXFLUSH bits */
#define MRF24J40_RXFLUSH_RXFLUSH 0x01
#define MRF24J40_RXFLUSH_BCNONLY 0x02
#define MRF24J40_RXFLUSH_DATAONLY 0x04
#define MRF24J40_RXFLUSH_CMDONLY 0x08
#define MRF24J40_RXFLUSH_WAKEPAD 0x20
#define MRF24J40_RXFLUSH_WAKEPOL 0x40
#define MRF24J40_RXFLUSH_SHIFT_RXFLUSH 0
#define MRF24J40_RXFLUSH_SHIFT_BCNONLY 1
#define MRF24J40_RXFLUSH_SHIFT_DATAONLY 2
#define MRF24J40_RXFLUSH_SHIFT_CMDONLY 3
#define MRF24J40_RXFLUSH_SHIFT_WAKEPAD 5
#define MRF24J40_RXFLUSH_SHIFT_WAKEPOL 6
#endif /* __DRIVERS_WIRELESS_IEEE802154_MRF24J40_H */

4
include/nuttx/net/ieee802154.h
View File

@@ -78,6 +78,10 @@
#define SIXLOWPAN_MAC_STDFRAME 127
/* Space for a two byte FCS must be reserved at the end of the frame */
#define SIXLOWPAN_MAC_FCSSIZE 2
/****************************************************************************
* Public Types
****************************************************************************/

2
include/nuttx/net/ip.h
View File

@@ -553,7 +553,7 @@ bool net_ipv6addr_maskcmp(const net_ipv6addr_t addr1,
* Name: net_is_addr_unspecified
*
* Description:
* Is Ithe Pv6 address the unspecified address?
* Is Ithe IPv6 address the unspecified address?
*
****************************************************************************/

2
include/nuttx/net/netdev.h
View File

@@ -3,7 +3,7 @@
* Defines architecture-specific device driver interfaces to the NuttX
* network.
*
* Copyright (C) 2007, 2009, 2011-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2007, 2009, 2011-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derived largely from portions of uIP with has a similar BSD-styple license:

36
include/nuttx/net/sixlowpan.h
View File

@@ -126,15 +126,39 @@
#define SIXLOWPAN_DISPATCH_FRAGN 0xe0 /* 11100xxx Fragmentation header (subsequent) */
#define SIXLOWPAN_DISPATCH_FRAG_MASK 0xf8 /* 11111000 */
/* HC1 encoding */
/* HC1 encoding (RFC4944)
*
* PI: Prefix carried in-line
* PC: Prefix compressed (link-local prefix assumed)
* II: Interface identifier carried in-line
* IC: Interface identifier elided (derivable from the corresponding
* link-layer address).
*/
#define SIXLOWPAN_HC1_NH_UDP 0x02
#define SIXLOWPAN_HC1_NH_TCP 0x06
#define SIXLOWPAN_HC1_NH_ICMP6 0x04
#define SIXLOWPAN_HC1_SRCADDR_MASK 0xc0 /* Bits 0-1: IPv6 source address */
# define SIXLOWPAN_HC1_SRCADDR_PIII 0x00 /* PI,II */
# define SIXLOWPAN_HC1_SRCADDR_PIIC 0x40 /* PI,IC */
# define SIXLOWPAN_HC1_SRCADDR_PCII 0x80 /* PC,II */
# define SIXLOWPAN_HC1_SRCADDR_PCIC 0xc0 /* PC,IC */
#define SIXLOWPAN_HC1_DESTADDR_MASK 0x30 /* Bits 2-3: IPv6 destination address */
# define SIXLOWPAN_HC1_DESTADDR_PIII 0x00 /* PI,II */
# define SIXLOWPAN_HC1_DESTADDR_PIIC 0x10 /* PI,IC */
# define SIXLOWPAN_HC1_DESTADDR_PCII 0x20 /* PC,II */
# define SIXLOWPAN_HC1_DESTADDR_PCIC 0x30 /* PC,IC */
#define SIXLOWPAN_HC1_TCFL_C 0x08 /* Bit 4: Traffic class and flow label are zero */
#define SIXLOWPAN_HC1_NH_MASK 0x06 /* Bits 5-6: Next HC1 header type */
# define SIXLOWPAN_HC1_NH_NC 0x00 /* Not compressed */
# define SIXLOWPAN_HC1_NH_UDP 0x02 /* UDP */
# define SIXLOWPAN_HC1_NH_ICMPv6 0x04 /* ICMPv6 */
# define SIXLOWPAN_HC1_NH_TCP 0x06 /* TCP */
#define SIXLOWPAN_HC1_H2ENCODE 0x01 /* Bit 0: HC2 encoding follows */
/* HC_UDP encoding (works together with HC1) */
#define SIXLOWPAN_HC_UDP_ALL_C 0xe0
#define SIXLOWPAN_HC_UDP_SRCPORT_C 0x80 /* Source port compressed to 4 bits */
#define SIXLOWPAN_HC_UDP_DESTPORT_C 0x40 /* Destination port compressed to 4 bits */
#define SIXLOWPAN_HC_UDP_LENGTH _C 0x20 /* Elided, compute from IPv6 length */
#define SIXLOWPAN_HC_UDP_ALL_C 0xe0 /* All commpressed */
/* IPHC encoding
*
@@ -146,7 +170,7 @@
# define SIXLOWPAN_IPHC_TC_00 0x00 /* ECN+DSCP+4-bit Pad+Flow Label (4 bytes) */
# define SIXLOWPAN_IPHC_TC_01 0x08 /* ECN+2-bit Pad+ Flow Label (3 bytes), DSCP is elided. */
# define SIXLOWPAN_IPHC_TC_10 0x10 /* ECN+DSCP (1 byte), Flow Label is elided */
# define SIXLOWPAN_IPHC_TC_11 0x11 /* Traffic Class and Flow Label are elided */
# define SIXLOWPAN_IPHC_TC_11 0x18 /* Traffic Class and Flow Label are elided */
#define SIXLOWPAN_IPHC_NH 0x04 /* Bit 5: Next Header Compressed */
#define SIXLOWPAN_IPHC_HLIM_MASK 0x03 /* Bits 6-7: Hop Limit */
# define SIXLOWPAN_IPHC_HLIM_INLINE 0x00 /* Carried in-line */

174
include/nuttx/wireless/ieee802154/ieee802154_mac.h
View File

@@ -60,6 +60,14 @@
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if !defined(CONFIG_MAC802154_NPANDESC) || CONFIG_MAC802154_NPANDESC <= 0
# undef CONFIG_MAC802154_NPANDESC
# define CONFIG_MAC802154_NPANDESC 5
#endif
#define MAC802154_NPANDESC CONFIG_MAC802154_NPANDESC
/* IEEE 802.15.4 address macros */
/* Copy a an IEEE 802.15.4 address */
@@ -97,8 +105,6 @@
#define IEEE802154_SADDR_BCAST ((uint8_t[]){0xFE,0xFF})
#define IEEE802154_EADDR_UNSPEC ((uint8_t[]){0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF})
/* Configuration ************************************************************/
/* None at the moment */
/* IEEE 802.15.4 MAC Character Driver IOCTL Commands ************************/
@@ -111,9 +117,9 @@
* - Response
* - Confirm
*
* Of these, Request and Response primitives are sent from the next highest layer
* to the MLME. Indication and Confirm primitives are used to notify the next
* highest layer of changes or actions that have taken place.
* Of these, Request and Response primitives are sent from the next highest
* layer to the MLME. Indication and Confirm primitives are used to notify the
* next highest layer of changes or actions that have taken place.
*
* The MAC802154 character driver exposed here provides IOCTL hooks for all
* Request and Response primitives.
@@ -160,8 +166,53 @@
#define IEEE802154_FRAMECTRL_SHIFT_VERSION 12 /* Source addressing mode, bits 12-13 */
#define IEEE802154_FRAMECTRL_SHIFT_SADDR 14 /* Source addressing mode, bits 14-15 */
/* Superframe Specification field masks, 2 bytes
* Seee IEEE 802.15.4/2011 5.2.2.1.2 page 62
*/
#define IEEE802154_SFSPEC_BEACONORDER 0x000F /* Beacon order, bits 0-3 */
#define IEEE802154_SFSPEC_SFORDER 0x00F0 /* Superframe Order, bit 4-7 */
#define IEEE802154_SFSPEC_FINCAPSLOT 0x0F00 /* Final CAP Slot, bit 8-11 */
#define IEEE802154_SFSPEC_BLE 0x1000 /* Battery Life Ext, bit 12 */
#define IEEE802154_SFSPEC_PANCOORD 0x4000 /* PAN Coordinator, bit 14 */
#define IEEE802154_SFSPEC_ASSOCPERMIT 0x8000 /* Association Permit, bit 15 */
#define IEEE802154_SFSPEC_SHIFT_BEACONORDER 0 /* Beacon order, bits 0-3 */
#define IEEE802154_SFSPEC_SHIFT_SFORDER 4 /* Superframe order, bit 4-7 */
#define IEEE802154_SFSPEC_SHIFT_FINCAPSLOT 8 /* Final CAP Slot, bit 8-11 */
#define IEEE802154_SFSPEC_SHIFT_BLE 12 /* Battery Life Ext, bit 12 */
#define IEEE802154_SFSPEC_SHIFT_PANCOORD 14 /* PAN Coordinator, bit 14 */
#define IEEE802154_SFSPEC_SHIFT_ASSOCPERMIT 15 /* Association Permit, bit 15 */
/* GTS Specification field masks, 1 byte
* Seee IEEE 802.15.4/2011 5.2.2.1.3 page 63
*/
#define IEEE802154_GTSSPEC_DESCCOUNT 0x07 /* GTS Desc. count, bits 0-2 */
#define IEEE802154_GTSSPEC_PERMIT 0x80 /* GTS Desc. count, bit 7 */
#define IEEE802154_GTSSPEC_SHIFT_DESCCOUNT 0 /* GTS Desc. count, bits 0-2 */
#define IEEE802154_GTSSPEC_SHIFT_PERMIT 7 /* GTS Desc. count, bit 7 */
/* GTS Directions field masks, 1 byte
* Seee IEEE 802.15.4/2011 5.2.2.1.3 page 63
*/
#define IEEE802154_GTSDIR_MASK 0x7F /* GTS Directions Mask, bits 0-6 */
#define IEEE802154_GTSDIR_SHIFT_MASK 0 /* GTS Directions Mask, bits 0-6 */
/* Pending address specifications field masks, 1 byte
* See IEEE 802.15.4/2011 5.2.2.1.6 page 64
*/
#define IEEE802154_PENDADDR_NSADDR 0x07 /* # of short addresses, bits 0-2 */
#define IEEE802154_PENDADDR_NEADDR 0x70 /* # of extended addresses, bits 4-6 */
#define IEEE802154_PENDADDR_SHIFT_NSADDR 0 /* # of short addresses, bits 0-2 */
#define IEEE802154_PENDADDR_SHIFT_NEADDR 4 /* # of extended addresses, bits 4-6 */
/* Capability Information Bitfield
*
*/
#define IEEE802154_CAPABILITY_DEVTYPE 0x02
@@ -203,7 +254,6 @@
#define IEEE802154_MAX_MPDU_UNSEC_OVERHEAD \
(IEEE802154_MAX_UNSEC_MHR_OVERHEAD + IEEE802154_MFR_LENGTH)
#define IEEE802154_MAX_SAFE_MAC_PAYLOAD_SIZE \
(IEEE802154_MAX_PHY_PACKET_SIZE - IEEE802154_MAX_MPDU_UNSEC_OVERHEAD)
@@ -220,7 +270,6 @@
#define MAX_ORPHAN_ADDR 32 /* REVISIT */
/****************************************************************************
* Public Types
****************************************************************************/
@@ -232,7 +281,7 @@ enum ieee802154_status_e
/* This first section of enums is defined in the standard. [1] pg. 70
* They must be in this order
*/
IEEE802154_STATUS_SUCCESS = 0,
IEEE802154_STATUS_OUT_OF_CAPACITY,
IEEE802154_STATUS_DENIED,
@@ -265,6 +314,7 @@ enum ieee802154_status_e
IEEE802154_STATUS_TX_ACTIVE,
IEEE802154_STATUS_UNAVAILABLE_KEY,
IEEE802154_STATUS_UNSUPPORTED_ATTRIBUTE,
IEEE802154_STATUS_LIMITREACHED,
};
static const char *IEEE802154_STATUS_STRING[] =
@@ -292,6 +342,7 @@ static const char *IEEE802154_STATUS_STRING[] =
"Tx active",
"Unavailable key",
"Unsupported attribute",
"Limit reached",
};
/* IEEE 802.15.4 PHY/MAC PIB attributes IDs */
@@ -300,7 +351,7 @@ enum ieee802154_attr_e
{
/* PHY PIB Attributes */
IEEE802154_ATTR_PHY_CURRENT_CHANNEL = 0x00,
IEEE802154_ATTR_PHY_CHAN = 0x00,
IEEE802154_ATTR_PHY_CHANNELS_SUPPORTED,
IEEE802154_ATTR_PHY_TX_POWER_TOLERANCE,
IEEE802154_ATTR_PHY_TX_POWER,
@@ -340,7 +391,7 @@ enum ieee802154_attr_e
/* MAC PIB Attributes */
IEEE802154_ATTR_MAC_EXTENDED_ADDR = 0x40,
IEEE802154_ATTR_MAC_EADDR = 0x40,
IEEE802154_ATTR_MAC_ACK_WAIT_DUR,
IEEE802154_ATTR_MAC_ASSOCIATED_PANCOORD,
IEEE802154_ATTR_MAC_ASSOCIATION_PERMIT,
@@ -352,8 +403,8 @@ enum ieee802154_attr_e
IEEE802154_ATTR_MAC_BEACON_ORDER,
IEEE802154_ATTR_MAC_BEACON_TX_TIME,
IEEE802154_ATTR_MAC_BSN,
IEEE802154_ATTR_MAC_COORD_EXT_ADDR,
IEEE802154_ATTR_MAC_COORD_SHORT_ADDR,
IEEE802154_ATTR_MAC_COORD_EADDR,
IEEE802154_ATTR_MAC_COORD_SADDR,
IEEE802154_ATTR_MAC_DSN,
IEEE802154_ATTR_MAC_GTS_PERMIT,
IEEE802154_ATTR_MAC_MAX_BE,
@@ -369,7 +420,7 @@ enum ieee802154_attr_e
IEEE802154_ATTR_MAC_RESPONSE_WAIT_TIME,
IEEE802154_ATTR_MAC_RX_ON_WHEN_IDLE,
IEEE802154_ATTR_MAC_SECURITY_ENABLED,
IEEE802154_ATTR_MAC_SHORT_ADDRESS,
IEEE802154_ATTR_MAC_SADDR,
IEEE802154_ATTR_MAC_SUPERFRAME_ORDER,
IEEE802154_ATTR_MAC_SYNC_SYMBOL_OFFSET,
IEEE802154_PIB_MAC_TIMESTAMP_SUPPORT,
@@ -511,31 +562,31 @@ struct ieee802154_capability_info_s
* 0=otherwise */
};
struct ieee802154_superframe_spec_s
struct ieee802154_superframespec_s
{
uint16_t beacon_order : 4; /* Transmission interval of beacon */
uint16_t superframe_order : 4; /* Length of superframe */
uint16_t final_cap_slot : 4; /* Last slot utilized by CAP */
uint16_t ble : 1; /* Battery Life Extension (BLE) */
uint16_t reserved : 1; /* Reserved bit */
uint16_t pan_coordinator : 1; /* 1 if beacon sent by pan coordinator */
uint16_t assoc_permit : 1; /* 1 if coordinator is accepting associaton */
uint16_t beaconorder : 4; /* Transmission interval of beacon */
uint16_t sforder : 4; /* Length of active portion of superframe */
uint16_t final_capslot : 4; /* Last slot utilized by CAP */
uint16_t ble : 1; /* Battery Life Extension (BLE) */
uint16_t reserved : 1; /* Reserved bit */
uint16_t pancoord : 1; /* 1 if beacon sent by pan coordinator */
uint16_t assocpermit : 1; /* 1 if coordinator is accepting associaton */
};
struct ieee802154_pan_desc_s
struct ieee802154_pandesc_s
{
/* The coordinator address of the received beacon frame */
struct ieee802154_addr_s coord_addr;
struct ieee802154_addr_s coordaddr;
uint8_t channel; /* current channel occupied by the network */
uint8_t channel_page; /* current channel page occupied by the network */
uint8_t chan; /* current channel occupied by the network */
uint8_t chpage; /* current channel page occupied by the network */
/* The superframe specifications received in the beacon frame */
struct ieee802154_superframe_spec_s superframe_spec;
struct ieee802154_superframespec_s sfspec;
uint8_t gts_permit; /* 0=No GTS requests allowed
uint8_t gtspermit; /* 0=No GTS requests allowed
* 1=GTS request allowed */
uint8_t lqi; /* Link Quality Indication of the beacon */
uint32_t timestamp; /* Time at which the beacon frame was received
@@ -574,13 +625,13 @@ union ieee802154_macattr_u
uint8_t saddr[IEEE802154_SADDRSIZE];
uint8_t panid[IEEE802154_PANIDSIZE];
uint8_t coord_eaddr[IEEE802154_EADDRSIZE];
uint8_t coord_saddr[IEEE802154_SADDRSIZE];
uint8_t coordeaddr[IEEE802154_EADDRSIZE];
uint8_t coordsaddr[IEEE802154_SADDRSIZE];
enum ieee802154_devmode_e devmode;
bool is_assoc;
bool assoc_permit;
bool assocpermit;
bool auto_req;
bool batt_life_ext;
bool gts_permit;
@@ -611,7 +662,7 @@ union ieee802154_macattr_u
uint8_t beacon_order;
uint32_t beacon_tx_time : 24;
uint8_t superframe_order;
uint8_t superframeorder;
uint8_t bsn;
uint8_t dsn;
@@ -619,7 +670,7 @@ union ieee802154_macattr_u
union ieee802154_phyattr_u
{
uint8_t channel;
uint8_t chan;
int32_t txpwr;
uint32_t symdur_picosec;
/* TODO: Fill this out as we implement supported get/set commands */
@@ -845,8 +896,38 @@ struct ieee802154_purge_req_s
struct ieee802154_assoc_req_s
{
uint8_t chnum; /* Channel number to attempt association */
uint8_t chpage; /* Channel page to attempt association */
uint8_t chan; /* Channel number to attempt association */
uint8_t chpage; /* Channel page to attempt association */
/* TODO:
* This is a non-standard field. I believe there is a catch 22 in the
* standard and until I can figure it out, I'm adding this boolean to let the
* application tell the MAC whether it is trying to assocaite with a beacon
* enabled PAN or non-beacon enabled PAN. If it is beacon-enabled, the MAC
* will track the beacon first before transmitting the association. This can
* take some time depending on the beacon interval. If the PAN is non-beacon
* enabled, the association request is sent immediately via CSMA.
*
* The catch 22: The standard outlines the procedure for associating: reset
* the MAC, scan to find PAN's and pass coordinator address info to
* application, application calls associate passing address info of
* coordinator. Which sounds good. The problem is that the primitive has no
* field for determining if the PAN we are trying to join is beacon enabled
* or not. Which means we don't know whether to tranmsit immediately or try
* to track the beacon. The standard does say that ALL command frames should
* be sent during the Contention Access Period (CAP), but how could you send
* it at the rigth tiem, if you are not tracking the beacon. What's worse is
* in the association section, it says if you are tracking the beacon, to
* send the association request during the CAP. But how can you track the
* beacon if you are not associated. Normally tracking the beacon would be
* triggered by the SYNC.request primitive. But from my understanding that
* primitive is intended to be used AFTER association since it requires the
* MAC to already have a coordinator address and PAN ID so that it can track
* the beacon frames properly. Which, of course, how could the MAC have that
* info if it is not associated.
*/
bool beacon;
/* Coordinator Address with which to associate */
@@ -1037,7 +1118,7 @@ struct ieee802154_beaconnotify_ind_s
/* PAN descriptor for the received beacon */
struct ieee802154_pan_desc_s pan_desc;
struct ieee802154_pandesc_s pandesc;
/* Beacon pending addresses */
@@ -1238,20 +1319,17 @@ struct ieee802154_scan_req_s
{
enum ieee802154_scantype_e type;
uint8_t duration;
uint8_t ch_page;
uint8_t chpage;
uint8_t channels[15];
uint8_t numchan;
#ifdef CONFIG_IEEE802154_SECURITY
/* Security information if enabled */
struct ieee802154_security_s security;
#endif
uint8_t channels[1];
};
#define SIZEOF_IEEE802154_SCAN_REQ_S(n) \
(sizeof(struct ieee802154_scan_req_s) + (n) - 1)
/*****************************************************************************
* Primitive: MLME-SCAN.confirm
*
@@ -1264,10 +1342,12 @@ struct ieee802154_scan_conf_s
{
enum ieee802154_status_e status;
enum ieee802154_scantype_e type;
uint8_t ch_page;
uint8_t num_channels;
/* TODO: Figure out how to handle missing primitive semantics. See standard. */
uint8_t chpage;
uint8_t unscanned[15];
uint8_t numunscanned;
uint8_t numdesc;
struct ieee802154_pandesc_s pandescs[MAC802154_NPANDESC];
uint8_t edlist[MAC802154_NPANDESC];
};
/*****************************************************************************
@@ -1318,7 +1398,7 @@ struct ieee802154_set_req_s
struct ieee802154_start_req_s
{
uint8_t panid[IEEE802154_PANIDSIZE];
uint8_t chnum;
uint8_t chan;
uint8_t chpage;
uint32_t starttime : 24;

22
include/nuttx/wireless/ieee802154/ieee802154_radio.h
View File

@@ -89,6 +89,18 @@ struct ieee802154_txdesc_s
/* TODO: Add slotting information for GTS transactions */
};
struct ieee802154_beaconframe_s
{
uint8_t bf_data[IEEE802154_MAX_PHY_PACKET_SIZE];
uint8_t bf_len;
uint8_t bf_offset;
};
enum ieee802154_sfevent_e
{
IEEE802154_SFEVENT_ENDOFACTIVE,
};
/* IEEE802.15.4 Radio Interface Operations **********************************/
struct ieee802154_radiocb_s
@@ -99,6 +111,8 @@ struct ieee802154_radiocb_s
FAR struct ieee802154_txdesc_s *tx_desc);
CODE void (*rxframe) (FAR const struct ieee802154_radiocb_s *radiocb,
FAR struct ieee802154_data_ind_s *ind);
CODE void (*sfevent) (FAR const struct ieee802154_radiocb_s *radiocb,
enum ieee802154_sfevent_e sfevent);
};
struct ieee802154_radio_s
@@ -119,6 +133,14 @@ struct ieee802154_radio_s
CODE int (*rxenable) (FAR struct ieee802154_radio_s *radio, bool enable);
CODE int (*req_rxenable)(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_rxenable_req_s *req);
CODE int (*beaconstart)(FAR struct ieee802154_radio_s *radio,
FAR const struct ieee802154_superframespec_s *sfspec,
FAR struct ieee802154_beaconframe_s *beacon);
CODE int (*beaconupdate)(FAR struct ieee802154_radio_s *radio,
FAR struct ieee802154_beaconframe_s *beacon);
CODE int (*beaconstop)(FAR struct ieee802154_radio_s *radio);
CODE int (*sfupdate)(FAR struct ieee802154_radio_s *radio,
FAR const struct ieee802154_superframespec_s *sfspec);
};
#ifdef __cplusplus

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