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@@ -560,7 +560,7 @@ o SMP
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This would also be an essential part of a high priority,
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This would also be an essential part of a high priority,
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nested interrupt implementation (unrelated).
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nested interrupt implementation (unrelated).
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Status: Open
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Status: Open
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Priority: Low. There are no know issues with the current non-maskable
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Priority: Low. There are no known issues with the current non-maskable
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SGI implementation. This change would, however, lead to
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SGI implementation. This change would, however, lead to
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simplification in the design and permit commonality with
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simplification in the design and permit commonality with
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other, non-GIC implementations.
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other, non-GIC implementations.
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@@ -169,6 +169,30 @@ Status
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But this does not completely eliminate instabilities which seem to be
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But this does not completely eliminate instabilities which seem to be
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related to memory corruption -- mm_mallinfo() asserts.
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related to memory corruption -- mm_mallinfo() asserts.
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CORTEX-A GIC SGI INTERRUPT MASKING (From the top-level TODO list)
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-----------------------------------------------------------------
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In the ARMv7-A GICv2 architecture, the inter-processor interrupts (SGIs) are
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non maskable and will occur even if interrupts are disabled. This adds a
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lot of complexity to the ARMV7-A critical section design.
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Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR register to
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control SGI interrupts. This register (much like the ARMv7-M BASEPRI
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register) can be used to mask interrupts by interrupt priority. Since SGIs
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may be assigned priorities the ICCMPR should be able to block execution of
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SGIs as well.
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Such an implementation would be very similar to the BASEPRI (vs PRIMASK)
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implementation for the ARMv7-M: (1) The up_irq_save() and up_irq_restore()
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registers would have to set/restore the ICCMPR register, (2) register setup
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logic in arch/arm/src/armv7-a for task start-up and signal dispatch would
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have to set the ICCMPR correctly, and (3) the 'xcp' structure would have to
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be extended to hold the ICCMPR register; logic would have to added be
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save/restore the ICCMPR register in the 'xcp' structure on each interrupt
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and context switch.
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This would also be an essential part of a high priority, nested interrupt
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implementation (unrelated feature).
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Platform Features
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Platform Features
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=================
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=================
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