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Fix some SPI bit bang timing. I still don't think it is working properly; I am going to need to borrow a logic analyzer

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This commit is contained in:
Gregory Nutt
2013-07-05 11:45:17 -06:00
parent 37ed44a1ee
commit a9e04b3f47
2 changed files with 133 additions and 92 deletions
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configs/sure-pic32mx/README.txt
+12 -7
View File
@@ -803,12 +803,14 @@ Where <subdir> is one of the following:
CONFIG_DEBUG_LCD=y : Enable LCD debug output CONFIG_DEBUG_LCD=y : Enable LCD debug output
NOTES: NOTES:
a. I do not have the LCD1602 working. I may just be getting lost in the 2013-05-27: The LCD1602 has been verified on the DB-DP11212 using
tangle of wires or perhaps there is something fundamentally wrong with this configuration. It has not been used with the usbnsh configuration
the code. or with the DB-11112 board. It looks to me like the connection to the
b. At this point in time, testing of the SLCD is very limited because LCD1602 is identical on the DB-11112 and so I would expect that to work.
there is not much in apps/examples/slcd. Basically driver with a working
test setup and ready to be tested and debugged. At this point in time, testing of the SLCD is very limited because
there is not much in apps/examples/slcd. Basically driver with a working
test setup and ready to be tested and debugged.
usbnsh: usbnsh:
======= =======
@@ -956,5 +958,8 @@ Where <subdir> is one of the following:
CONFIG_RAMLOG_CONSOLE_BUFSIZE=8192 CONFIG_RAMLOG_CONSOLE_BUFSIZE=8192
STATUS:
2013-7-4: This configuration was last verified.
7. See the notes for the nsh configuration. Most also apply to the usbnsh 7. See the notes for the nsh configuration. Most also apply to the usbnsh
configuration. configuration as well.
include/nuttx/spi/spi_bitbang.c
+121 -85
View File
@@ -330,14 +330,19 @@ static void spi_setmode(FAR struct spi_bitbang_s *priv,
* rising edge and data is propagated on the falling edge (high->low * rising edge and data is propagated on the falling edge (high->low
* transition). * transition).
* *
* hold time * /CS --+
* +------------+ * |
* | | hold time * +-----------------------------------------------------------------
* -----+ +------------ * <-hold time-> <-hold time-><-hold time-><-hold time-><-hold time->
* | | `- Propagate to next bit * +------------+ +------------+
* | | * | | | |
* | `- MISO sampled * SCLK ---------------+ +------------+ +------------
* ` Set MOSI * ` Set MOSI | `- Set MOSI | `- Set MOSI
* | |
* `- Sample MISO `- Sample MISO
*
* MISO <------------X------------><-----------X------------>
* MOSO
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
@@ -352,28 +357,33 @@ static void spi_setmode(FAR struct spi_bitbang_s *priv,
static uint16_t spi_bitexchange0(uint16_t dataout, uint32_t holdtime) static uint16_t spi_bitexchange0(uint16_t dataout, uint32_t holdtime)
{ {
uint16_t datain; uint16_t datain;
/* No clock transition before setting MOSI */
/* Here the clock is is in the resting set (low). Set MOSI output and wait
* for the hold time
*/
if (dataout != 0) if (dataout != 0)
{ {
SPI_SETMOSI; /* Set MOSI if the bit is set */ SPI_SETMOSI;
} }
else else
{ {
SPI_CLRMOSI; /* Clear MOSI if the bit is not set */ SPI_CLRMOSI;
} }
SPI_SETSCK; /* Clock transition before getting MISO */ spi_delay(holdtime);
datain = (uint16_t)SPI_GETMISO; /* Get bit 0 = MISO value */
if (holdtime > 0)
{
spi_delay(holdtime);
}
SPI_CLRSCK; /* Return clock to the resting state */ /* Set the clock high and sample MISO */
if (holdtime > 0)
{ SPI_SETSCK;
spi_delay(holdtime); datain = (uint16_t)SPI_GETMISO;
}
/* Wait the required amount of hold time then put the clock back in the
* resting state.
*/
spi_delay(holdtime);
SPI_CLRSCK;
return datain; return datain;
} }
@@ -389,14 +399,19 @@ static uint16_t spi_bitexchange0(uint16_t dataout, uint32_t holdtime)
* The base value of the clock is zero. Data is captured on the clock's * The base value of the clock is zero. Data is captured on the clock's
* falling edge and data is propagated on the rising edge * falling edge and data is propagated on the rising edge
* *
* hold time * /CS --+
* +------------+ * |
* | | hold time * +-----------------------------------------------------------------
* -----+ +------------ * <-hold time-> <-hold time-><-hold time-><-hold time-><-hold time->
* | | `- MISO sampled * +------------+ +------------+
* | | * | | | |
* | `- Propagate to next bit * SCLK -+ +------------+ +------------
* ` Set MOSI * ` Set MOSI | `- Set MOSI |
* | |
* `- Sample MISO `- Sample MISO
*
* MISO <-----------X-------------><----------X------------->
* MOSO
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
@@ -412,28 +427,31 @@ static uint16_t spi_bitexchange1(uint16_t dataout, uint32_t holdtime)
{ {
uint16_t datain; uint16_t datain;
SPI_SETSCK; /* Clock transition before setting MOSI */ /* The clock should be in the resting state (low). Set the clock to the
* high state and set MOSI.
*/
SPI_SETSCK;
if (dataout != 0) if (dataout != 0)
{ {
SPI_SETMOSI; /* Set MOSI if the bit is set */ SPI_SETMOSI;
} }
else else
{ {
SPI_CLRMOSI; /* Clear MOSI if the bit is not set */ SPI_CLRMOSI;
} }
if (holdtime > 0) /* Wait for the required hold time then put the clock back into the
{ * resting (low) state.
spi_delay(holdtime); */
}
SPI_CLRSCK; /* Clock transition before getting MISO */ spi_delay(holdtime);
datain = (uint16_t)SPI_GETMISO; /* Get bit 0 = MISO value */ SPI_CLRSCK;
/* Clock is in resting state */
if (holdtime > 0) /* Sample MISO on the falling edge and wait for the hold time again */
{
spi_delay(holdtime); datain = (uint16_t)SPI_GETMISO;
} spi_delay(holdtime);
return datain; return datain;
} }
@@ -449,14 +467,19 @@ static uint16_t spi_bitexchange1(uint16_t dataout, uint32_t holdtime)
* The base value of the clock is one. Data is captured on the clock's * The base value of the clock is one. Data is captured on the clock's
* falling edge and data is propagated on the rising edge. * falling edge and data is propagated on the rising edge.
* *
* hold time * /CS --+
* -----+ +------------ * |
* | | hold time * +-----------------------------------------------------------------
* +------------+ * <-hold time-> <-hold time-><-hold time-><-hold time-><-hold time->
* | | `- Propagate to next bit * ---------------+ +------------+ +------------
* | | * | | | |
* | `- MISO sampled * SCLK +------------+ +------------+
* ` Set MOSI * ` Set MOSI | `- Set MOSI | `- Set MOSI
* | |
* `- Sample MISO `- Sample MISO
*
* MISO <------------X------------><-----------X------------>
* MOSO
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
@@ -471,28 +494,33 @@ static uint16_t spi_bitexchange1(uint16_t dataout, uint32_t holdtime)
static uint16_t spi_bitexchange2(uint16_t dataout, uint32_t holdtime) static uint16_t spi_bitexchange2(uint16_t dataout, uint32_t holdtime)
{ {
uint16_t datain; uint16_t datain;
/* No clock transition before setting MOSI */
/* Here the clock is is in the resting set (high). Set MOSI output and wait
* for the hold time
*/
if (dataout != 0) if (dataout != 0)
{ {
SPI_SETMOSI; /* Set MOSI if the bit is set */ SPI_SETMOSI;
} }
else else
{ {
SPI_CLRMOSI; /* Clear MOSI if the bit is not set */ SPI_CLRMOSI;
} }
SPI_CLRSCK; /* Clock transition before getting MISO */ spi_delay(holdtime);
datain = (uint16_t)SPI_GETMISO; /* Get bit 0 = MISO value */
if (holdtime > 0)
{
spi_delay(holdtime);
}
SPI_SETSCK; /* Return clock to the resting state */ /* Set the clock low and sample MISO */
if (holdtime > 0)
{ SPI_CLRSCK;
spi_delay(holdtime); datain = (uint16_t)SPI_GETMISO;
}
/* Wait the required amount of hold time then put the clock back in the
* resting state (high).
*/
spi_delay(holdtime);
SPI_SETSCK;
return datain; return datain;
} }
@@ -508,14 +536,19 @@ static uint16_t spi_bitexchange2(uint16_t dataout, uint32_t holdtime)
* The base value of the clock is one. Data is captured on the clock's * The base value of the clock is one. Data is captured on the clock's
* rising edge and data is propagated on the falling edge. * rising edge and data is propagated on the falling edge.
* *
* hold time * /CS --+
* -----+ +------------ * |
* | | hold time * +-----------------------------------------------------------------
* +------------+ * <-hold time-> <-hold time-><-hold time-><-hold time-><-hold time->
* | | `- MISO sampled * -+ +------------+ +------------
* | | * | | | |
* | `- Propagate to next bit * SCLK +------------+ +------------+
* ` Set MOSI * ` Set MOSI | `- Set MOSI |
* | |
* `- Sample MISO `- Sample MISO
*
* MISO <-----------X-------------><----------X------------->
* MOSO
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
@@ -531,6 +564,10 @@ static uint16_t spi_bitexchange3(uint16_t dataout, uint32_t holdtime)
{ {
uint16_t datain; uint16_t datain;
/* The clock should be in the resting state (high). Set the clock to the
* low state and set MOSI.
*/
SPI_CLRSCK; /* Clock transition before setting MOSI */ SPI_CLRSCK; /* Clock transition before setting MOSI */
if (dataout != 0) if (dataout != 0)
{ {
@@ -541,18 +578,17 @@ static uint16_t spi_bitexchange3(uint16_t dataout, uint32_t holdtime)
SPI_CLRMOSI; /* Clear MOSI if the bit is not set */ SPI_CLRMOSI; /* Clear MOSI if the bit is not set */
} }
if (holdtime > 0) /* Wait for the required hold time then put the clock back into the
{ * resting (high) state.
spi_delay(holdtime); */
}
SPI_SETSCK; /* Clock transition before getting MISO */ spi_delay(holdtime);
datain = (uint16_t)SPI_GETMISO; /* Get bit 0 = MISO value */ SPI_SETSCK;
/* Clock is in resting state */
if (holdtime > 0) /* Sample MISO on the rising edge and wait for the hold time again */
{
spi_delay(holdtime); datain = (uint16_t)SPI_GETMISO;
} spi_delay(holdtime);
return datain; return datain;
} }