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A few more fixes for LPC1788 compilation (still more needed)

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5650 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2013-02-13 15:59:10 +00:00
parent 868455a291
commit a8abef3907
1 changed files with 4 additions and 4 deletions
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configs/open1788/include/board.h
+4 -4
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@@ -84,7 +84,7 @@
*/ */
#define BOARD_CCLKCFG_DIVIDER 6 #define BOARD_CCLKCFG_DIVIDER 6
#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) #define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT)
/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). /* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK).
* *
@@ -100,10 +100,10 @@
#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN #define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
#define BOARD_PLL0CFG_MSEL 20 #define BOARD_PLL0CFG_MSEL 20
#define BOARD_PLL0CFG_NSEL 1 #define BOARD_PLL0CFG_PSEL 1
#define BOARD_PLL0CFG_VALUE \ #define BOARD_PLL0CFG_VALUE \
(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) ((BOARD_PLL0CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
/* PLL1 -- Not used. */ /* PLL1 -- Not used. */