Squashed commit of the following:

Update some comments
    drivers/usbhost/usbhost_max3421e.c:  Fix issue with uninitialized data.

arch/arm/src/stm32/stm32_spi.c

@@ -1690,7 +1690,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
    *   Mode 0:                        CR1.CPHA=0 and CR1.CPOL=0
    *   Master:                        CR1.MSTR=1
    *   8-bit:                         CR2.DS=7
-   *   MSB tranmitted first:          CR1.LSBFIRST=0
+   *   MSB transmitted first:         CR1.LSBFIRST=0
    *   Replace NSS with SSI & SSI=1:  CR1.SSI=1 CR1.SSM=1 (prevents MODF error)
    *   Two lines full duplex:         CR1.BIDIMODE=0 CR1.BIDIOIE=(Don't care) and CR1.RXONLY=0
    */
@@ -1708,7 +1708,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
    *   Mode 0:                        CPHA=0 and CPOL=0
    *   Master:                        MSTR=1
    *   8-bit:                         DFF=0
-   *   MSB tranmitted first:          LSBFIRST=0
+   *   MSB transmitted first:         LSBFIRST=0
    *   Replace NSS with SSI & SSI=1:  SSI=1 SSM=1 (prevents MODF error)
    *   Two lines full duplex:         BIDIMODE=0 BIDIOIE=(Don't care) and RXONLY=0
    */

configs/viewtool-stm32f107/README.txt

@@ -706,33 +706,35 @@ MAX3421E Integration
 
   Using SPI1on J8 pins 7-12, discretes on J18
 
-    ------ ----------- -----------
+    ------ ----------- ----------- ------------------
-    NAME   VIEWTOOL    STM32
+    NAME   VIEWTOOL    STM32       USBHostShield-v13
-    ------ ----------- -----------
+    ------ ----------- ----------- ------------------
-    CS#    J8  Pin 12  PA4/NSS1
+    CS#    J8  Pin 12  PA4/NSS1    D10
-    SCK    J8  Pin 11  PA5/SCK1
+    SCK    J8  Pin 11  PA5/SCK1    D13
-    MISO   J8  Pin  9  PA6/MISO1
+    MISO   J8  Pin  9  PA6/MISO1   D12
-    MOSI   J8  Pin 10  PA7/MOSI1
+    MOSI   J8  Pin 10  PA7/MOSI1   D11
-    INT#   J18 Pin  6  PC5
+    INT#   J18 Pin 10  PA0         D9
-    RST#   J18 Pin  8  PA1
+    RST#   J18 Pin  8  PA1         D7
-    VBUS   J18 Pin 10  PA0
+    GPX                            D8
-    3.3V   J8  Pin 7
+    VBUS   J18 Pin  2  5V          VIN
-    GND    J8  Pin 8
+    3.3V   J8  Pin  7              N/C
+    GND    J8  Pin  8              GND
 
   Using SPI2 on J8 pins 1-6, discretes on J18
 
-    ------ ----------- -----------
+    ------ ----------- ----------- ------------------
-    NAME   VIEWTOOL    STM32
+    NAME   VIEWTOOL    STM32       USBHostShield-v13
-    ------ ----------- -----------
+    ------ ----------- ----------- ------------------
-    CS#    J8  Pin  6  PB12/NSS2
+    CS#    J8  Pin  6  PB12/NSS2   D10
-    SCK    J8  Pin  5  PB13/SCK2
+    SCK    J8  Pin  5  PB13/SCK2   D13
-    MISO   J8  Pin  3  PB14/MISO2
+    MISO   J8  Pin  3  PB14/MISO2  D12
-    MOSI   J8  Pin  4  PB15/MOSI2
+    MOSI   J8  Pin  4  PB15/MOSI2  D11
-    INT#   J18 Pin  6  PC5
+    INT#   J18 Pin 10  PA0         D9
-    RST#   J18 Pin  8  PA1
+    RST#   J18 Pin  8  PA1         D7
-    VBUS   J18 Pin 10  PA0
+    GPX                            D8
-    3.3V   J8  Pin 1
+    VBUS   J18 Pin  2  5V          VIN
-    GND    J8  Pin 2
+    3.3V   J8  Pin  1              N/C
+    GND    J8  Pin  2              GND
 
   5V VBUS power is also needed.  This might be directly connected to the USB
   host connector (as assumed here), or switched via additional logic.  Then
@@ -752,6 +754,15 @@ MAX3421E Integration
     CONFIG_USBHOST_MAX3421E=y     # MAX3421E support
     CONFIG_USBHOST_MSC=y          # USB MSC class
 
+  Using SPI1:
+
+    CONFIG_VIEWTOOL_MAX3421E_SPI1=y
+    CONFIG_VIEWTOOL_MAX3421E_FREQUENCY=20000000
+    CONFIG_VIEWTOOL_MAX3421E_RST=y
+    # CONFIG_VIEWTOOL_MAX3421E_PWR is not set
+    CONFIG_VIEWTOOL_MAX3421E_CONNMON_STACKSIZE=2048
+    CONFIG_VIEWTOOL_MAX3421E_CONNMON_PRIORITY=100
+
   Settings not listed above can be left at their default values.
 
 Toolchains

drivers/usbhost/usbhost_max3421e.c

@@ -4598,12 +4598,25 @@ static inline int max3421e_hw_initialize(FAR struct max3421e_usbhost_s *priv)
 
   max3421e_lock(priv);
 
+  /* NOTE:  Initially, the MAX3421E operations in half-duplex mode.  MISO is
+   * tristated and there is no status response to commands.  Writes are not
+   * effected:  The MISO pin continues to be high impedance and the master
+   * continues to drive MOSI.
+   *
+   * For reads, however, after the 8-bit command, the max3421e starts driving
+   * the MOSI pin.  The  master must turn off its driver to the MOSI pin to
+   * avoid contention.
+   */
+
   /* Reset the MAX3421E by toggling the CHIPRES bit in the USBCTRL register. */
 
   max3421e_putreg(priv, MAX3421E_USBHOST_USBCTL, USBHOST_USBCTL_CHIPRES);
   max3421e_putreg(priv, MAX3421E_USBHOST_USBCTL, 0);
 
-  /* Wait for the oscillator to become stable */
+  /* Wait for the oscillator to become stable
+   *
+   * REVISIT:  This can't work in half duplex mode!
+   */
 
   while ((max3421e_getreg(priv, MAX3421E_USBHOST_USBIRQ) &
                           USBHOST_USBIRQ_OSCOKIRQ) == 0)
@@ -4612,6 +4625,8 @@ static inline int max3421e_hw_initialize(FAR struct max3421e_usbhost_s *priv)
 
   /* Disable interrupts, clear pending interrupts, and reset the interrupt
    * state
+   *
+   * REVISIT: modifyreg() will not work correctly in half duplex mode.
    */
 
   max3421e_modifyreg(priv, MAX3421E_USBHOST_CPUCTL, USBHOST_CPUCTL_IE, 0);
@@ -4629,6 +4644,8 @@ static inline int max3421e_hw_initialize(FAR struct max3421e_usbhost_s *priv)
   regval |= USBHOST_PINCTL_FDUPSPI;
   max3421e_putreg(priv, MAX3421E_USBHOST_PINCTL, regval);
 
+  /* Beyond this point the SPI is operating in full duplex */
+
   /* Configure as full-speed USB host */
 
   max3421e_modifyreg(priv, MAX3421E_USBHOST_MODE,
@@ -4711,7 +4728,7 @@ max3421e_usbhost_initialize(FAR const struct max3421e_lowerhalf_s *lower)
   /* Allocate and instance of the MAX4321E state structure */
 
   alloc = (FAR struct usbhost_alloc_s *)
-    kmm_malloc(sizeof(struct usbhost_alloc_s));
+    kmm_zalloc(sizeof(struct usbhost_alloc_s));
 
   if (alloc < 0)
     {