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Add STM32 F4 DMA framework (untested)

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4142 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-12-07 14:56:28 +00:00
parent 32991cee64
commit a3c9f34ca5
8 changed files with 1332 additions and 592 deletions
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ChangeLog
+2
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@@ -2245,3 +2245,5 @@
6.13 2012-xx-xx Gregory Nutt <gnutt@nuttx.org> 6.13 2012-xx-xx Gregory Nutt <gnutt@nuttx.org>
* arch/arm/src/stm32/stm32f40xxx_dma.c: Add DMA support for the STM32 F4
family (untested on initial check-in)
arch/arm/src/stm32/chip/stm32f40xxx_dma.h
+23 -43
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@@ -270,52 +270,32 @@
/* Register Bitfield Definitions ****************************************************/ /* Register Bitfield Definitions ****************************************************/
#define DMA_STREAM_MASK 0x3f #define DMA_STREAM_MASK 0x3f
#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ #define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */
#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ #define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */
#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ #define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */
#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ #define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */
#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ #define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */
/* DMA interrupt status register */ /* DMA interrupt status register and interrupt flag clear register field defintions */
#define DMA_LISR_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt status */ #define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */
#define DMA_LISR_STREAM0_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM0_SHIFT) #define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT)
#define DMA_LISR_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt status */ #define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */
#define DMA_LISR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM1_SHIFT) #define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT)
#define DMA_LISR_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt status */ #define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */
#define DMA_LISR_STREAM2_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM2_SHIFT) #define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT)
#define DMA_LISR_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt status */ #define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */
#define DMA_LISR_STREAM3_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM3_SHIFT) #define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT)
#define DMA_HISR_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt status */ #define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */
#define DMA_HISR_STREAM4_MASK (DMA_STREAM_MASK << DMA_HISR_STREAM4_SHIFT) #define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT)
#define DMA_HISR_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt status */ #define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */
#define DMA_HISR_STREAM5_MASK (DMA_STREAM_MASK << DMA_HISR_STREAM5_SHIFT) #define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT)
#define DMA_HISR_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt status */ #define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */
#define DMA_HISR_STREAM6_MASK (DMA_STREAM_MASK << DMA_HISR_STREAM6_SHIFT) #define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT)
#define DMA_HISR_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt status */ #define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */
#define DMA_HISR_STREAM7_MASK (DMA_STREAM_MASK << DMA_HISR_STREAM7_SHIFT) #define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT)
/* DMA interrupt flag clear register */
#define DMA_LICR_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt flag clear */
#define DMA_LICR_STREAM0_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM0_SHIFT)
#define DMA_LICR_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt flag clear */
#define DMA_LICR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM1_SHIFT)
#define DMA_LICR_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt flag clear */
#define DMA_LICR_STREAM2_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM2_SHIFT)
#define DMA_LICR_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt flag clear */
#define DMA_LICR_STREAM3_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM3_SHIFT)
#define DMA_HICR_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt flag clear */
#define DMA_HICR_STREAM4_MASK (DMA_STREAM_MASK << DMA_HICR_STREAM4_SHIFT)
#define DMA_HICR_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt flag clear */
#define DMA_HICR_STREAM5_MASK (DMA_STREAM_MASK << DMA_HICR_STREAM5_SHIFT)
#define DMA_HICR_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt flag clear */
#define DMA_HICR_STREAM6_MASK (DMA_STREAM_MASK << DMA_HICR_STREAM6_SHIFT)
#define DMA_HICR_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt flag clear */
#define DMA_HICR_STREAM7_MASK (DMA_STREAM_MASK << DMA_HICR_STREAM7_SHIFT)
/* DMA stream configuration register */ /* DMA stream configuration register */
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+4 -4
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@@ -62,12 +62,12 @@
* The driver will then automatically configre PA11 as the CAN1 RX pin. * The driver will then automatically configre PA11 as the CAN1 RX pin.
*/ */
/* Additional effort is required to select specific GPIO options such as frequency, /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* open-drain/push-pull, and pull-up/down! * Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/ */
#warning "Missing logic"
/* CAN */ /* CAN */
#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11) #define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN11)
arch/arm/src/stm32/stm32_allocateheap.c
+2
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@@ -43,6 +43,8 @@
#include <debug.h> #include <debug.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/mm.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include "chip.h" #include "chip.h"
arch/arm/src/stm32/stm32_dma.c
+13 -545
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_dma.h
+16
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@@ -61,6 +61,7 @@ typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg); typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg);
#ifdef CONFIG_DEBUG_DMA #ifdef CONFIG_DEBUG_DMA
#if defined(CONFIG_STM32_STM32F10XX)
struct stm32_dmaregs_s struct stm32_dmaregs_s
{ {
uint32_t isr; uint32_t isr;
@@ -69,6 +70,21 @@ struct stm32_dmaregs_s
uint32_t cpar; uint32_t cpar;
uint32_t cmar; uint32_t cmar;
}; };
#elif defined(CONFIG_STM32_STM32F40XX)
struct stm32_dmaregs_s
{
uint32_t lisr;
uint32_t hisr;
uint32_t scr;
uint32_t sndtr;
uint32_t spar;
uint32_t sm0ar;
uint32_t sm1ar;
uint32_t sfcr;
};
#else
# error "Unknown STM32 DMA"
#endif
#endif #endif
/************************************************************************************ /************************************************************************************
arch/arm/src/stm32/stm32f10xxx_dma.c
+610
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32f40xxx_dma.c
+662
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File diff suppressed because it is too large Load Diff