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arch/arm/src/tiva/hardware: Initialize .bss sooner, Fix some PRCM register definitions

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configs/launchxl-cc1312r1:  Correct DIOs used to provide the UART0 serial console.

Status:  Board boots to NSH prompt now.  But I am not getting serial input.  Things are probably not very stable in general.
This commit is contained in:
Gregory Nutt
2019-02-12 16:35:14 -06:00
parent cf62b2288b
commit a2406c1ac8
7 changed files with 306 additions and 287 deletions
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arch/arm/src/tiva/cc13xx/cc13xx_gpio.c
+1 -15
View File
@@ -48,16 +48,12 @@
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include "up_arch.h" #include "up_arch.h"
#include "tiva_enablepwr.h"
#include "tiva_enableclks.h"
#include "tiva_gpio.h" #include "tiva_gpio.h"
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
static bool g_gpio_powered;
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@@ -67,6 +63,7 @@ static bool g_gpio_powered;
* *
* Description: * Description:
* Configure a GPIO pin based on bit-encoded description of the pin. * Configure a GPIO pin based on bit-encoded description of the pin.
* NOTE: Power and clocking provided in __start().
* *
****************************************************************************/ ****************************************************************************/
@@ -82,17 +79,6 @@ int tiva_configgpio(pinconfig_t pinconfig)
flags = spin_lock_irqsave(); flags = spin_lock_irqsave();
/* Enable power and clocking for this GPIO peripheral if this is the first
* GPIO pin configured.
*/
if (!g_gpio_powered)
{
tiva_gpio_enablepwr();
tiva_gpio_enableclk();
g_gpio_powered = true;
}
#ifdef CONFIG_TIVA_GPIO_IRQS #ifdef CONFIG_TIVA_GPIO_IRQS
/* Mask and clear any pending GPIO interrupt */ /* Mask and clear any pending GPIO interrupt */
arch/arm/src/tiva/cc13xx/cc13xx_start.c
+18 -13
View File
@@ -53,6 +53,8 @@
#include "up_arch.h" #include "up_arch.h"
#include "up_internal.h" #include "up_internal.h"
#include "tiva_enablepwr.h"
#include "tiva_enableclks.h"
#include "tiva_lowputc.h" #include "tiva_lowputc.h"
#include "tiva_userspace.h" #include "tiva_userspace.h"
#include "tiva_eeprom.h" #include "tiva_eeprom.h"
@@ -229,12 +231,6 @@ void __start(void)
cc13xx_trim_device(); cc13xx_trim_device();
/* Configure the UART so that we can get debug output as soon as possible */
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be /* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables. * certain that there are no issues with the state of global variables.
*/ */
@@ -244,7 +240,16 @@ void __start(void)
*dest++ = 0; *dest++ = 0;
} }
showprogress('B'); /* Enable power and clocking for the GPIO peripheral. */
tiva_gpio_enablepwr();
tiva_gpio_enableclk();
/* Configure the UART so that we can get debug output as soon as possible */
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
#ifdef CONFIG_BOOT_RUNFROMFLASH #ifdef CONFIG_BOOT_RUNFROMFLASH
/* Move the initialized data section from his temporary holding spot in /* Move the initialized data section from his temporary holding spot in
@@ -258,14 +263,14 @@ void __start(void)
*dest++ = *src++; *dest++ = *src++;
} }
showprogress('C'); showprogress('B');
#endif #endif
#ifdef USE_EARLYSERIALINIT #ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */ /* Perform early serial initialization */
up_earlyserialinit(); up_earlyserialinit();
showprogress('D'); showprogress('C');
#endif #endif
#ifdef CONFIG_BUILD_PROTECTED #ifdef CONFIG_BUILD_PROTECTED
@@ -276,7 +281,7 @@ void __start(void)
*/ */
tiva_userspace(); tiva_userspace();
showprogress('E'); showprogress('D');
#endif #endif
#ifdef CONFIG_TIVA_CC26X2_POWERLIB /* REVISIT: Used with CC13x2 as well. */ #ifdef CONFIG_TIVA_CC26X2_POWERLIB /* REVISIT: Used with CC13x2 as well. */
@@ -285,19 +290,19 @@ void __start(void)
*/ */
cc13xx_power_initialize(); cc13xx_power_initialize();
showprogress('F'); showprogress('E');
#endif #endif
/* Initialize on-board resources */ /* Initialize on-board resources */
tiva_boardinitialize(); tiva_boardinitialize();
showprogress('G'); showprogress('F');
#ifdef CONFIG_TIVA_EEPROM #ifdef CONFIG_TIVA_EEPROM
/*Initialize the EEPROM */ /*Initialize the EEPROM */
tiva_eeprom_initialize(); tiva_eeprom_initialize();
showprogress('H'); showprogress('G');
#endif #endif
/* Then start NuttX */ /* Then start NuttX */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
+97 -97
View File
@@ -231,11 +231,11 @@
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode * SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */ #define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT) #define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */ #define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT) #define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */ #define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT) #define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and /* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
@@ -269,50 +269,50 @@
* UART Clock Gate For Deep Sleep Mode * UART Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */ #define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT) #define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and /* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
* SSI Clock Gate For Deep Sleep Mode. * SSI Clock Gate For Deep Sleep Mode.
*/ */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */ #define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT) #define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */ #define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT) #define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and /* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
* I2S Clock Gate For Deep Sleep Mode * I2S Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */ #define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT) #define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
/* Internal */ /* Internal */
#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */ #define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
# define PRCM_CPUCLKDIV_DIV1 (0) # define PRCM_CPUCLKDIV_DIV1 (0)
# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV # define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
/* I2S Clock Control */ /* I2S Clock Control */
#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */ #define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
# define PRCM_I2SBCLKSEL_EXTERNAL (0) # define PRCM_I2SBCLKSEL_EXTERNAL (0)
# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC # define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
/* GPT Scalar */ /* GPT Scalar */
#define PRCM_GPTCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */ #define PRCM_GPTCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */
#define PRCM_GPTCLKDIV_MASK (15 << PRCM_GPTCLKDIV_SHIFT) #define PRCM_GPTCLKDIV_MASK (15 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV1 (0 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV1 (0 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV2 (1 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV2 (1 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV4 (2 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV4 (2 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)
/* I2S Clock Control */ /* I2S Clock Control */
@@ -327,153 +327,153 @@
/* MCLK Division Ratio */ /* MCLK Division Ratio */
#define PRCM_I2SMCLKDIV_MDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SMCLKDIV_MDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SMCLKDIV_MDIV_MASK (0x3ff << PRCM_I2SMCLKDIV_MDIV_SHIFT) #define PRCM_I2SMCLKDIV_MDIV_MASK (0x3ff << PRCM_I2SMCLKDIV_MDIV_SHIFT)
# define PRCM_I2SMCLKDIV_MDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SMCLKDIV_MDIV_SHIFT) # define PRCM_I2SMCLKDIV_MDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SMCLKDIV_MDIV_SHIFT)
/* BCLK Division Ratio */ /* BCLK Division Ratio */
#define PRCM_I2SBCLKDIV_BDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SBCLKDIV_BDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SBCLKDIV_BDIV_MASK (0x3ff << PRCM_I2SBCLKDIV_BDIV_SHIFT) #define PRCM_I2SBCLKDIV_BDIV_MASK (0x3ff << PRCM_I2SBCLKDIV_BDIV_SHIFT)
# define PRCM_I2SBCLKDIV_BDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SBCLKDIV_BDIV_SHIFT) # define PRCM_I2SBCLKDIV_BDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SBCLKDIV_BDIV_SHIFT)
/* WCLK Division Ratio */ /* WCLK Division Ratio */
#define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT) #define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT) # define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
/* SW Initiated Resets */ /* SW Initiated Resets */
#define PRCM_SWRESET_MCU (1 << 0) /* Bit 0: Reset MCU */ #define PRCM_SWRESET_MCU (1 << 0) /* Bit 0: Reset MCU */
/* WARM Reset Control And Status */ /* WARM Reset Control And Status */
#define PRCM_WARMRESET_WDT_STAT (1 << 0) /* Bit 0: WDT event occurred */ #define PRCM_WARMRESET_WDT_STAT (1 << 0) /* Bit 0: WDT event occurred */
#define PRCM_WARMRESET_LOCKUP_STAT (1 << 1) /* Bit 1: System CPU LOCKUP event occurred */ #define PRCM_WARMRESET_LOCKUP_STAT (1 << 1) /* Bit 1: System CPU LOCKUP event occurred */
#define PRCM_WARMRESET_WRTO_PINRESET (1 << 2) /* Bit 2: Warm reset emulates pin reset */ #define PRCM_WARMRESET_WRTO_PINRESET (1 << 2) /* Bit 2: Warm reset emulates pin reset */
/* Power Domain Control */ /* Power Domain Control */
#define PRCM_PDCTL0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */ #define PRCM_PDCTL0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */
#define PRCM_PDCTL0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */ #define PRCM_PDCTL0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */
#define PRCM_PDCTL0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */ #define PRCM_PDCTL0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */
/* RFC Power Domain Control */ /* RFC Power Domain Control */
#define PRCM_PDCTL0RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL0.RFC_ON */ #define PRCM_PDCTL0RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL0.RFC_ON */
/* SERIAL Power Domain Control */ /* SERIAL Power Domain Control */
#define PRCM_PDCTL0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDCTL0.SERIAL_ON */ #define PRCM_PDCTL0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDCTL0.SERIAL_ON */
/* PERIPH Power Domain Control */ /* PERIPH Power Domain Control */
#define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIOPH_ON */ #define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIOPH_ON */
/* Power Domain Status */ /* Power Domain Status */
#define PRCM_PDSTAT0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */ #define PRCM_PDSTAT0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */
#define PRCM_PDSTAT0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */ #define PRCM_PDSTAT0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */
#define PRCM_PDSTAT0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */ #define PRCM_PDSTAT0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */
/* RFC Power Domain Status */ /* RFC Power Domain Status */
#define PRCM_PDSTAT0RFC_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.RFC_ON */ #define PRCM_PDSTAT0RFC_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.RFC_ON */
/* SERIAL Power Domain Status */ /* SERIAL Power Domain Status */
#define PRCM_PDSTAT0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.SERIAL_ON */ #define PRCM_PDSTAT0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.SERIAL_ON */
/* PERIPH Power Domain Status */ /* PERIPH Power Domain Status */
#define PRCM_PDSTAT0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.PERIPH_ON */ #define PRCM_PDSTAT0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.PERIPH_ON */
/* Power Domain Control */ /* Power Domain Control */
#define PRCM_PDCTL1_CPU_ON (1 << 1) /* Bit 1: Initiate power-on CPU domain */ #define PRCM_PDCTL1_CPU_ON (1 << 1) /* Bit 1: Initiate power-on CPU domain */
#define PRCM_PDCTL1_RFC_ON (1 << 2) /* Bit 2: RFC power off if PDCTL.RFC_ON */ #define PRCM_PDCTL1_RFC_ON (1 << 2) /* Bit 2: RFC power off if PDCTL.RFC_ON */
#define PRCM_PDCTL1_VIMS_MODE_SHIFT (3) /* Bits 3-4: VIMS mode */ #define PRCM_PDCTL1_VIMS_MODE_SHIFT (3) /* Bits 3-4: VIMS mode */
#define PRCM_PDCTL1_VIMS_MODE_MASK (3 << PRCM_PDCTL1_VIMS_MODE_SHIFT) #define PRCM_PDCTL1_VIMS_MODE_MASK (3 << PRCM_PDCTL1_VIMS_MODE_SHIFT)
# define PRCM_PDCTL1_VIMS_MODE_CPU (0 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When CPU domain powered */ # define PRCM_PDCTL1_VIMS_MODE_CPU (0 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When CPU domain powered */
# define PRCM_PDCTL1_VIMS_MODE_BUS (1 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When BUS domain powered */ # define PRCM_PDCTL1_VIMS_MODE_BUS (1 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When BUS domain powered */
# define PRCM_PDCTL1_VIMS_MODE_BLOCK (2 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* Block on next wakeup */ # define PRCM_PDCTL1_VIMS_MODE_BLOCK (2 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* Block on next wakeup */
/* CPU Power Domain Direct Control */ /* CPU Power Domain Direct Control */
#define PRCM_PDCTL1CPU_ON (1 << 0) /* Bit 0: Alias for PDCTL1.CPU_ON */ #define PRCM_PDCTL1CPU_ON (1 << 0) /* Bit 0: Alias for PDCTL1.CPU_ON */
/* RFC Power Domain Direct Control */ /* RFC Power Domain Direct Control */
#define PRCM_PDCTL1RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL1.RFC_ON */ #define PRCM_PDCTL1RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL1.RFC_ON */
/* VIMS Mode Direct Control */ /* VIMS Mode Direct Control */
#define PRCM_PDCTL1VIMS_ON (1 << 0) /* Bit 0: Alias for PDCTL1.VIMS_ON */ #define PRCM_PDCTL1VIMS_ON (1 << 0) /* Bit 0: Alias for PDCTL1.VIMS_ON */
/* Power Manager Status */ /* Power Manager Status */
#define PRCM_PDSTAT1_CPU_ON (1 << 1) /* Bit 1: CPU domain is accessible */ #define PRCM_PDSTAT1_CPU_ON (1 << 1) /* Bit 1: CPU domain is accessible */
#define PRCM_PDSTAT1_RFC_ON (1 << 2) /* Bit 2: RFC domain is accessible */ #define PRCM_PDSTAT1_RFC_ON (1 << 2) /* Bit 2: RFC domain is accessible */
#define PRCM_PDSTAT1_VIMS_ON (1 << 3) /* Bit 3: VIMS domain is accessible */ #define PRCM_PDSTAT1_VIMS_ON (1 << 3) /* Bit 3: VIMS domain is accessible */
#define PRCM_PDSTAT1_BUS_ON (1 << 4) /* Bit 4: BUS domain is accessible */ #define PRCM_PDSTAT1_BUS_ON (1 << 4) /* Bit 4: BUS domain is accessible */
/* BUS Power Domain Direct Read Status */ /* BUS Power Domain Direct Read Status */
#define PRCM_PDSTAT1BUS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.BUS_ON */ #define PRCM_PDSTAT1BUS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.BUS_ON */
/* RFC Power Domain Direct Read Status */ /* RFC Power Domain Direct Read Status */
#define PRCM_PDSTAT1RFC_ON (1 << 0) /* Bit 0: Alias for PSTAT1.RFC_ON */ #define PRCM_PDSTAT1RFC_ON (1 << 0) /* Bit 0: Alias for PSTAT1.RFC_ON */
/* CPU Power Domain Direct Read Status */ /* CPU Power Domain Direct Read Status */
#define PRCM_PDSTAT1CPU_ON (1 << 0) /* Bit 0: Alias for PSTAT1.CPU_ON */ #define PRCM_PDSTAT1CPU_ON (1 << 0) /* Bit 0: Alias for PSTAT1.CPU_ON */
/* VIMS Mode Direct Read Status */ /* VIMS Mode Direct Read Status */
#define PRCM_PDSTAT1VIMS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.VIMS_ON */ #define PRCM_PDSTAT1VIMS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.VIMS_ON */
/* Control To RFC (32-bits RFCBITS) */ /* Control To RFC (32-bits RFCBITS) */
/* Selected RFC Mode */ /* Selected RFC Mode */
#define PRCM_RFCMODESEL_CURR_SHIFT (0) /* Bits 0-2: Selects RFC command set */ #define PRCM_RFCMODESEL_CURR_SHIFT (0) /* Bits 0-2: Selects RFC command set */
#define PRCM_RFCMODESEL_CURR_MASK (7 << PRCM_RFCMODESEL_CURR_SHIFT) #define PRCM_RFCMODESEL_CURR_MASK (7 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE0 (0 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE0 (0 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE1 (1 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE1 (1 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE2 (2 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE2 (2 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE3 (3 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE3 (3 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE4 (4 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE4 (4 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE5 (5 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE5 (5 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE6 (6 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE6 (6 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE7 (7 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE7 (7 << PRCM_RFCMODESEL_CURR_SHIFT)
/* Allowed RFC Modes */ /* Allowed RFC Modes */
#define PRCM_RFCMODEHWOPT_CURR_SHIFT (0) /* Bits 0-2: Permitted RFC modes */ #define PRCM_RFCMODEHWOPT_CURR_SHIFT (0) /* Bits 0-2: Permitted RFC modes */
#define PRCM_RFCMODEHWOPT_CURR_MASK (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT) #define PRCM_RFCMODEHWOPT_CURR_MASK (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE0 (0 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE0 (0 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE1 (1 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE1 (1 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE2 (2 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE2 (2 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE3 (3 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE3 (3 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE4 (4 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE4 (4 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE5 (5 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE5 (5 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE6 (6 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE6 (6 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE7 (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE7 (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
/* Power Profiler Register */ /* Power Profiler Register */
#define PRCM_PWRPROFSTAT_VALUE_SHIFT (0) /* Bits 0-7: Timestamp value */ #define PRCM_PWRPROFSTAT_VALUE_SHIFT (0) /* Bits 0-7: Timestamp value */
#define PRCM_PWRPROFSTAT_VALUE_MASK (0xff << PRCM_PWRPROFSTAT_VALUE_SHIFT) #define PRCM_PWRPROFSTAT_VALUE_MASK (0xff << PRCM_PWRPROFSTAT_VALUE_SHIFT)
/* Memory Retention Control */ /* Memory Retention Control */
#define PRCM_RAMRETEN_VIMS_SHIFT (0) /* Bits 0-1: VIMS memory retention enabled */ #define PRCM_RAMRETEN_VIMS_SHIFT (0) /* Bits 0-1: VIMS memory retention enabled */
#define PRCM_RAMRETEN_VIMS_MASK (3 << PRCM_RAMRETEN_VIMS_SHIFT) #define PRCM_RAMRETEN_VIMS_MASK (3 << PRCM_RAMRETEN_VIMS_SHIFT)
# define PRCM_RAMRETEN_VIMS_TRAM (1 << PRCM_RAMRETEN_VIMS_SHIFT) # define PRCM_RAMRETEN_VIMS_TRAM (1 << PRCM_RAMRETEN_VIMS_SHIFT)
# define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT) # define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT)
#define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */ #define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */
/**************************************************************************************************** /****************************************************************************************************
* Public Types * Public Types
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_prcm.h
+151 -151
View File
@@ -256,13 +256,13 @@
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode * SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */ #define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT) #define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */ #define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT) #define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (1 << 2) /* Bit 2: Enable PKA clock */ #define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKG_PKA_CLKEN (1 << PRCM_SECDMACLKG_PKA_CLKEN_SHIFT) #define PRCM_SECDMACLKG_PKA_CLKEN (1 << PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */ #define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT) #define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes (only) */ /* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes (only) */
@@ -282,7 +282,7 @@
/* GPIO Clock Gate For Run And All Modes (only) */ /* GPIO Clock Gate For Run And All Modes (only) */
#define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8 Force clock for all modes */ #define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8: Force clock for all modes */
/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and /* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
* GPT Clock Gate For Deep Sleep Mode. * GPT Clock Gate For Deep Sleep Mode.
@@ -319,9 +319,9 @@
* UART Clock Gate For Deep Sleep Mode * UART Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */ #define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT) #define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
#define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1 << 1) /* Bit 1: UART1 Enable clock */ #define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1) /* Bit 1: UART1 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART1 (1 << PRCM_UARTCLKGDS_CLKEN_UART1_SHIFT) #define PRCM_UARTCLKG_CLKEN_UART1 (1 << PRCM_UARTCLKGDS_CLKEN_UART1_SHIFT)
/* UART Clock Gate For Run And All Modes (only) */ /* UART Clock Gate For Run And All Modes (only) */
@@ -333,86 +333,86 @@
* SSI Clock Gate For Deep Sleep Mode * SSI Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */ #define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT) #define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */ #define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT) #define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* SSI Clock Gate For Run And All Modes (only) */ /* SSI Clock Gate For Run And All Modes (only) */
#define PRCM_SSICLKGR_AMCLKEN_SSI0 (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */ #define PRCM_SSICLKGR_AMCLKEN_SSI0 (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
#define PRCM_SSICLKGR_AMCLKEN_SSI1 (1 << 9) /* Bit 9: SSI1 Force clock on for all modes */ #define PRCM_SSICLKGR_AMCLKEN_SSI1 (1 << 9) /* Bit 9: SSI1 Force clock on for all modes */
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and /* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
* I2S Clock Gate For Deep Sleep Mode * I2S Clock Gate For Deep Sleep Mode
*/ */
#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */ #define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT) #define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
/* I2S Clock Gate For Run And All Modes (only) */ /* I2S Clock Gate For Run And All Modes (only) */
#define PRCM_I2SCLKGR_AMCLKEN (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */ #define PRCM_I2SCLKGR_AMCLKEN (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
/* Internal */ /* Internal */
#define PRCM_SYSBUSCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */ #define PRCM_SYSBUSCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
# define PRCM_SYSBUSCLKDIV_DIV1 (0) # define PRCM_SYSBUSCLKDIV_DIV1 (0)
# define PRCM_SYSBUSCLKDIV_DIV2 PRCM_SYSBUSCLKDIV_DIV # define PRCM_SYSBUSCLKDIV_DIV2 PRCM_SYSBUSCLKDIV_DIV
/* Internal */ /* Internal */
#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */ #define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
# define PRCM_CPUCLKDIV_DIV1 (0) # define PRCM_CPUCLKDIV_DIV1 (0)
# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV # define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
/* Internal */ /* Internal */
#define PRCM_PERBUSCPUCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */ #define PRCM_PERBUSCPUCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */
#define PRCM_PERBUSCPUCLKDIV_MASK (15 << PRCM_PERBUSCPUCLKDIV_SHIFT) #define PRCM_PERBUSCPUCLKDIV_MASK (15 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV1 (0 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV1 (0 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV2 (1 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV2 (1 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV4 (2 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV4 (2 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV8 (3 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV8 (3 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV16 (4 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV16 (4 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV32 (5 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV32 (5 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV65 (6 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV65 (6 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV128 (7 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV128 (7 << PRCM_PERBUSCPUCLKDIV_SHIFT)
# define PRCM_PERBUSCPUCLKDIV_DIV256 (8 << PRCM_PERBUSCPUCLKDIV_SHIFT) # define PRCM_PERBUSCPUCLKDIV_DIV256 (8 << PRCM_PERBUSCPUCLKDIV_SHIFT)
/* Internal */ /* Internal */
#define PRCM_PERDMACLKDIV_SHIFT (0) /* Bit 0-3: Ratio */ #define PRCM_PERDMACLKDIV_SHIFT (0) /* Bit 0-3: Ratio */
#define PRCM_PERDMACLKDIV_MASK (15 << PRCM_PERDMACLKDIV_SHIFT) #define PRCM_PERDMACLKDIV_MASK (15 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV1 (0 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV1 (0 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV2 (1 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV2 (1 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV4 (2 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV4 (2 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV8 (3 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV8 (3 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV16 (4 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV16 (4 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV32 (5 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV32 (5 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV65 (6 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV65 (6 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV128 (7 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV128 (7 << PRCM_PERDMACLKDIV_SHIFT)
# define PRCM_PERDMACLKDIV_DIV256 (8 << PRCM_PERDMACLKDIV_SHIFT) # define PRCM_PERDMACLKDIV_DIV256 (8 << PRCM_PERDMACLKDIV_SHIFT)
/* I2S Clock Control */ /* I2S Clock Control */
#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */ #define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
# define PRCM_I2SBCLKSEL_EXTERNAL (0) # define PRCM_I2SBCLKSEL_EXTERNAL (0)
# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC # define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
/* GPT Scalar */ /* GPT Scalar */
#define PRCM_GPTCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */ #define PRCM_GPTCLKDIV_SHIFT (0) /* Bit 0-3: Ratio */
#define PRCM_GPTCLKDIV_MASK (15 << PRCM_GPTCLKDIV_SHIFT) #define PRCM_GPTCLKDIV_MASK (15 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV1 (0 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV1 (0 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV2 (1 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV2 (1 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV4 (2 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV4 (2 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT) # define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)
/* I2S Clock Control */ /* I2S Clock Control */
@@ -427,199 +427,199 @@
/* MCLK Division Ratio */ /* MCLK Division Ratio */
#define PRCM_I2SMCLKDIV_MDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SMCLKDIV_MDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SMCLKDIV_MDIV_MASK (0x3ff << PRCM_I2SMCLKDIV_MDIV_SHIFT) #define PRCM_I2SMCLKDIV_MDIV_MASK (0x3ff << PRCM_I2SMCLKDIV_MDIV_SHIFT)
# define PRCM_I2SMCLKDIV_MDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SMCLKDIV_MDIV_SHIFT) # define PRCM_I2SMCLKDIV_MDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SMCLKDIV_MDIV_SHIFT)
/* BCLK Division Ratio */ /* BCLK Division Ratio */
#define PRCM_I2SBCLKDIV_BDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SBCLKDIV_BDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SBCLKDIV_BDIV_MASK (0x3ff << PRCM_I2SBCLKDIV_BDIV_SHIFT) #define PRCM_I2SBCLKDIV_BDIV_MASK (0x3ff << PRCM_I2SBCLKDIV_BDIV_SHIFT)
# define PRCM_I2SBCLKDIV_BDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SBCLKDIV_BDIV_SHIFT) # define PRCM_I2SBCLKDIV_BDIV(n) (((uint32_t)(n) & 0x3ff) << PRCM_I2SBCLKDIV_BDIV_SHIFT)
/* WCLK Division Ratio */ /* WCLK Division Ratio */
#define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */ #define PRCM_I2SWCLKDIV_WDIV_SHIFT (0) /* Bits 0-9: MCLK divider */
#define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT) #define PRCM_I2SWCLKDIV_WDIV_MASK (0x3ff << PRCM_I2SWCLKDIV_WDIV_SHIFT)
# define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT) # define PRCM_I2SWCLKDIV_WDIV(n) ((uint32_t)(n) << PRCM_I2SWCLKDIV_WDIV_SHIFT)
/* RESET For SEC (PKA And TRNG And CRYPTO) And UDMA */ /* RESET For SEC (PKA And TRNG And CRYPTO) And UDMA */
#define PRCM_RESETSECDMA_CRYPTO (1 << 0) /* Bit 0: Reset Crypto */ #define PRCM_RESETSECDMA_CRYPTO (1 << 0) /* Bit 0: Reset Crypto */
#define PRCM_RESETSECDMA_TRNG (1 << 1) /* Bit 1: Reset TRNG */ #define PRCM_RESETSECDMA_TRNG (1 << 1) /* Bit 1: Reset TRNG */
#define PRCM_RESETSECDMA_PKA (1 << 2) /* Bit 2: Reset PKA */ #define PRCM_RESETSECDMA_PKA (1 << 2) /* Bit 2: Reset PKA */
#define PRCM_RESETSECDMA_DMA (1 << 8) /* Bit 8: Reset DMA */ #define PRCM_RESETSECDMA_DMA (1 << 8) /* Bit 8: Reset DMA */
/* RESET For GPIO IPs */ /* RESET For GPIO IPs */
#define PRCM_RESETGPIO_GPIO (1 << 0) /* Bit 0: Reset GPIO */ #define PRCM_RESETGPIO_GPIO (1 << 0) /* Bit 0: Reset GPIO */
/* RESET For GPT IPs */ /* RESET For GPT IPs */
#define PRCM_RESETGPT_GPT (1 << 0) /* Bit 0: Reset GPT */ #define PRCM_RESETGPT_GPT (1 << 0) /* Bit 0: Reset GPT */
/* RESET For I2C IPs */ /* RESET For I2C IPs */
#define PRCM_RESETI2C_I2C (1 << 0) /* Bit 0: Reset I2C */ #define PRCM_RESETI2C_I2C (1 << 0) /* Bit 0: Reset I2C */
/* RESET For UART IPs */ /* RESET For UART IPs */
#define PRCM_RESETUART_UART0 (1 << 0) /* Bit 0: Reset UART0 */ #define PRCM_RESETUART_UART0 (1 << 0) /* Bit 0: Reset UART0 */
#define PRCM_RESETUART_UART1 (1 << 1) /* Bit 1: Reset UART1 */ #define PRCM_RESETUART_UART1 (1 << 1) /* Bit 1: Reset UART1 */
/* RESET For SSI IPs */ /* RESET For SSI IPs */
#define PRCM_RESETSSI_SSI0 (1 << 0) /* Bit 0: Reset SSI0 */ #define PRCM_RESETSSI_SSI0 (1 << 0) /* Bit 0: Reset SSI0 */
#define PRCM_RESETSSI_SSI1 (1 << 1) /* Bit 1: Reset SSI1 */ #define PRCM_RESETSSI_SSI1 (1 << 1) /* Bit 1: Reset SSI1 */
/* RESET For I2S IP */ /* RESET For I2S IP */
#define PRCM_RESETI2S_I2S (1 << 0) /* Bit 0: Reset I2S */ #define PRCM_RESETI2S_I2S (1 << 0) /* Bit 0: Reset I2S */
/* Power Domain Control */ /* Power Domain Control */
#define PRCM_PDCTL0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */ #define PRCM_PDCTL0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */
#define PRCM_PDCTL0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */ #define PRCM_PDCTL0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */
#define PRCM_PDCTL0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */ #define PRCM_PDCTL0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */
/* RFC Power Domain Control */ /* RFC Power Domain Control */
#define PRCM_PDCTL0RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL0.RFC_ON */ #define PRCM_PDCTL0RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL0.RFC_ON */
/* SERIAL Power Domain Control */ /* SERIAL Power Domain Control */
#define PRCM_PDCTL0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDCTL0.SERIAL_ON */ #define PRCM_PDCTL0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDCTL0.SERIAL_ON */
/* PERIPH Power Domain Control */ /* PERIPH Power Domain Control */
#define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIOPH_ON */ #define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIPH_ON */
/* Power Domain Status */ /* Power Domain Status */
#define PRCM_PDSTAT0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */ #define PRCM_PDSTAT0_RFC_ON (1 << 0) /* Bit 0: RFC domain powered on */
#define PRCM_PDSTAT0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */ #define PRCM_PDSTAT0_SERIAL_ON (1 << 1) /* Bit 1: SERIAL domain powered up */
#define PRCM_PDSTAT0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */ #define PRCM_PDSTAT0_PERIPH_ON (1 << 2) /* Bit 2: PERIPH domain powered up */
/* RFC Power Domain Status */ /* RFC Power Domain Status */
#define PRCM_PDSTAT0RFC_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.RFC_ON */ #define PRCM_PDSTAT0RFC_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.RFC_ON */
/* SERIAL Power Domain Status */ /* SERIAL Power Domain Status */
#define PRCM_PDSTAT0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.SERIAL_ON */ #define PRCM_PDSTAT0SERIAL_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.SERIAL_ON */
/* PERIPH Power Domain Status */ /* PERIPH Power Domain Status */
#define PRCM_PDSTAT0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.PERIPH_ON */ #define PRCM_PDSTAT0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDSTAT0.PERIPH_ON */
/* Power Domain Control */ /* Power Domain Control */
#define PRCM_PDCTL1_CPU_ON (1 << 1) /* Bit 1: Initiate power-on CPU domain */ #define PRCM_PDCTL1_CPU_ON (1 << 1) /* Bit 1: Initiate power-on CPU domain */
#define PRCM_PDCTL1_RFC_ON (1 << 2) /* Bit 2: RFC power off if PDCTL.RFC_ON */ #define PRCM_PDCTL1_RFC_ON (1 << 2) /* Bit 2: RFC power off if PDCTL.RFC_ON */
#define PRCM_PDCTL1_VIMS_MODE_SHIFT (3) /* Bits 3-4: VIMS mode */ #define PRCM_PDCTL1_VIMS_MODE_SHIFT (3) /* Bits 3-4: VIMS mode */
#define PRCM_PDCTL1_VIMS_MODE_MASK (3 << PRCM_PDCTL1_VIMS_MODE_SHIFT) #define PRCM_PDCTL1_VIMS_MODE_MASK (3 << PRCM_PDCTL1_VIMS_MODE_SHIFT)
# define PRCM_PDCTL1_VIMS_MODE_CPU (0 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When CPU domain powered */ # define PRCM_PDCTL1_VIMS_MODE_CPU (0 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When CPU domain powered */
# define PRCM_PDCTL1_VIMS_MODE_BUS (1 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When BUS domain powered */ # define PRCM_PDCTL1_VIMS_MODE_BUS (1 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* When BUS domain powered */
# define PRCM_PDCTL1_VIMS_MODE_BLOCK (2 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* Block on next wakeup */ # define PRCM_PDCTL1_VIMS_MODE_BLOCK (2 << PRCM_PDCTL1_VIMS_MODE_SHIFT) /* Block on next wakeup */
/* CPU Power Domain Direct Control */ /* CPU Power Domain Direct Control */
#define PRCM_PDCTL1CPU_ON (1 << 0) /* Bit 0: Alias for PDCTL1.CPU_ON */ #define PRCM_PDCTL1CPU_ON (1 << 0) /* Bit 0: Alias for PDCTL1.CPU_ON */
/* RFC Power Domain Direct Control */ /* RFC Power Domain Direct Control */
#define PRCM_PDCTL1RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL1.RFC_ON */ #define PRCM_PDCTL1RFC_ON (1 << 0) /* Bit 0: Alias for PDCTL1.RFC_ON */
/* VIMS Mode Direct Control */ /* VIMS Mode Direct Control */
#define PRCM_PDCTL1VIMS_ON (1 << 0) /* Bit 0: Alias for PDCTL1.VIMS_ON */ #define PRCM_PDCTL1VIMS_ON (1 << 0) /* Bit 0: Alias for PDCTL1.VIMS_ON */
/* Power Manager Status */ /* Power Manager Status */
#define PRCM_PDSTAT1_CPU_ON (1 << 1) /* Bit 1: CPU domain is accessible */ #define PRCM_PDSTAT1_CPU_ON (1 << 1) /* Bit 1: CPU domain is accessible */
#define PRCM_PDSTAT1_RFC_ON (1 << 2) /* Bit 2: RFC domain is accessible */ #define PRCM_PDSTAT1_RFC_ON (1 << 2) /* Bit 2: RFC domain is accessible */
#define PRCM_PDSTAT1_VIMS_ON (1 << 3) /* Bit 3: VIMS domain is accessible */ #define PRCM_PDSTAT1_VIMS_ON (1 << 3) /* Bit 3: VIMS domain is accessible */
#define PRCM_PDSTAT1_BUS_ON (1 << 4) /* Bit 4: BUS domain is accessible */ #define PRCM_PDSTAT1_BUS_ON (1 << 4) /* Bit 4: BUS domain is accessible */
/* BUS Power Domain Direct Read Status */ /* BUS Power Domain Direct Read Status */
#define PRCM_PDSTAT1BUS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.BUS_ON */ #define PRCM_PDSTAT1BUS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.BUS_ON */
/* RFC Power Domain Direct Read Status */ /* RFC Power Domain Direct Read Status */
#define PRCM_PDSTAT1RFC_ON (1 << 0) /* Bit 0: Alias for PSTAT1.RFC_ON */ #define PRCM_PDSTAT1RFC_ON (1 << 0) /* Bit 0: Alias for PSTAT1.RFC_ON */
/* CPU Power Domain Direct Read Status */ /* CPU Power Domain Direct Read Status */
#define PRCM_PDSTAT1CPU_ON (1 << 0) /* Bit 0: Alias for PSTAT1.CPU_ON */ #define PRCM_PDSTAT1CPU_ON (1 << 0) /* Bit 0: Alias for PSTAT1.CPU_ON */
/* VIMS Mode Direct Read Status */ /* VIMS Mode Direct Read Status */
#define PRCM_PDSTAT1VIMS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.VIMS_ON */ #define PRCM_PDSTAT1VIMS_ON (1 << 0) /* Bit 0: Alias for PSTAT1.VIMS_ON */
/* Control To RFC (32-bits RFCBITS) */ /* Control To RFC (32-bits RFCBITS) */
/* Selected RFC Mode */ /* Selected RFC Mode */
#define PRCM_RFCMODESEL_CURR_SHIFT (0) /* Bits 0-2: Selects RFC command set */ #define PRCM_RFCMODESEL_CURR_SHIFT (0) /* Bits 0-2: Selects RFC command set */
#define PRCM_RFCMODESEL_CURR_MASK (7 << PRCM_RFCMODESEL_CURR_SHIFT) #define PRCM_RFCMODESEL_CURR_MASK (7 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE0 (0 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE0 (0 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE1 (1 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE1 (1 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE2 (2 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE2 (2 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE3 (3 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE3 (3 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE4 (4 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE4 (4 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE5 (5 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE5 (5 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE6 (6 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE6 (6 << PRCM_RFCMODESEL_CURR_SHIFT)
# define PRCM_RFCMODESEL_CURR_MODE7 (7 << PRCM_RFCMODESEL_CURR_SHIFT) # define PRCM_RFCMODESEL_CURR_MODE7 (7 << PRCM_RFCMODESEL_CURR_SHIFT)
/* Allowed RFC Modes */ /* Allowed RFC Modes */
#define PRCM_RFCMODEHWOPT_CURR_SHIFT (0) /* Bits 0-2: Permitted RFC modes */ #define PRCM_RFCMODEHWOPT_CURR_SHIFT (0) /* Bits 0-2: Permitted RFC modes */
#define PRCM_RFCMODEHWOPT_CURR_MASK (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT) #define PRCM_RFCMODEHWOPT_CURR_MASK (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE0 (0 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE0 (0 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE1 (1 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE1 (1 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE2 (2 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE2 (2 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE3 (3 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE3 (3 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE4 (4 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE4 (4 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE5 (5 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE5 (5 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE6 (6 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE6 (6 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
# define PRCM_RFCMODEHWOPT_CURR_MODE7 (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT) # define PRCM_RFCMODEHWOPT_CURR_MODE7 (7 << PRCM_RFCMODEHWOPT_CURR_SHIFT)
/* Power Profiler Register */ /* Power Profiler Register */
#define PRCM_PWRPROFSTAT_VALUE_SHIFT (0) /* Bits 0-7: Timestamp value */ #define PRCM_PWRPROFSTAT_VALUE_SHIFT (0) /* Bits 0-7: Timestamp value */
#define PRCM_PWRPROFSTAT_VALUE_MASK (0xff << PRCM_PWRPROFSTAT_VALUE_SHIFT) #define PRCM_PWRPROFSTAT_VALUE_MASK (0xff << PRCM_PWRPROFSTAT_VALUE_SHIFT)
/* MCU SRAM configuration */ /* MCU SRAM configuration */
#define PRCM_MCUSRAMCFG_PCHL (1 << 0) /* Bit 0: 1st half bitline precharge when BM=1 */ #define PRCM_MCUSRAMCFG_PCHL (1 << 0) /* Bit 0: 1st half bitline precharge when BM=1 */
#define PRCM_MCUSRAMCFG_PCHF (1 << 1) /* Bit 1: 2nd half bitline precharge when BM=1 */ #define PRCM_MCUSRAMCFG_PCHF (1 << 1) /* Bit 1: 2nd half bitline precharge when BM=1 */
#define PRCM_MCUSRAMCFG_BM (1 << 2) /* Bit 2: Burst mode enable */ #define PRCM_MCUSRAMCFG_BM (1 << 2) /* Bit 2: Burst mode enable */
#define PRCM_MCUSRAMCFG_PGS (1 << 3) /* Bit 3: Select word MSB in page mode */ #define PRCM_MCUSRAMCFG_PGS (1 << 3) /* Bit 3: Select word MSB in page mode */
#define PRCM_MCUSRAMCFG_PAGE (1 << 4) /* Bit 4: Page mode enable */ #define PRCM_MCUSRAMCFG_PAGE (1 << 4) /* Bit 4: Page mode enable */
#define PRCM_MCUSRAMCFG_BMOFF (1 << 5) /* Bit 5: Burst mode disable */ #define PRCM_MCUSRAMCFG_BMOFF (1 << 5) /* Bit 5: Burst mode disable */
/* Memory Retention Control */ /* Memory Retention Control */
#define PRCM_RAMRETEN_VIMS_SHIFT (0) /* Bits 0-1: VIMS memory retention enabled */ #define PRCM_RAMRETEN_VIMS_SHIFT (0) /* Bits 0-1: VIMS memory retention enabled */
#define PRCM_RAMRETEN_VIMS_MASK (3 << PRCM_RAMRETEN_VIMS_SHIFT) #define PRCM_RAMRETEN_VIMS_MASK (3 << PRCM_RAMRETEN_VIMS_SHIFT)
# define PRCM_RAMRETEN_VIMS_TRAM (1 << PRCM_RAMRETEN_VIMS_SHIFT) # define PRCM_RAMRETEN_VIMS_TRAM (1 << PRCM_RAMRETEN_VIMS_SHIFT)
# define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT) # define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT)
#define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */ #define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */
#define PRCM_RAMRETEN_RFCULL (1 << 3) /* Bit 3: RFC ULL SRAM retention enabled */ #define PRCM_RAMRETEN_RFCULL (1 << 3) /* Bit 3: RFC ULL SRAM retention enabled */
/* Oscillator Interrupt Mask, Oscillator Raw Interrupt Status, and /* Oscillator Interrupt Mask, Oscillator Raw Interrupt Status, and
* Oscillator Raw Interrupt Clear * Oscillator Raw Interrupt Clear
*/ */
#define PRCM_OSCINT_RCOSCHF (1 << 0) /* Bit 0: RCOSCHF interrupt */ #define PRCM_OSCINT_RCOSCHF (1 << 0) /* Bit 0: RCOSCHF interrupt */
#define PRCM_OSCINT_XOSCHF (1 << 1) /* Bit 1: XOSCHF interrupt */ #define PRCM_OSCINT_XOSCHF (1 << 1) /* Bit 1: XOSCHF interrupt */
#define PRCM_OSCINT_RCOSCLF (1 << 2) /* Bit 2: RCOSCLF interrupt */ #define PRCM_OSCINT_RCOSCLF (1 << 2) /* Bit 2: RCOSCLF interrupt */
#define PRCM_OSCINT_RCOSCDLF (1 << 3) /* Bit 3: RCOSCDLF interrupt */ #define PRCM_OSCINT_RCOSCDLF (1 << 3) /* Bit 3: RCOSCDLF interrupt */
#define PRCM_OSCINT_XOSCLF (1 << 4) /* Bit 4: XOSCLF interrupt */ #define PRCM_OSCINT_XOSCLF (1 << 4) /* Bit 4: XOSCLF interrupt */
#define PRCM_OSCINT_XOSCDLF (1 << 5) /* Bit 5: XOSCDLF interrupt */ #define PRCM_OSCINT_XOSCDLF (1 << 5) /* Bit 5: XOSCDLF interrupt */
#define PRCM_OSCINT_LFSRCDONE (1 << 6) /* Bit 6: LFSRCDONE interrupt */ #define PRCM_OSCINT_LFSRCDONE (1 << 6) /* Bit 6: LFSRCDONE interrupt */
#define PRCM_OSCINT_HFSRCPEND (1 << 7) /* Bit 7: HFSRCPEND interrupt */ #define PRCM_OSCINT_HFSRCPEND (1 << 7) /* Bit 7: HFSRCPEND interrupt */
/**************************************************************************************************** /****************************************************************************************************
* Public Types * Public Types
configs/launchxl-cc1312r1/README.txt
+35 -7
View File
@@ -21,21 +21,30 @@ Status
development. Serious board development will occur later. Board development. Serious board development will occur later. Board
support is missing LED and button support. support is missing LED and button support.
2019-02-10: Figured out how to connect J-Link and began debug. 2019-02-10: Figured out how to connect J-Link and began debug.
2019-02-12: Now hard-faults in tiva_lowsetup() here: 2019-02-12: A little progress. I do make it all the way into NSH:
352 ctl = getreg32(TIVA_CONSOLE_BASE + TIVA_UART_CTL_OFFSET); ABCF
nx_start: Entry
uart_register: Registering /dev/console
uart_register: Registering /dev/ttyS0
work_hpstart: Starting high-priority kernel worker thread(s)
up_release_pending: From TCB=20000c00
nx_start_application: Starting init thread
Most likely UART0 clocking is not being enabled correctly. NuttShell (NSH) NuttX-7.28
nsh> nx_start: CPU0: Beginning Idle Loop
But things are not very stable and I do not get any console input.
Serial Console Serial Console
============== ==============
The on-board XDS110 Debugger provide a USB virtual serial console using The on-board XDS110 Debugger provide a USB virtual serial console using
UART0 (PA0/U0RX and PA1/U0TX). UART0 (DIO2_RXD and DIO3_TXD).
A J-Link debugger is used (see below), then the RXD/TXD jumper pins can A J-Link debugger is used (see below), then the RXD/TXD jumper pins can
be used to support a serial console through appropriate TTL level adapater be used to support a serial console through these same pins via an
(RS-232 or USB serial). appropriate TTL level adapater (RS-232 or USB serial).
LEDs and Buttons LEDs and Buttons
================ ================
@@ -133,5 +142,24 @@ Using J-Link
NOTE: When connecting the J-Link GDB server, the interface must be set to NOTE: When connecting the J-Link GDB server, the interface must be set to
JTAG, not SWD as you might expect. JTAG, not SWD as you might expect.
The RXD/TXD pins. PA0/U0RX and PA1/U0TX, can then support a Serial console The RXD/TXD pins, DIO2_RXD and DIO3_TXD, can then support a Serial console
using the appropriate TTL adapter (TTL to RS-232 or TTL to USB serial). using the appropriate TTL adapter (TTL to RS-232 or TTL to USB serial).
One odd behavior that I have found is after a reset from the J-Link, the
SP and PC registers are not automatically set and I had to manually set
them as shown below:
(gdb) target remote localhost:2331
(gdb) mon reset
(gdb) mon halt
(gdb) file nuttx
(gdb) mon memu32 0
Reading from address 0x00000000 (Data = 0x20001950)
(gdb) mon memu32 4
Reading from address 0x00000004 (Data = 0x00000139)
(gdb) mon reg sp 0x20001950
Writing register (SP = 0x20001950)
(gdb) mon reg pc 0x00000139
Writing register (PC = 0x00000139)
(gdb) n
232 cc13xx_trim_device();
configs/launchxl-cc1312r1/include/board.h
+1 -1
View File
@@ -126,7 +126,7 @@
/* UART0: /* UART0:
* *
* The on-board XDS110 Debugger provide a USB virtual serial console using * The on-board XDS110 Debugger provide a USB virtual serial console using
* UART0 (PA0/U0RX and PA1/U0TX). * UART0 (DIO2_RXD and DIO3_TXD).
*/ */
# define GPIO_UART0_RX &g_gpio_uart0_rx # define GPIO_UART0_RX &g_gpio_uart0_rx
configs/launchxl-cc1312r1/src/cc1312_pinconfig.c
+3 -3
View File
@@ -51,18 +51,18 @@
/* UART0: /* UART0:
* *
* The on-board XDS110 Debugger provide a USB virtual serial console using * The on-board XDS110 Debugger provide a USB virtual serial console using
* UART0 (PA0/U0RX and PA1/U0TX). * UART0 (DIO2_RXD and DIO3_TXD).
*/ */
const struct cc13xx_pinconfig_s g_gpio_uart0_rx = const struct cc13xx_pinconfig_s g_gpio_uart0_rx =
{ {
.gpio = GPIO_DIO(0), .gpio = GPIO_DIO(2),
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT
}; };
const struct cc13xx_pinconfig_s g_gpio_uart0_tx = const struct cc13xx_pinconfig_s g_gpio_uart0_tx =
{ {
.gpio = GPIO_DIO(1), .gpio = GPIO_DIO(3),
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT .ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT
}; };
#endif #endif