Last Updated: March 28, 2016
+Last Updated: May 12, 2016
@@ -154,9 +154,8 @@ 4.7.1up_testset()up_cpu_index()up_cpu_start()up_cpu_initialize()up_cpu_pause()up_cpu_resume()
+ 4.7.4 up_cpu_pause()up_cpu_resume()
4.8 APIs Exported by NuttX to Architecture-Specific Logic
up_cpu_initialize()Function Prototype:
-
-#include <nuttx/arch.h> -#ifdef CONFIG_SMP -int up_cpu_initialize(void); -#endif -- -
Description:
-
- After the CPU has been started (via up_cpu_start()) the system will call back into the architecture-specific code with this function on the thread of execution of the newly started CPU.
- This gives the architecture-specific a chance to perform ny initial, CPU-specific initialize on that thread.
-
Input Parameters:
-Returned Value:
-
- Zero (OK) is returned on success; a negated errno value on failure.
-
up_cpu_pause()up_cpu_pause()Function Prototype:
#include <nuttx/arch.h> @@ -3781,7 +3753,7 @@ int up_cpu_pause(int cpu); -4.7.6
+up_cpu_resume()4.7.5
up_cpu_resume()Function Prototype:
#include <nuttx/arch.h>
diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c
index c999ea6ef57..b7ceee33f74 100644
--- a/arch/arm/src/a1x/a1x_boot.c
+++ b/arch/arm/src/a1x/a1x_boot.c
@@ -289,7 +289,7 @@ static void a1x_copyvectorblock(void)
****************************************************************************/
/****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
*
* Description:
* Complete boot operations started in arm_head.S
@@ -305,7 +305,7 @@ static void a1x_copyvectorblock(void)
*
****************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
#ifndef CONFIG_ARCH_ROMPGTABLE
/* __start provided the basic MMU mappings for SRAM. Now provide mappings
diff --git a/arch/arm/src/arm/up_head.S b/arch/arm/src/arm/up_head.S
index 296c30656fd..53f94a2e0fa 100644
--- a/arch/arm/src/arm/up_head.S
+++ b/arch/arm/src/arm/up_head.S
@@ -609,7 +609,7 @@ __start:
/* Perform early C-level, platform-specific initialization */
- bl up_boot
+ bl arm_boot
#ifdef CONFIG_STACK_COLORATION
/* Write a known value to the IDLE thread stack to support stack
diff --git a/arch/arm/src/arm/up_pginitialize.c b/arch/arm/src/arm/up_pginitialize.c
index 5470f73e354..25cb917809a 100644
--- a/arch/arm/src/arm/up_pginitialize.c
+++ b/arch/arm/src/arm/up_pginitialize.c
@@ -88,7 +88,7 @@ void up_pginitialize(void)
{
/* None needed at present. This file is just retained in case the need
* arises in the future. Nothing calls up_pginitialize() now. If needed,
- * if should be called early in up_boot.c to assure that all paging is
+ * if should be called early in arm_boot.c to assure that all paging is
* ready.
*/
}
diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S
new file mode 100644
index 00000000000..487fee0a46b
--- /dev/null
+++ b/arch/arm/src/armv7-a/arm_cpuhead.S
@@ -0,0 +1,492 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuhead.S
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include "arm.h"
+#include "cp15.h"
+#include "sctlr.h"
+#include "mmu.h"
+#include "smp.h"
+
+#include "chip.h"
+#include "up_internal.h"
+
+ .file "arm_cpuhead.S"
+
+/**********************************************************************************
+ * Configuration
+ **********************************************************************************/
+
+/* Hard-coded options */
+
+#undef CPU_ALIGNMENT_TRAP
+#undef CPU_CACHE_ROUND_ROBIN
+#undef CPU_DCACHE_DISABLE
+#undef CPU_ICACHE_DISABLE
+#undef CPU_AFE_ENABLE
+
+/* Check for the identity mapping: For this configuration, this would be
+ * the case where the virtual beginning of RAM is the same as the physical
+ * beginning of RAM.
+ */
+
+#if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
+# error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
+#endif
+
+#if CONFIG_RAM_START == CONFIG_RAM_VSTART
+# define CONFIG_IDENTITY_TEXTMAP 1
+#endif
+
+/****************************************************************************
+ * .text
+ ****************************************************************************/
+
+ .text
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ * Boot functions for each CPU (other than CPU0). These functions set up
+ * the ARM operating mode, the initial stack, and configure co-processor
+ * registers. At the end of the boot, arm_cpu_boot() is called.
+ *
+ * These functions are provided by the common ARMv7-A logic.
+ *
+ * Input parameters:
+ * None
+ *
+ * Returned Value:
+ * Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+ .global __cpu1_start
+ .type __cpu1_start, #function
+
+__cpu1_start:
+ /* Set up the stack pointer and the CPU index */
+
+ ldr sp, .Lcpu1_stackpointer
+ mov r5, #1
+
+ /* Then branch to the common startup logic (PC-relative) */
+
+ b .Lcpu_start
+
+.Lcpu1_stackpointer:
+ .long .Lcpu1_stacktop
+ .size __cpu1_start, .-__cpu1_start
+
+#if CONFIG_SMP_NCPUS > 2
+ .global __cpu2_start
+ .type __cpu2_start, #function
+
+__cpu2_start:
+ /* Set up the stack pointer and the CPU index */
+
+ ldr sp, .Lcpu2_stackpointer
+ mov r5, #2
+
+ /* Then branch to the common startup logic (PC-relative) */
+
+ b .Lcpu_start
+
+.Lcpu2_stackpointer:
+ .long .Lcpu2_stacktop
+ .size __cpu2_start, .-__cpu2_start
+
+#if CONFIG_SMP_NCPUS > 3
+ .global __cpu3_start
+ .type __cpu3_start, #function
+
+__cpu3_start:
+ /* Set up the stack pointer and the CPU index */
+
+ ldr sp, .Lcpu3_stackpointer
+ mov r5, #3
+
+ /* Then branch to the common startup logic (PC-relative) */
+
+ b .Lcpu_start
+
+.Lcpu3_stackpointer:
+ .long .Lcpu3_stacktop
+ .size __cpu3_start, .-__cpu3_start
+
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Name: .Lcpu_start
+ *
+ * Description:
+ * Common CPUn startup logic (n > 0)
+ *
+ * On input:
+ * SP = Set to top of CPU IDLE stack (virtual)
+ * R5 = CPU number
+ *
+ ****************************************************************************/
+
+ .type .Lcpu_start, #function
+
+.Lcpu_start:
+ /* Make sure that we are in SVC mode with IRQs and FIQs disabled */
+
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+ msr cpsr_c, r0
+
+ /* The MMU and caches should be disabled */
+
+ mrc CP15_SCTLR(r0)
+ bic r0, r0, #(SCTLR_M | SCTLR_C)
+ bic r0, r0, #(SCTLR_I)
+ mcr CP15_SCTLR(r0)
+
+ /* Invalidate caches and TLBs.
+ *
+ * NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
+ * support a CP15 operation to invalidate the entire data cache. ...
+ * In normal usage the only time the entire data cache has to be
+ * invalidated is on reset."
+ *
+ * The instruction cache is virtually indexed and physically tagged but
+ * the data cache is physically indexed and physically tagged. So it
+ * should not be an issue if the system comes up with a dirty Dcache;
+ * the ICache, however, must be invalidated.
+ */
+
+ mov r0, #0
+ mcr CP15_TLBIALL(r0,c7) /* Invalidate the entire unified TLB */
+ mcr CP15_TLBIALL(r0,c6)
+ mcr CP15_TLBIALL(r0,c5)
+ mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
+ mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
+
+ /* Load the page table address.
+ *
+ * NOTES:
+ * - Here we assume that the page table address is aligned to at least
+ * least a 16KB boundary (bits 0-13 are zero). No masking is provided
+ * to protect against an unaligned page table address.
+ * - The ARMv7-A has two page table address registers, TTBR0 and 1.
+ * Only TTBR0 is used in this implementation but both are initialized.
+ */
+
+ ldr r1, .LCppgtable /* r1=phys. page table */
+ orr r1, r1, #(TTBR0_RGN_WBWA | TTBR0_IRGN0) /* Select cache properties */
+ mcr CP15_TTBR0(r1)
+ mcr CP15_TTBR1(r1)
+
+ /* Set the TTB control register (TTBCR) to indicate that we are using
+ * TTBR0. r0 still holds the value of zero.
+ *
+ * N : 0=Selects TTBR0 and 16KB page table size indexed by VA[31:20]
+ * PD0 : 0=Perform translation table walks using TTBR0
+ * PD1 : 0=Perform translation table walks using TTBR1 (but it is disabled)
+ * EAE : 0=Use 32-bit translation system
+ */
+
+ mcr CP15_TTBCR(r0)
+
+ /* Enable the MMU and caches
+ * lr = Resume at .Lcpu_vstart with the MMU enabled
+ */
+
+ ldr lr, .LCcpu_vstart /* Abs. virtual address */
+
+ /* Configure the domain access register (see mmu.h). Only domain 0 is
+ * supported and it uses the permissions in the TLB.
+ */
+
+ mov r0, #DACR_CLIENT(0)
+ mcr CP15_DACR(r0) /* Set domain access register */
+
+ /* Configure the system control register (see sctrl.h) */
+
+ mrc CP15_SCTLR(r0) /* Get control register */
+
+ /* Clear bits to reset values. This is only necessary in situations like, for
+ * example, we get here via a bootloader and the control register is in some
+ * unknown state.
+ *
+ * SCTLR_M Bit 0: Enable the MMU
+ * SCTLR_A Bit 1: Strict alignment disabled (reset value)
+ * SCTLR_C Bit 2: DCache disabled (reset value)
+ *
+ * SCTLR_SW Bit 10: SWP/SWPB not enabled (reset value)
+ * SCTLR_I Bit 12: ICache disabled (reset value)
+ * SCTLR_V Bit 13: Assume low vectors (reset value)
+ * SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
+ * replacement strategy.
+ * SCTLR_HA Bit 17: Not supported by A5
+ *
+ * SCTLR_EE Bit 25: 0=Little endian (reset value).
+ * SCTLR_TRE Bit 28: No memory region remapping (reset value)
+ * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
+ * SCTLR_TE Bit 30: All exceptions handled in ARM state (reset value).
+ */
+
+ bic r0, r0, #(SCTLR_A | SCTLR_C)
+ bic r0, r0, #(SCTLR_SW | SCTLR_I | SCTLR_V | SCTLR_RR | SCTLR_HA)
+ bic r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
+
+ /* Set bits to enable the MMU
+ *
+ * SCTLR_M Bit 0: Enable the MMU
+ * SCTLR_Z Bit 11: Program flow prediction control always enabled on A5
+ */
+
+ orr r0, r0, #(SCTLR_M)
+#ifndef CONFIG_ARCH_CORTEXA5
+ orr r0, r0, #(SCTLR_Z)
+#endif
+
+#ifndef CONFIG_ARCH_LOWVECTORS
+ /* Position vectors to 0xffff0000 if so configured.
+ *
+ * SCTLR_V Bit 13: High vectors
+ */
+
+ orr r0, r0, #(SCTLR_V)
+#endif
+
+#if defined(CPU_CACHE_ROUND_ROBIN) && !defined(CONFIG_ARCH_CORTEXA5)
+ /* Round Robin cache replacement
+ *
+ * SCTLR_RR Bit 14: The Cortex-A5 processor only supports a fixed random
+ * replacement strategy.
+ */
+
+ orr r0, r0, #(SCTLR_RR)
+#endif
+
+#ifndef CPU_DCACHE_DISABLE
+ /* Dcache enable
+ *
+ * SCTLR_C Bit 2: DCache enable
+ */
+
+ orr r0, r0, #(SCTLR_C)
+#endif
+
+#ifndef CPU_ICACHE_DISABLE
+ /* Icache enable
+ *
+ * SCTLR_I Bit 12: ICache enable
+ */
+
+ orr r0, r0, #(SCTLR_I)
+#endif
+
+#ifdef CPU_ALIGNMENT_TRAP
+ /* Alignment abort enable
+ *
+ * SCTLR_A Bit 1: Strict alignment enabled
+ */
+
+ orr r0, r0, #(SCTLR_A)
+#endif
+
+#ifdef CONFIG_ENDIAN_BIG
+ /* Big endian mode
+ *
+ * SCTLR_EE Bit 25: 1=Big endian.
+ */
+
+ orr r0, r0, #(SCTLR_EE)
+#endif
+
+#ifdef CPU_AFE_ENABLE
+ /* AP[0:2] Permissions model
+ *
+ * SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
+ *
+ * When AFE=1, the page table AP[0] is used as an access flag and AP[2:1]
+ * control. When AFE=0, AP[2:0] control access permissions.
+ */
+
+ orr r0, r0, #(SCTLR_AFE)
+#endif
+
+ /* Then write the configured control register */
+
+ mcr CP15_SCTLR(r0) /* Write control reg */
+ .rept 12 /* Cortex A8 wants lots of NOPs here */
+ nop
+ .endr
+
+ /* And "jump" to .Lcpu_vstart in the newly mapped virtual address space */
+
+ mov pc, lr
+
+/****************************************************************************
+ * PC_Relative Data
+ ****************************************************************************/
+
+ /* The physical base address of the page table */
+
+ .type .LCppgtable, %object
+.LCppgtable:
+ .long PGTABLE_BASE_PADDR /* Physical start of page table */
+ .size .LCppgtable, . -.LCppgtable
+
+ /* The virtual start address of the second phase boot logic */
+
+ .type .LCcpu_vstart, %object
+.LCcpu_vstart:
+ .long .Lcpu_vstart
+ .size .LCcpu_vstart, . -.LCcpu_vstart
+
+ .size .Lcpu_start, .-.Lcpu_start
+
+/****************************************************************************
+ * Name: .Lcpu_vstart
+ *
+ * Description:
+ * Continue initialization after the MMU has been enabled.
+ *
+ * The following is executed after the MMU has been enabled. This uses
+ * absolute addresses; this is not position independent.
+ *
+ * On input:
+ * SP = Set to top of CPU IDLE stack (virtual)
+ * R5 = CPU number
+ *
+ ****************************************************************************/
+
+ .align 8
+ .globl arm_cpu_boot
+ .type .Lcpu_vstart, %function
+
+.Lcpu_vstart:
+
+#ifdef CONFIG_STACK_COLORATION
+ /* Write a known value to the IDLE thread stack to support stack
+ * monitoring logic
+ */
+
+ adr r3, .Lstkinit
+ ldmia r3, {r0, r1, r2} /* R0 = start of IDLE stack; R1 = Size of stack; R2 = coloration */
+
+1: /* Top of the loop */
+ sub r1, r1, #1 /* R1 = Number of words remaining */
+ cmp r1, #0 /* Check (nwords == 0) */
+ str r2, [r0], #4 /* Save stack color word, increment stack address */
+ bne 1b /* Bottom of the loop */
+#endif
+
+ /* Branch to continue C level CPU initialization */
+
+ mov fp, #0 /* Clear framepointer */
+ mov lr, #0 /* LR = return address (none) */
+ mov r0, r5 /* Input parameter = CPU index */
+ b arm_cpu_boot /* Branch to C level CPU initialization */
+ .size .Lcpu_vstart, .-.Lcpu_vstart
+
+/***************************************************************************
+ * Text-section constants
+ ***************************************************************************/
+
+ /* Text-section constants: */
+
+#ifdef CONFIG_STACK_COLORATION
+ .type .Lstkinit, %object
+.Lstkinit:
+ .long SMP_STACK_WORDS
+ .long STACK_COLOR /* Stack coloration word */
+ .size .Lstkinit, . -.Lstkinit
+#endif
+
+/***************************************************************************
+ * .noinit section data
+ ***************************************************************************/
+
+ .section .noinit, "aw"
+
+#if CONFIG_SMP_NCPUS > 1
+ .align 8
+ .globl g_cpu1_idlestack
+ .type g_cpu1_idlestack, object
+
+g_cpu1_idlestack:
+ .space SMP_STACK_SIZE
+.Lcpu1_stacktop:
+ .size g_cpu1_idlestack, .Lcpu1_stacktop-g_cpu1_idlestack
+
+#if CONFIG_SMP_NCPUS > 2
+ .align 8
+ .globl g_cpu2_idlestack
+ .type g_cpu2_idlestack, object
+
+g_cpu2_idlestack:
+ .space SMP_STACK_SIZE
+.Lcpu2_stacktop:
+ .size g_cpu2_idlestack, .Lcpu2_stacktop-g_cpu2_idlestack
+
+#if CONFIG_SMP_NCPUS > 3
+ .align 8
+ .globl g_cpu3_idlestack
+ .type g_cpu3_idlestack, object
+
+g_cpu3_idlestack:
+ .space SMP_STACK_SIZE
+.Lcpu3_stacktop:
+ .size g_cpu3_idlestack, .Lcpu3_stacktop-g_cpu3_idlestack
+
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+ .end
diff --git a/arch/arm/src/armv7-a/arm_cpuidlestack.c b/arch/arm/src/armv7-a/arm_cpuidlestack.c
new file mode 100644
index 00000000000..fe191233216
--- /dev/null
+++ b/arch/arm/src/armv7-a/arm_cpuidlestack.c
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuidlestack.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include
+#include
+
+#include "smp.h"
+#include "up_internal.h"
+
+#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Stack alignment macros */
+
+#define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~SMP_STACK_MASK)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR const uint32_t *g_cpu_stackalloc[CONFIG_SMP_NCPUS] =
+{
+ 0
+ , g_cpu1_idlestack
+#if CONFIG_SMP_NCPUS > 2
+ , g_cpu2_idlestack
+#if CONFIG_SMP_NCPUS > 3
+ , g_cpu3_idlestack
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_idlestack
+ *
+ * Description:
+ * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ * setup up stack-related information in the IDLE task's TCB. This
+ * function is always called before up_cpu_start(). This function is
+ * only called for the CPU's initial IDLE task; up_create_task is used for
+ * all normal tasks, pthreads, and kernel threads for all CPUs.
+ *
+ * The initial IDLE task is a special case because the CPUs can be started
+ * in different wans in different environments:
+ *
+ * 1. The CPU may already have been started and waiting in a low power
+ * state for up_cpu_start(). In this case, the IDLE thread's stack
+ * has already been allocated and is already in use. Here
+ * up_cpu_idlestack() only has to provide information about the
+ * already allocated stack.
+ *
+ * 2. The CPU may be disabled but started when up_cpu_start() is called.
+ * In this case, a new stack will need to be created for the IDLE
+ * thread and this function is then equivalent to:
+ *
+ * up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ *
+ * The following TCB fields must be initialized by this function:
+ *
+ * - adj_stack_size: Stack size after adjustment for hardware, processor,
+ * etc. This value is retained only for debug purposes.
+ * - stack_alloc_ptr: Pointer to allocated stack
+ * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
+ * the stack pointer.
+ *
+ * Inputs:
+ * - cpu: CPU index that indicates which CPU the IDLE task is
+ * being created for.
+ * - tcb: The TCB of new CPU IDLE task
+ * - stack_size: The requested stack size for the IDLE task. At least
+ * this much must be allocated. This should be
+ * CONFIG_SMP_STACK_SIZE.
+ *
+ ****************************************************************************/
+
+int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
+{
+ uintptr_t stack_alloc;
+ uintptr_t top_of_stack;
+
+ DEBUGASSERT(cpu > 0 && cpu < CONFIG_SMP_NCPUS && tcb != NULL &&
+ stack_size <= SMP_STACK_SIZE);
+
+ /* Get the top of the stack */
+
+
+ stack_alloc = (uintptr_t)g_cpu_stackalloc[cpu];
+ DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
+ top_of_stack = stack_alloc + SMP_STACK_TOP;
+
+ tcb->adj_stack_size = SMP_STACK_SIZE;
+ tcb->stack_alloc_ptr = (FAR uint32_t *)stack_alloc;
+ tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack;
+
+ return OK;
+}
+
+#endif /* CONFIG_SMP && CONFIG_SMP_NCPUS > 1 */
diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index 5af4f17ddf7..220026da340 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -630,18 +630,18 @@ __start:
#ifndef CONFIG_BOOT_SDRAM_DATA
/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
* ready to use. Other memory, such as SDRAM, must be initialized before
- * it can be used. up_boot() will perform that memory initialization and
- * .bss and .data can be initialized after up_boot() returns.
+ * it can be used. arm_boot() will perform that memory initialization and
+ * .bss and .data can be initialized after arm_boot() returns.
*/
bl arm_data_initialize
#endif
/* Perform early C-level, platform-specific initialization. Logic
- * within up_boot() must configure SDRAM and call arm_ram_initailize.
+ * within arm_boot() must configure SDRAM and call arm_ram_initailize.
*/
- bl up_boot
+ bl arm_boot
#ifdef CONFIG_STACK_COLORATION
/* Write a known value to the IDLE thread stack to support stack
diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S
index e785360dfec..bc4c99ce26d 100644
--- a/arch/arm/src/armv7-a/arm_pghead.S
+++ b/arch/arm/src/armv7-a/arm_pghead.S
@@ -650,8 +650,8 @@ __start:
/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
* ready to use. Other memory, such as SDRAM, must be initialized before
- * it can be used. up_boot() will perform that memory initialization and
- * .bss and .data can be initialized after up_boot() returns.
+ * it can be used. arm_boot() will perform that memory initialization and
+ * .bss and .data can be initialized after arm_boot() returns.
*/
/* Set up the stack pointer and clear the frame pointer */
@@ -662,18 +662,18 @@ __start:
#ifndef CONFIG_BOOT_SDRAM_DATA
/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
* ready to use. Other memory, such as SDRAM, must be initialized before
- * it can be used. up_boot() will perform that memory initialization and
- * .bss and .data can be initialized after up_boot() returns.
+ * it can be used. arm_boot() will perform that memory initialization and
+ * .bss and .data can be initialized after arm_boot() returns.
*/
bl arm_data_initialize
#endif
/* Perform early C-level, platform-specific initialization. Logic
- * within up_boot() must configure SDRAM and call arm_ram_initailize.
+ * within arm_boot() must configure SDRAM and call arm_ram_initailize.
*/
- bl up_boot
+ bl arm_boot
#ifdef CONFIG_STACK_COLORATION
/* Write a known value to the IDLE thread stack to support stack
diff --git a/arch/arm/src/armv7-a/arm_pginitialize.c b/arch/arm/src/armv7-a/arm_pginitialize.c
index f419a28ba4c..94b44449ed2 100644
--- a/arch/arm/src/armv7-a/arm_pginitialize.c
+++ b/arch/arm/src/armv7-a/arm_pginitialize.c
@@ -88,7 +88,7 @@ void up_pginitialize(void)
{
/* None needed at present. This file is just retained in case the need
* arises in the future. Nothing calls up_pginitialize() now. If needed,
- * if should be called early in up_boot.c to assure that all paging is
+ * if should be called early in arm_boot.c to assure that all paging is
* ready.
*/
}
diff --git a/arch/arm/src/armv7-a/smp.h b/arch/arm/src/armv7-a/smp.h
new file mode 100644
index 00000000000..7c9d1cc72af
--- /dev/null
+++ b/arch/arm/src/armv7-a/smp.h
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/smp.h
+ * Common ARM support for SMP on multi-core CPUs.
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARMV7_A_SMP_H
+#define __ARCH_ARM_SRC_ARMV7_A_SMP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* ARM requires at least a 4-byte stack alignment. For use with EABI and
+ * floating point, the stack must be aligned to 8-byte addresses. We will
+ * always use the EABI stack alignment
+ */
+
+#define SMP_STACK_ALIGNMENT 8
+#define SMP_STACK_MASK 7
+#define SMP_STACK_SIZE ((CONFIG_SMP_IDLETHREAD_STACKSIZE + 7) & ~7)
+#define SMP_STACK_WORDS (SMP_STACK_SIZE >> 2)
+#define SMP_STACK_TOP (SMP_STACK_SIZE - 8)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if CONFIG_SMP_NCPUS > 1
+extern uint32_t g_cpu1_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 2
+extern uint32_t g_cpu2_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 3
+extern uint32_t g_cpu3_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ * Boot functions for each CPU (other than CPU0). These functions set up
+ * the ARM operating mode, the initial stack, and configure co-processor
+ * registers. At the end of the boot, arm_cpu_boot() is called.
+ *
+ * These functions are provided by the common ARMv7-A logic.
+ *
+ * Input parameters:
+ * None
+ *
+ * Returned Value:
+ * Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+void __cpu1_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 2
+void __cpu2_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 3
+void __cpu3_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif
+
+/****************************************************************************
+ * Name: arm_cpu_boot
+ *
+ * Description:
+ * Continues the C-level initialization started by the assembly language
+ * __cpu[n]_start function. At a minimum, this function needs to initialize
+ * interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
+ * issue an SGI.
+ *
+ * This function must be provided by the each ARMv7-A MCU and implement
+ * MCU-specific initialization logic.
+ *
+ * Input parameters:
+ * cpu - The CPU index. This is the same value that would be obtained by
+ * calling up_cpu_index();
+ *
+ * Returned Value:
+ * Does not return.
+ *
+ ****************************************************************************/
+
+void arm_cpu_boot(int cpu);
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_SMP */
+#endif /* __ARCH_ARM_SRC_ARMV7_A_SMP_H */
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index 0e8650c76cd..8dccf8a1ef0 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -331,7 +331,7 @@ EXTERN uint32_t _eramfuncs; /* Copy destination end address in RAM */
/* Low level initialization provided by board-level logic ******************/
-void up_boot(void);
+void arm_boot(void);
/* Context switching */
diff --git a/arch/arm/src/dm320/dm320_boot.c b/arch/arm/src/dm320/dm320_boot.c
index 4ba55ac1726..aba87ed2400 100644
--- a/arch/arm/src/dm320/dm320_boot.c
+++ b/arch/arm/src/dm320/dm320_boot.c
@@ -202,7 +202,7 @@ static void up_copyvectorblock(void)
* Public Functions
************************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
/* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all
* IO regions (Including the vector region).
diff --git a/arch/arm/src/imx1/imx_boot.c b/arch/arm/src/imx1/imx_boot.c
index f28d2cd7ee1..c429a317491 100644
--- a/arch/arm/src/imx1/imx_boot.c
+++ b/arch/arm/src/imx1/imx_boot.c
@@ -195,7 +195,7 @@ static void up_copyvectorblock(void)
* Public Functions
************************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
/* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all
* IO regions (Including the vector region).
diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs
index 8ddf77b5e84..3f949158e36 100644
--- a/arch/arm/src/imx6/Make.defs
+++ b/arch/arm/src/imx6/Make.defs
@@ -49,6 +49,9 @@ ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
else
CMN_ASRCS = arm_head.S
+ifeq ($(CONFIG_SMP),y)
+CMN_ASRCS += arm_cpuhead.S
+endif
endif
# Common assembly language files
@@ -77,7 +80,7 @@ CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c
ifeq ($(CONFIG_SMP),y)
-CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c
+CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
endif
ifeq ($(CONFIG_DEBUG_IRQ),y)
@@ -145,5 +148,5 @@ CHIP_CSRCS += imx_timerisr.c imx_gpio.c imx_iomuxc.c
CHIP_CSRCS += imx_serial.c imx_lowputc.c
ifeq ($(CONFIG_SMP),y)
-CHIP_CSRCS += imx_cpuinit.c
+CHIP_CSRCS += imx_cpuboot.c
endif
diff --git a/arch/arm/src/imx6/chip/imx_src.h b/arch/arm/src/imx6/chip/imx_src.h
new file mode 100644
index 00000000000..b49a9b44254
--- /dev/null
+++ b/arch/arm/src/imx6/chip/imx_src.h
@@ -0,0 +1,212 @@
+/****************************************************************************************************
+ * arch/arm/src/imx6/imx_src.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Reference:
+ * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number
+ * IMX6DQRM, Rev. 3, 07/2015, FreeScale.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
+#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+#include
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* SRC Register Offsets *****************************************************************************/
+
+#define IMX_SRC_SCR_OFFSET 0x0000 /* SRC Control Register */
+#define IMX_SRC_SBMR1_OFFSET 0x0004 /* SRC Boot Mode Register 1 */
+#define IMX_SRC_SRSR_OFFSET 0x0008 /* SRC Reset Status Register */
+#define IMX_SRC_SISR_OFFSET 0x0014 /* SRC Interrupt Status Register */
+#define IMX_SRC_SIMR_OFFSET 0x0018 /* SRC Interrupt Mask Register */
+#define IMX_SRC_SBMR2_OFFSET 0x001c /* SRC Boot Mode Register 2 */
+#define IMX_SRC_GPR1_OFFSET 0x0020 /* SRC General Purpose Register 1 */
+#define IMX_SRC_GPR2_OFFSET 0x0024 /* SRC General Purpose Register 2 */
+#define IMX_SRC_GPR3_OFFSET 0x0028 /* SRC General Purpose Register 3 */
+#define IMX_SRC_GPR4_OFFSET 0x002c /* SRC General Purpose Register 4 */
+#define IMX_SRC_GPR5_OFFSET 0x0030 /* SRC General Purpose Register 5 */
+#define IMX_SRC_GPR6_OFFSET 0x0034 /* SRC General Purpose Register 6 */
+#define IMX_SRC_GPR7_OFFSET 0x0038 /* SRC General Purpose Register 7 */
+#define IMX_SRC_GPR8_OFFSET 0x003c /* SRC General Purpose Register 8 */
+#define IMX_SRC_GPR9_OFFSET 0x0040 /* SRC General Purpose Register 9 */
+#define IMX_SRC_GPR10_OFFSET 0x0044 /* SRC General Purpose Register 10 */
+
+/* SRC Register Addresses ***************************************************************************/
+
+#define IMX_SRC_SCR (IMX_SRC_VBASE+IMX_SRC_SCR_OFFSET)
+#define IMX_SRC_SBMR1 (IMX_SRC_VBASE+IMX_SRC_SBMR1_OFFSET)
+#define IMX_SRC_SRSR (IMX_SRC_VBASE+IMX_SRC_SRSR_OFFSET)
+#define IMX_SRC_SISR (IMX_SRC_VBASE+IMX_SRC_SISR_OFFSET)
+#define IMX_SRC_SIMR (IMX_SRC_VBASE+IMX_SRC_SIMR_OFFSET)
+#define IMX_SRC_SBMR2 (IMX_SRC_VBASE+IMX_SRC_SBMR2_OFFSET)
+#define IMX_SRC_GPR1 (IMX_SRC_VBASE+IMX_SRC_GPR1_OFFSET)
+#define IMX_SRC_GPR2 (IMX_SRC_VBASE+IMX_SRC_GPR2_OFFSET)
+#define IMX_SRC_GPR3 (IMX_SRC_VBASE+IMX_SRC_GPR3_OFFSET)
+#define IMX_SRC_GPR4 (IMX_SRC_VBASE+IMX_SRC_GPR4_OFFSET)
+#define IMX_SRC_GPR5 (IMX_SRC_VBASE+IMX_SRC_GPR5_OFFSET)
+#define IMX_SRC_GPR6 (IMX_SRC_VBASE+IMX_SRC_GPR6_OFFSET)
+#define IMX_SRC_GPR7 (IMX_SRC_VBASE+IMX_SRC_GPR7_OFFSET)
+#define IMX_SRC_GPR8 (IMX_SRC_VBASE+IMX_SRC_GPR8_OFFSET)
+#define IMX_SRC_GPR9 (IMX_SRC_VBASE+IMX_SRC_GPR9_OFFSET)
+#define IMX_SRC_GPR10 (IMX_SRC_VBASE+IMX_SRC_GPR10_OFFSET)
+
+/* SRC Register Bit Definitions *********************************************************************/
+
+/* SRC Control Register: Reset value 0x00000521 */
+
+#define SRC_SCR_WARM_RESET_ENABLE (1 << 0) /* Bit 0: WARM reset enable bit */
+#define SRC_SCR_SW_GPU_RST (1 << 1) /* Bit 1: Software reset for GPU */
+#define SRC_SCR_SW_VPU_RST (1 << 2) /* Bit 2: Software reset for VPU */
+#define SRC_SCR_SW_IPU1_RST (1 << 3) /* Bit 3: Software reset for IPU1 */
+#define SRC_SCR_SW_OPEN_VG_RST (1 << 4) /* Bit 4: Software reset for open_vg */
+#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5) /* Bits 5-6: XTALI cycles before bypassing the MMDC ack */
+#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)
+# define SRC_SCR_WARM_RST_BYPASS_COUNT_NONE (0 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* Counter not used */
+# define SRC_SCR_WARM_RST_BYPASS_COUNT_16 (1 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 16 XTALI cycles before WARM to COLD reset */
+# define SRC_SCR_WARM_RST_BYPASS_COUNT_32 (2 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 32 XTALI cycles before WARM to COLD reset */
+# define SRC_SCR_WARM_RST_BYPASS_COUNT_64 (3 << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT) /* 64 XTALI cycles before WARM to COLD reset */
+#define SRC_SCR_MASK_WDOG_RST_SHIFT (7) /* Bits 7-10: Mask wdog_rst_b source */
+#define SRC_SCR_MASK_WDOG_RST_MASK (15 << SRC_SCR_MASK_WDOG_RST_SHIFT)
+# define SRC_SCR_MASK_WDOG_RST_MASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is masked */
+# define SRC_SCR_MASK_WDOG_RST_UNMASKED (15 << SRC_SCR_MASK_WDOG_RST_SHIFT) /* wdog_rst_b is not masked */
+#define SRC_SCR_EIM_RST (1 << 11) /* Bit 11: EIM reset is needed in order to reconfigure the eim chip select */
+#define SRC_SCR_SW_IPU2_RST (1 << 12) /* Bit 12: Software reset for ipu2 */
+#define SRC_SCR_CORE0_RST (1 << 13) /* Bit 13: Software reset for core0 */
+#define SRC_SCR_CORE1_RST (1 << 14) /* Bit 14: Software reset for core1 */
+#define SRC_SCR_CORE2_RST (1 << 15) /* Bit 15: Software reset for core2 */
+#define SRC_SCR_CORE3_RST (1 << 16) /* Bit 16: Software reset for core3 */
+#define SRC_SCR_CORE0_DBG_RST (1 << 17) /* Bit 17: Software reset for core0 debug */
+#define SRC_SCR_CORE1_DBG_RST (1 << 18) /* Bit 18: Software reset for core1 debug */
+#define SRC_SCR_CORE2_DBG_RST (1 << 19) /* Bit 19: Software reset for core2 debug */
+#define SRC_SCR_CORE3_DBG_RST (1 << 20) /* Bit 20: Software reset for core3 debug */
+#define SRC_SCR_CORES_DBG_RST (1 << 21) /* Bit 21: Software reset for debug of arm platform */
+#define SRC_SCR_CORE1_ENABLE (1 << 22) /* Bit 22: core1 enable */
+#define SRC_SCR_CORE2_ENABLE (1 << 23) /* Bit 23: core2 enable */
+#define SRC_SCR_CORE3_ENABLE (1 << 24) /* Bit 24: core3 enable */
+#define SRC_SCR_DBG_RST_MSK_PG (1 << 25) /* Bit 25: No debug resets after core power gating event */
+ /* Bits 26-31: Reserved */
+
+/* SRC Boot Mode Register 1 */
+
+#define SRC_SBMR1_BOOT_CFG1_SHIFT (0) /* Bits 0-7: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG1_MASK (0xff << SRC_SBMR1_BOOT_CFG1_SHIFT)
+# define SRC_SBMR1_BOOT_CFG1(n) ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG1_SHIFT)
+#define SRC_SBMR1_BOOT_CFG2_SHIFT (8) /* Bits 8-15: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG2_MASK (0xff << SRC_SBMR1_BOOT_CFG2_SHIFT)
+# define SRC_SBMR1_BOOT_CFG2(n) ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG2_SHIFT)
+#define SRC_SBMR1_BOOT_CFG3_SHIFT (16) /* Bits 16-23: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG3_MASK (0xff << SRC_SBMR1_BOOT_CFG3_SHIFT)
+# define SRC_SBMR1_BOOT_CFG3(n) ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG3_SHIFT)
+#define SRC_SBMR1_BOOT_CFG4_SHIFT (24) /* Bits 24-31: Refer to fusemap */
+#define SRC_SBMR1_BOOT_CFG4_MASK (0xff << SRC_SBMR1_BOOT_CFG4_SHIFT)
+# define SRC_SBMR1_BOOT_CFG4(n) ((uint32_t)(n) << SRC_SBMR1_BOOT_CFG4_SHIFT)
+
+/* SRC Reset Status Register */
+
+#define SRC_SRSR_IPP_RESET (1 << 0) /* Bit 0: Reset result of ipp_reset_b pin (Power-up sequence) */
+ /* Bit 1: Reserved */
+#define SRC_SRSR_CSU_RESET (1 << 2) /* Bit 2: Reset result of the csu_reset_b input */
+#define SRC_SRSR_IPP_USER_RESET (1 << 3) /* Bit 3: Reset result of ipp_user_reset_b qualified reset */
+#define SRC_SRSR_WDOG_RST (1 << 4) /* Bit 4: IC Watchdog Time-out reset */
+#define SRC_SRSR_JTAG_RST (1 << 5) /* Bit 5: HIGH - Z JTAG reset */
+#define SRC_SRSR_JTAG_SW_RST (1 << 6) /* Bit 6: JTAG software reset */
+ /* Bits 7-15: Reserved */
+#define SRC_SRSR_WARM_BOOT (1 << 16) /* Bit 16: WARM boot indication shows that WARM boot was initiated by software */
+ /* Bits 17-31: Reserved */
+
+/* SRC Interrupt Status Register */
+
+#define SRC_SISR_GPU_PASSED_RESET (1 << 0) /* Bit 0: GPU passed software reset and is ready */
+#define SRC_SISR_VPU_PASSED_RESET (1 << 1) /* Bit 1: VPU passed software reset and is ready */
+#define SRC_SISR_IPU1_PASSED_RESET (1 << 2) /* Bit 2: ipu passed software reset and is ready */
+#define SRC_SISR_OPEN_VG_PASSED_RESET (1 << 3) /* Bit 3: open_vg passed software reset and is ready */
+#define SRC_SISR_IPU2_PASSED_RESET (1 << 4) /* Bit 4: ipu2 passed software reset and is ready */
+#define SRC_SISR_CORE0_WDOG_RST_REQ (1 << 5) /* Bit 5: WDOG reset request from core0 */
+#define SRC_SISR_CORE1_WDOG_RST_REQ (1 << 6) /* Bit 6: WDOG reset request from core1 */
+#define SRC_SISR_CORE2_WDOG_RST_REQ (1 << 7) /* Bit 7: WDOG reset request from core2 */
+#define SRC_SISR_CORE3_WDOG_RST_REQ (1 << 8) /* Bit 8: WDOG reset request from core3 */
+ /* Bits 9-31: Reserved */
+
+/* SRC Interrupt Mask Register */
+#define SRC_SIMR_
+
+#define SRC_SIMR_GPU_PASSED_RESET (1 << 0) /* Bit 0: Mask GPU passed software reset interrupt */
+#define SRC_SIMR_VPU_PASSED_RESET (1 << 1) /* Bit 1: Mask VPU passed software reset interrupt */
+#define SRC_SIMR_IPU1_PASSED_RESET (1 << 2) /* Bit 2: Mask ipu passed software reset interrupt */
+#define SRC_SIMR_OPEN_VG_PASSED_RESET (1 << 3) /* Bit 3: Mask open_vg passed software reset interrupt */
+#define SRC_SIMR_IPU2_PASSED_RESET (1 << 4) /* Bit 4: Mask ipu2 passed software reset interrupt */
+ /* Bits 5-31: Reserved */
+
+/* SRC Boot Mode Register 2 */
+
+#define SRC_SBMR2_SEC_CONFIG_SHIFT (0) /* Bits 0-1: State of the SECONFIG fuses */
+ /* Bit 2: Reserved */
+#define SRC_SBMR2_DIR_BT_DIS (1 << 3) /* Bit 3: State of the DIR_BT_DIS fuse */
+#define SRC_SBMR2_BT_FUSE_SEL (1 << 4) /* Bit 4: State of the BT_FUSE_SEL fuse */
+ /* Bits 5-23: Reserved */
+#define SRC_SBMR2_BMOD_SHIFT (24) /* Bits 24-25: Latched state of the BOOT_MODE1 and BOOT_MODE0 */
+#define SRC_SBMR2_BMOD_MASK (3 << SRC_SBMR2_BMOD_SHIFT)
+ /* Bits 26-31: Reserved */
+
+/* SRC General Purpose Register 1: 32-bit PERSISTENT_ENTRY0: core0 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 2: 32-bit PERSISTENT_ARG0: core0 entry function argument */
+/* SRC General Purpose Register 3: 32-bit PERSISTENT_ENTRY1: core1 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 4: 32-bit PERSISTENT_ARG1: core1 entry function argument */
+/* SRC General Purpose Register 5: 32-bit PERSISTENT_ENTRY2: core2 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 6: 32-bit PERSISTENT_ARG2: core1 entry function argument */
+/* SRC General Purpose Register 7: 32-bit PERSISTENT_ENTRY3: core3 entry function for waking-up from low power mode */
+/* SRC General Purpose Register 8: 32-bit PERSISTENT_ARG3: core3 entry function argument */
+/* SRC General Purpose Register 9: Reserved */
+
+/* SRC General Purpose Register 10 */
+
+#define SRC_GPR10_RW1_SHIFT (0) /* Bits 0-24: General purpose R/W bits */
+#define SRC_GPR10_RW1_MASK (0x01ffffff << SRC_GPR10_RW1_SHIFT)
+# define SRC_GPR10_RW1(n) ((uint32_t)(n) << SRC_GPR10_RW1_SHIFT)
+#define SRC_GPR10_CORE1_ERROR_STATUS (1 << 25) /* Bit 25: core1 error status bit */
+#define SRC_GPR10_CORE2_ERROR_STATUS (1 << 26) /* Bit 26: core2 error status bit */
+#define SRC_GPR10_CORE3_ERROR_STATUS (1 << 27) /* Bit 27: core3 error status bit */
+#define SRC_GPR10_RW2_SHIFT (28) /* Bits 28-31: General purpose R/W bits */
+#define SRC_GPR10_RW2_MASK (15 << SRC_GPR10_RW2_SHIFT)
+# define SRC_GPR10_RW2(n) ((uint32_t)(n) << SRC_GPR10_RW2_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H */
diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c
index ae3cc1a123b..edfd5304a14 100644
--- a/arch/arm/src/imx6/imx_boot.c
+++ b/arch/arm/src/imx6/imx_boot.c
@@ -309,7 +309,7 @@ static void imx_copyvectorblock(void)
#ifndef CONFIG_IMX6_WDT
static inline void imx_wdtdisable(void)
{
-# warning REVISIT WDT initialization
+ /* REVISIT: WDT initialization */
}
#else
# define imx_wdtdisable()
@@ -320,7 +320,7 @@ static inline void imx_wdtdisable(void)
****************************************************************************/
/****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
*
* Description:
* Complete boot operations started in arm_head.S
@@ -386,7 +386,7 @@ static inline void imx_wdtdisable(void)
*
****************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
#ifdef CONFIG_ARCH_RAMFUNCS
const uint32_t *src;
@@ -400,6 +400,13 @@ void up_boot(void)
imx_setupmappings();
imx_lowputc('A');
+ /* Make sure that all other CPUs are in the disabled state. This is a
+ * formality because the other CPUs are actually running then we have
+ * probably already crashed.
+ */
+
+ imx_cpu_disable();
+
/* Provide a special mapping for the OCRAM interrupt vector positioned in
* high memory.
*/
@@ -498,5 +505,13 @@ void up_boot(void)
imx_earlyserialinit();
imx_lowputc('M');
#endif
+
+ /* Now we can enable all other CPUs. The enabled CPUs will start execution
+ * at __cpuN_start and, after very low-level CPU initialzation has been
+ * performed, will branch to arm_cpu_boot() (see arch/arm/src/armv7-a/smp.h)
+ */
+
+ imx_cpu_enable();
+ imx_lowputc('N');
imx_lowputc('\n');
}
diff --git a/arch/arm/src/imx6/imx_boot.h b/arch/arm/src/imx6/imx_boot.h
index 8e63cc9e9d6..11c1ef56fe3 100644
--- a/arch/arm/src/imx6/imx_boot.h
+++ b/arch/arm/src/imx6/imx_boot.h
@@ -51,23 +51,11 @@
#include "chip.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline Functions
+ * Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@@ -78,9 +66,50 @@ extern "C"
#endif
/****************************************************************************
- * Public Function Prototypes
+ * Name: imx_cpu_disable
+ *
+ * Description:
+ * Called from CPU0 to make sure that all other CPUs are in the disabled
+ * state. This is a formality because the other CPUs are actually running
+ * then we have probably already crashed.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
****************************************************************************/
+#ifdef CONFIG_SMP
+void imx_cpu_disable(void);
+#else
+# define imx_cpu_disable()
+#endif
+
+/****************************************************************************
+ * Name: imx_cpu_enable
+ *
+ * Description:
+ * Called from CPU0 to enable all other CPUs. The enabled CPUs will start
+ * execution at __cpuN_start and, after very low-level CPU initialzation
+ * has been performed, will branch to arm_cpu_boot()
+ * (see arch/arm/src/armv7-a/smp.h)
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+void imx_cpu_enable(void);
+#else
+# define imx_cpu_enable()
+#endif
+
/****************************************************************************
* Name: imx_board_initialize
*
diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c
new file mode 100644
index 00000000000..cc8494782e9
--- /dev/null
+++ b/arch/arm/src/imx6/imx_cpuboot.c
@@ -0,0 +1,302 @@
+/****************************************************************************
+ * arch/arm/src/imx6/imx_cpuboot.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip/imx_src.h"
+#include "sctlr.h"
+#include "smp.h"
+#include "gic.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+typedef CODE void (*cpu_start_t)(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
+{
+ 0,
+#if CONFIG_SMP_NCPUS > 1
+ SRC_SCR_CORE1_RST,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+ SRC_SCR_CORE2_RST,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+ SRC_SCR_CORE3_RST
+#endif
+};
+#endif
+
+static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
+{
+ 0,
+#if CONFIG_SMP_NCPUS > 1
+ SRC_SCR_CORE1_ENABLE,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+ SRC_SCR_CORE2_ENABLE,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+ SRC_SCR_CORE3_ENABLE
+#endif
+};
+
+static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
+{
+ 0,
+#if CONFIG_SMP_NCPUS > 1
+ IMX_SRC_GPR3,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+ IMX_SRC_GPR5,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+ IMX_SRC_GPR7
+#endif
+};
+
+static const cpu_start_t g_cpu_boot[CONFIG_SMP_NCPUS] =
+{
+ 0,
+#if CONFIG_SMP_NCPUS > 1
+ __cpu1_start,
+#endif
+#if CONFIG_SMP_NCPUS > 2
+ __cpu2_start,
+#endif
+#if CONFIG_SMP_NCPUS > 3
+ __cpu3_start
+#endif
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Symbols defined via the linker script */
+
+extern uint32_t _vector_start; /* Beginning of vector block */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imx_cpu_reset
+ *
+ * Description:
+ * CPUn software reset
+ *
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static void imx_cpu_reset(int cpu)
+{
+ uint32_t regval;
+
+ regval = getreg32(IMX_SRC_SCR);
+ regval |= g_cpu_reset[cpu];
+ putreg32(regval, IMX_SRC_SCR);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imx_cpu_disable
+ *
+ * Description:
+ * Called from CPU0 to make sure that all other CPUs are in the disabled
+ * state. This is a formality because the other CPUs are actually running
+ * then we have probably already crashed.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void imx_cpu_disable(void)
+{
+ uint32_t regval;
+ uint32_t cpumask;
+
+ cpumask = 0;
+#if CONFIG_SMP_NCPUS > 1
+ cpumask |= SRC_SCR_CORE1_ENABLE;
+#endif
+#if CONFIG_SMP_NCPUS > 2
+ cpumask |= SRC_SCR_CORE2_ENABLE;
+#endif
+#if CONFIG_SMP_NCPUS > 3
+ cpumask |= SRC_SCR_CORE3_ENABLE;
+#endif
+
+ regval = getreg32(IMX_SRC_SCR);
+ regval &= ~cpumask;
+ putreg32(regval, IMX_SRC_SCR);
+}
+
+/****************************************************************************
+ * Name: imx_cpu_enable
+ *
+ * Description:
+ * Called from CPU0 to enable all other CPUs. The enabled CPUs will start
+ * execution at __cpuN_start and, after very low-level CPU initialzation
+ * has been performed, will branch to arm_cpu_boot()
+ * (see arch/arm/src/armv7-a/smp.h)
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void imx_cpu_enable(void)
+{
+ cpu_start_t bootaddr;
+ uintptr_t regaddr;
+ uint32_t regval;
+ int cpu;
+
+ for (cpu = 1; cpu < CONFIG_SMP_NCPUS; cpu++)
+ {
+ /* Set the start up address */
+
+ regaddr = g_cpu_gpr[cpu];
+ bootaddr = g_cpu_boot[cpu];
+ putreg32((uint32_t)bootaddr, regaddr);
+
+ /* Then enable the CPU */
+
+ regval = getreg32(IMX_SRC_SCR);
+ regval |= g_cpu_ctrl[cpu];
+ putreg32(regval, IMX_SRC_SCR);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_cpu_boot
+ *
+ * Description:
+ * Continues the C-level initialization started by the assembly language
+ * __cpu[n]_start function. At a minimum, this function needs to initialize
+ * interrupt handling and, perhaps, wait on WFI for arm_cpu_start() to
+ * issue an SGI.
+ *
+ * This function must be provided by the each ARMv7-A MCU and implement
+ * MCU-specific initialization logic.
+ *
+ * Input parameters:
+ * cpu - The CPU index. This is the same value that would be obtained by
+ * calling up_cpu_index();
+ *
+ * Returned Value:
+ * Does not return.
+ *
+ ****************************************************************************/
+
+void arm_cpu_boot(int cpu)
+{
+ /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
+
+ arm_gic_initialize();
+
+#ifdef CONFIG_ARCH_LOWVECTORS
+ /* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
+ * beginning of the .text region must appear at address at the address
+ * specified in the VBAR. There are two ways to accomplish this:
+ *
+ * 1. By explicitly mapping the beginning of .text region with a page
+ * table entry so that the virtual address zero maps to the beginning
+ * of the .text region. VBAR == 0x0000:0000.
+ *
+ * 2. Set the Cortex-A5 VBAR register so that the vector table address
+ * is moved to a location other than 0x0000:0000.
+ *
+ * The second method is used by this logic.
+ */
+
+ /* Set the VBAR register to the address of the vector table */
+
+ DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
+ cp15_wrvbar((uint32_t)&_vector_start);
+#endif /* CONFIG_ARCH_LOWVECTORS */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* And finally, enable interrupts */
+
+ (void)up_irq_enable();
+#endif
+
+ /* The next thing that we expect to happen is for logic running on CPU0
+ * to call up_cpu_start() which generate an SGI and a context switch to
+ * the configured NuttX IDLE task.
+ */
+
+ for (; ; )
+ {
+ asm("WFI");
+ }
+}
+#endif /* CONFIG_SMP */
diff --git a/arch/arm/src/lpc31xx/lpc31.h b/arch/arm/src/lpc31xx/lpc31.h
index d16058a35cf..4a342a9a839 100644
--- a/arch/arm/src/lpc31xx/lpc31.h
+++ b/arch/arm/src/lpc31xx/lpc31.h
@@ -154,7 +154,7 @@ static inline void gpio_outputhigh(uint32_t ioconfig, uint32_t bit)
* Name: lpc31_lowsetup
*
* Description:
- * Called early in up_boot. Performs chip-common low level initialization.
+ * Called early in arm_boot. Performs chip-common low level initialization.
*
************************************************************************************/
diff --git a/arch/arm/src/lpc31xx/lpc31_boot.c b/arch/arm/src/lpc31xx/lpc31_boot.c
index 1932b8fee7d..11a3e71302a 100644
--- a/arch/arm/src/lpc31xx/lpc31_boot.c
+++ b/arch/arm/src/lpc31xx/lpc31_boot.c
@@ -333,14 +333,14 @@ static void up_copyvectorblock(void)
************************************************************************************/
/************************************************************************************
- * Name: up_boot
+ * Name: arm_boot
*
* Description:
* Complete boot operations started in up_head.S
*
************************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all
* IO regions (Including the vector region).
diff --git a/arch/arm/src/lpc31xx/lpc31_lowputc.c b/arch/arm/src/lpc31xx/lpc31_lowputc.c
index 189ad0b9c73..3e3213927f1 100644
--- a/arch/arm/src/lpc31xx/lpc31_lowputc.c
+++ b/arch/arm/src/lpc31xx/lpc31_lowputc.c
@@ -271,7 +271,7 @@ static inline void up_configbaud(void)
* Name: lpc31_lowsetup
*
* Description:
- * Called early in up_boot. Performs chip-common low level initialization.
+ * Called early in arm_boot. Performs chip-common low level initialization.
*
****************************************************************************/
diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c
index 58cae338248..d2d154613cb 100644
--- a/arch/arm/src/sama5/sam_boot.c
+++ b/arch/arm/src/sama5/sam_boot.c
@@ -338,7 +338,7 @@ static inline void sam_wdtdisable(void)
****************************************************************************/
/****************************************************************************
- * Name: up_boot
+ * Name: arm_boot
*
* Description:
* Complete boot operations started in arm_head.S
@@ -407,7 +407,7 @@ static inline void sam_wdtdisable(void)
*
****************************************************************************/
-void up_boot(void)
+void arm_boot(void)
{
#ifdef CONFIG_ARCH_RAMFUNCS
const uint32_t *src;
diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig
index 1f9941e3154..5a68712427d 100644
--- a/arch/arm/src/samv7/Kconfig
+++ b/arch/arm/src/samv7/Kconfig
@@ -26,7 +26,7 @@ config ARCH_CHIP_SAME70Q21
select ARCH_CHIP_SAME70Q
config ARCH_CHIP_SAME70N19
- bool "SAME70N10"
+ bool "SAME70N19"
select ARCH_CHIP_SAME70N
config ARCH_CHIP_SAME70N20
diff --git a/arch/avr/src/common/up_internal.h b/arch/avr/src/common/up_internal.h
index bc6a7ebf257..92a160ee90e 100644
--- a/arch/avr/src/common/up_internal.h
+++ b/arch/avr/src/common/up_internal.h
@@ -134,7 +134,6 @@ extern uint32_t _ebss; /* End+1 of .bss */
/* Defined in files with the same name as the function */
-void up_boot(void);
void up_irqinitialize(void);
#ifdef CONFIG_ARCH_DMA
void weak_function up_dmainitialize(void);
diff --git a/arch/hc/src/common/up_internal.h b/arch/hc/src/common/up_internal.h
index a2d44341551..1650711f3a6 100644
--- a/arch/hc/src/common/up_internal.h
+++ b/arch/hc/src/common/up_internal.h
@@ -157,10 +157,6 @@ extern uint32_t g_intstackbase;
* Public Functions
****************************************************************************/
-/* Start-up functions */
-
-void up_boot(void);
-
/* Context switching functions */
void up_copystate(uint8_t *dest, uint8_t *src);
diff --git a/arch/mips/src/pic32mx/pic32mx.h b/arch/mips/src/pic32mx/pic32mx.h
index ab8e50b491a..d636293703b 100644
--- a/arch/mips/src/pic32mx/pic32mx.h
+++ b/arch/mips/src/pic32mx/pic32mx.h
@@ -234,7 +234,7 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
*
* Description:
* This function must be provided by the board-specific logic in the directory
- * configs//up_boot.c.
+ * configs//pic32_boot.c.
*
************************************************************************************/
diff --git a/arch/sh/src/common/up_internal.h b/arch/sh/src/common/up_internal.h
index 724efbca93f..5f1a54bb3ef 100644
--- a/arch/sh/src/common/up_internal.h
+++ b/arch/sh/src/common/up_internal.h
@@ -155,7 +155,6 @@ extern uint32_t g_idle_topstack;
/* Defined in files with the same name as the function */
-void up_boot(void);
void up_copystate(uint32_t *dest, uint32_t *src);
void up_dataabort(uint32_t *regs);
void up_decodeirq(uint32_t *regs);
diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile
index f4f6270660e..406ac4ee934 100644
--- a/arch/sim/src/Makefile
+++ b/arch/sim/src/Makefile
@@ -70,7 +70,7 @@ ifeq ($(CONFIG_SPINLOCK),y)
endif
ifeq ($(CONFIG_SMP),y)
- CSRCS += up_smpsignal.c up_smphook.c
+ CSRCS += up_smpsignal.c up_smphook.c up_cpuidlestack.c
HOSTSRCS += up_simsmp.c
endif
diff --git a/arch/arm/src/imx6/imx_cpuinit.c b/arch/sim/src/up_cpuidlestack.c
similarity index 52%
rename from arch/arm/src/imx6/imx_cpuinit.c
rename to arch/sim/src/up_cpuidlestack.c
index d928781408b..ee728849a91 100644
--- a/arch/arm/src/imx6/imx_cpuinit.c
+++ b/arch/sim/src/up_cpuidlestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/imx6/imx_clockconfig.c
+ * arch/sim/src/up_cpuidlestack.c
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -39,9 +39,12 @@
#include
-#include
+#include
-#include "gic.h"
+#include
+#include
+
+#include "up_internal.h"
#ifdef CONFIG_SMP
@@ -50,28 +53,55 @@
****************************************************************************/
/****************************************************************************
- * Name: up_cpu_initialize
+ * Name: up_cpu_idlestack
*
* Description:
- * After the CPU has been started (via up_cpu_start()) the system will
- * call back into the architecture-specific code with this function on the
- * thread of execution of the newly started CPU. This gives the
- * architecture-specific a chance to perform ny initial, CPU-specific
- * initialize on that thread.
+ * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ * setup up stack-related information in the IDLE task's TCB. This
+ * function is always called before up_cpu_start(). This function is
+ * only called for the CPU's initial IDLE task; up_create_task is used for
+ * all normal tasks, pthreads, and kernel threads for all CPUs.
*
- * Input Parameters:
- * None
+ * The initial IDLE task is a special case because the CPUs can be started
+ * in different wans in different environments:
*
- * Returned Value:
- * Zero on success; a negated errno value on failure.
+ * 1. The CPU may already have been started and waiting in a low power
+ * state for up_cpu_start(). In this case, the IDLE thread's stack
+ * has already been allocated and is already in use. Here
+ * up_cpu_idlestack() only has to provide information about the
+ * already allocated stack.
+ *
+ * 2. The CPU may be disabled but started when up_cpu_start() is called.
+ * In this case, a new stack will need to be created for the IDLE
+ * thread and this function is then equivalent to:
+ *
+ * up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ *
+ * The following TCB fields must be initialized by this function:
+ *
+ * - adj_stack_size: Stack size after adjustment for hardware, processor,
+ * etc. This value is retained only for debug purposes.
+ * - stack_alloc_ptr: Pointer to allocated stack
+ * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
+ * the stack pointer.
+ *
+ * Inputs:
+ * - cpu: CPU index that indicates which CPU the IDLE task is
+ * being created for.
+ * - tcb: The TCB of new CPU IDLE task
+ * - stack_size: The requested stack size for the IDLE task. At least
+ * this much must be allocated. This should be
+ * CONFIG_SMP_IDLETHREAD_STACKSIZE.
*
****************************************************************************/
-int up_cpu_initialize(void)
+int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
- /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
+ /* REVISIT: I don't think anything is needed here */
- arm_gic_initialize();
+ tcb->adj_stack_size = stack_size;
+ tcb->stack_alloc_ptr = NULL;
+ tcb->adj_stack_ptr = NULL;
return OK;
}
diff --git a/arch/sim/src/up_smphook.c b/arch/sim/src/up_smphook.c
index 7c008a7d3d3..e871c42f0fb 100644
--- a/arch/sim/src/up_smphook.c
+++ b/arch/sim/src/up_smphook.c
@@ -51,29 +51,6 @@
* Public Functions
****************************************************************************/
-/****************************************************************************
- * Name: up_cpu_initialize
- *
- * Description:
- * After the CPU has been started (via up_cpu_start()) the system will
- * call back into the architecture-specific code with this function on the
- * thread of execution of the newly started CPU. This gives the
- * architecture-specific a chance to perform ny initial, CPU-specific
- * initialize on that thread.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Zero on success; a negated errno value on failure.
- *
- ****************************************************************************/
-
-int up_cpu_initialize(void)
-{
- return OK;
-}
-
/****************************************************************************
* Name: sim_smp_hook
*
diff --git a/arch/x86/src/common/up_internal.h b/arch/x86/src/common/up_internal.h
index db35e68035a..d0eb1570c36 100644
--- a/arch/x86/src/common/up_internal.h
+++ b/arch/x86/src/common/up_internal.h
@@ -192,7 +192,6 @@ void x86_boardinitialize(void);
/* Defined in files with the same name as the function */
-void up_boot(void);
void up_copystate(uint32_t *dest, uint32_t *src);
void up_savestate(uint32_t *regs);
void up_decodeirq(uint32_t *regs);
diff --git a/configs/ea3131/locked/mklocked.sh b/configs/ea3131/locked/mklocked.sh
index 29b357ae399..97a126015d9 100755
--- a/configs/ea3131/locked/mklocked.sh
+++ b/configs/ea3131/locked/mklocked.sh
@@ -140,9 +140,9 @@ fi
# consequence, the 1-time initialization code takes up precious memory
# in the locked memory region.
#
-# up_boot is a low-level initialization function called by __start:
+# arm_boot is a low-level initialization function called by __start:
-echo "EXTERN(up_boot)" >>ld-locked.inc
+echo "EXTERN(arm_boot)" >>ld-locked.inc
# All of the initialization functions that are called by os_start up to
# the point where the page fill worker thread is started must also be
@@ -150,7 +150,7 @@ echo "EXTERN(up_boot)" >>ld-locked.inc
answer=$(checkzero CONFIG_TASK_NAME_SIZE)
if [ "$answer" = n ]; then
- echo "EXTERN(up_boot)" >>ld-locked.inc
+ echo "EXTERN(arm_boot)" >>ld-locked.inc
fi
echo "EXTERN(dq_addfirst)" >>ld-locked.inc
diff --git a/configs/freedom-kl25z/src/kl_boardinitialize.c b/configs/freedom-kl25z/src/kl_boardinitialize.c
index a3036bd9075..2ab54047bef 100644
--- a/configs/freedom-kl25z/src/kl_boardinitialize.c
+++ b/configs/freedom-kl25z/src/kl_boardinitialize.c
@@ -1,6 +1,5 @@
/************************************************************************************
- * configs/freedom-kl25z/src/up_boot.c
- * arch/arm/src/board/up_boot.c
+ * configs/freedom-kl25z/src/kl_boardinitialize.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/configs/freedom-kl26z/src/kl_boardinitialize.c b/configs/freedom-kl26z/src/kl_boardinitialize.c
index 4d80f64591b..004274c6f62 100644
--- a/configs/freedom-kl26z/src/kl_boardinitialize.c
+++ b/configs/freedom-kl26z/src/kl_boardinitialize.c
@@ -1,5 +1,5 @@
/************************************************************************************
- * configs/freedom-kl26z/src/up_boot.c
+ * configs/freedom-kl26z/src/kl_boardinitialize.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/configs/mirtoo/README.txt b/configs/mirtoo/README.txt
index 799d77ccd0d..483e1d50a24 100644
--- a/configs/mirtoo/README.txt
+++ b/configs/mirtoo/README.txt
@@ -530,7 +530,7 @@ UART Usage
When mounted on the DTX1-4000L EV-kit1 board, serial output is avaiable through
an FT230X device via the FUNC0 and FUNC1 module outputs. If CONFIG_PIC32MX_UART2
- is enabled, the src/up_boot will configure the UART2 pins as follows:
+ is enabled, the src/pic32_boot will configure the UART2 pins as follows:
---------- ------ ----- ------ -------------------------
BOARD MODULE PIN SIGNAL NOTES
@@ -542,7 +542,7 @@ UART Usage
for UART2 if you are also debugging with the ICD3. In that case, you may need
to switch to UART1.
- If CONFIG_PIC32MX_UART1 is enabled, the src/up_boot will configure the UART
+ If CONFIG_PIC32MX_UART1 is enabled, the src/pic32_boot will configure the UART
pins as follows. This will support communictions (via an external RS-232
driver) through X3 pins 4 and 5:
diff --git a/configs/mirtoo/src/pic32_boot.c b/configs/mirtoo/src/pic32_boot.c
index 221377fd5ac..01d7b57a4b0 100644
--- a/configs/mirtoo/src/pic32_boot.c
+++ b/configs/mirtoo/src/pic32_boot.c
@@ -70,7 +70,7 @@
* Description:
* When mounted on the DTX1-4000L EV-kit1 board, serial output is avaiable through
* an FT230X device via the FUNC0 and FUNC1 module outputs. If CONFIG_PIC32MX_UART2
- * is enabled, the src/up_boot will configure the UART2 pins as follows.
+ * is enabled, the src/pic32_boot will configure the UART2 pins as follows.
*
* ---------- ------ ----- ------ -------------------------
* BOARD OUTPUT PIN SIGNAL NOTES
@@ -78,7 +78,7 @@
* FT230X RXD FUNC0 RPB11 U2RX UART2 RX (Also PGEC2)
* FT230X TXD FUNC1 RPB10 U2TX UART2 TX (Also PGED2)
*
- * If CONFIG_PIC32MX_UART1 is enabled, the src/up_boot will configure the UART
+ * If CONFIG_PIC32MX_UART1 is enabled, the src/pic32_boot will configure the UART
* pins as follows. This will support communictions (via an external RS-232
* driver) through X3 pins 4 and 5:
*
diff --git a/configs/nutiny-nuc120/src/nuc_boardinitialize.c b/configs/nutiny-nuc120/src/nuc_boardinitialize.c
index ef4ec1a7e84..add4e9290f6 100644
--- a/configs/nutiny-nuc120/src/nuc_boardinitialize.c
+++ b/configs/nutiny-nuc120/src/nuc_boardinitialize.c
@@ -1,6 +1,5 @@
/************************************************************************************
- * configs/nutiny-nuc120/src/up_boot.c
- * arch/arm/src/board/up_boot.c
+ * configs/nutiny-nuc120/src/nuc_boardinitialize.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/configs/pcduino-a10/nsh/pcduino-140107.patch b/configs/pcduino-a10/nsh/pcduino-140107.patch
index 50d4a0aca1a..1d0b6651844 100644
--- a/configs/pcduino-a10/nsh/pcduino-140107.patch
+++ b/configs/pcduino-a10/nsh/pcduino-140107.patch
@@ -2,7 +2,7 @@ diff --git a/nuttx/arch/arm/src/a1x/a1x_boot.c b/nuttx/arch/arm/src/a1x/a1x_boot
index 3cc6323..ad42790 100644
--- a/nuttx/arch/arm/src/a1x/a1x_boot.c
+++ b/nuttx/arch/arm/src/a1x/a1x_boot.c
-@@ -312,12 +312,14 @@ void up_boot(void)
+@@ -312,12 +312,14 @@ void arm_boot(void)
* for all IO regions (Including the vector region).
*/
@@ -17,7 +17,7 @@ index 3cc6323..ad42790 100644
a1x_vectormapping();
#endif /* CONFIG_ARCH_ROMPGTABLE */
-@@ -326,16 +328,19 @@ void up_boot(void)
+@@ -326,16 +328,19 @@ void arm_boot(void)
* arm_vector.S
*/
@@ -37,7 +37,7 @@ index 3cc6323..ad42790 100644
a1x_lowsetup();
/* Perform early serial initialization if we are going to use the serial
-@@ -343,6 +348,7 @@ void up_boot(void)
+@@ -343,6 +348,7 @@ void arm_boot(void)
*/
#ifdef USE_EARLYSERIALINIT
@@ -45,7 +45,7 @@ index 3cc6323..ad42790 100644
up_earlyserialinit();
#endif
-@@ -353,6 +359,7 @@ void up_boot(void)
+@@ -353,6 +359,7 @@ void arm_boot(void)
*/
#ifdef CONFIG_BUILD_PROTECTED
@@ -53,7 +53,7 @@ index 3cc6323..ad42790 100644
a1x_userspace();
#endif
-@@ -362,5 +369,7 @@ void up_boot(void)
+@@ -362,5 +369,7 @@ void arm_boot(void)
* - Configuration of board specific resources (PIOs, LEDs, etc).
*/
diff --git a/configs/pcduino-a10/scripts/sdram.ld b/configs/pcduino-a10/scripts/sdram.ld
index 414c408a4ac..b4eaeef8d7c 100644
--- a/configs/pcduino-a10/scripts/sdram.ld
+++ b/configs/pcduino-a10/scripts/sdram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/pcduino-a10/scripts/sdram.ld
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -49,7 +49,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -67,13 +68,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -86,7 +89,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -94,7 +98,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -102,7 +107,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld
index ef87268ff6f..f1134bcc926 100644
--- a/configs/sabre-6quad/scripts/dramboot.ld
+++ b/configs/sabre-6quad/scripts/dramboot.ld
@@ -55,7 +55,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -73,13 +74,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > ddr3
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > ddr3
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > ddr3
@@ -92,7 +95,10 @@ SECTIONS
} > ddr3
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ /* Uninitialized data */
+
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -100,7 +106,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > ddr3
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -108,6 +115,13 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > ddr3
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > ddr3
+
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
diff --git a/configs/sama5d2-xult/scripts/dramboot.ld b/configs/sama5d2-xult/scripts/dramboot.ld
index 0494ff0a911..e921c5e8aaf 100644
--- a/configs/sama5d2-xult/scripts/dramboot.ld
+++ b/configs/sama5d2-xult/scripts/dramboot.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d2-xult/scripts/dramboot.ld
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -54,7 +54,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -72,13 +73,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -91,7 +94,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -99,7 +103,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -107,7 +112,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d2-xult/scripts/gnu-elf.ld b/configs/sama5d2-xult/scripts/gnu-elf.ld
index d84460b4c05..7f35d218bc1 100644
--- a/configs/sama5d2-xult/scripts/gnu-elf.ld
+++ b/configs/sama5d2-xult/scripts/gnu-elf.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d2-xult/scripts/gnu-elf.ld
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -76,6 +76,15 @@ SECTIONS
_edata = . ;
}
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = . ;
+ *(.noinit*)
+ _enoinit = . ;
+ }
+
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
diff --git a/configs/sama5d2-xult/scripts/isram.ld b/configs/sama5d2-xult/scripts/isram.ld
index a170e022600..a5b1afe9a03 100644
--- a/configs/sama5d2-xult/scripts/isram.ld
+++ b/configs/sama5d2-xult/scripts/isram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d2-xult/scripts/isram.ld
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -69,7 +70,8 @@ SECTIONS
_etext = ABSOLUTE(.);
} > isram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
@@ -88,7 +90,8 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -96,7 +99,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > isram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -104,7 +108,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > isram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > isram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d2-xult/scripts/uboot.ld b/configs/sama5d2-xult/scripts/uboot.ld
index 66e524d9225..3ad820747d3 100644
--- a/configs/sama5d2-xult/scripts/uboot.ld
+++ b/configs/sama5d2-xult/scripts/uboot.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d2-xult/scripts/uboot.ld
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -55,7 +55,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -73,13 +74,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -92,7 +95,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -100,7 +104,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -108,7 +113,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3-xplained/scripts/ddram.ld b/configs/sama5d3-xplained/scripts/ddram.ld
index edb3f63a49e..9c3243d04e6 100644
--- a/configs/sama5d3-xplained/scripts/ddram.ld
+++ b/configs/sama5d3-xplained/scripts/ddram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3-xplained/scripts/ddram.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -55,7 +55,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -73,13 +74,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -92,7 +95,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -100,7 +104,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -108,7 +113,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3-xplained/scripts/gnu-elf.ld b/configs/sama5d3-xplained/scripts/gnu-elf.ld
index 88c53fe05f0..ffd6dc04b3d 100644
--- a/configs/sama5d3-xplained/scripts/gnu-elf.ld
+++ b/configs/sama5d3-xplained/scripts/gnu-elf.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3-xplained/scripts/gnu-elf.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -76,6 +76,15 @@ SECTIONS
_edata = . ;
}
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = . ;
+ *(.noinit*)
+ _enoinit = . ;
+ }
+
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
diff --git a/configs/sama5d3-xplained/scripts/isram.ld b/configs/sama5d3-xplained/scripts/isram.ld
index dae430c3081..847d3e58b30 100644
--- a/configs/sama5d3-xplained/scripts/isram.ld
+++ b/configs/sama5d3-xplained/scripts/isram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3-xplained/scripts/isram.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -69,13 +70,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > isram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > isram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > isram
@@ -88,7 +91,8 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -96,7 +100,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > isram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -104,7 +109,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > isram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > isram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3x-ek/scripts/ddram.ld b/configs/sama5d3x-ek/scripts/ddram.ld
index 8735df50a66..6376646ba2c 100644
--- a/configs/sama5d3x-ek/scripts/ddram.ld
+++ b/configs/sama5d3x-ek/scripts/ddram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/ddram.ld
*
- * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -55,7 +55,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -73,13 +74,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -92,7 +95,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -100,7 +104,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -108,7 +113,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3x-ek/scripts/gnu-elf.ld b/configs/sama5d3x-ek/scripts/gnu-elf.ld
index 82c9b37e2f1..6b77f5dffd2 100644
--- a/configs/sama5d3x-ek/scripts/gnu-elf.ld
+++ b/configs/sama5d3x-ek/scripts/gnu-elf.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/gnu-elf.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -76,6 +76,15 @@ SECTIONS
_edata = . ;
}
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = . ;
+ *(.noinit*)
+ _enoinit = . ;
+ }
+
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
diff --git a/configs/sama5d3x-ek/scripts/isram.ld b/configs/sama5d3x-ek/scripts/isram.ld
index 0dde103d990..c7c3ac1799a 100644
--- a/configs/sama5d3x-ek/scripts/isram.ld
+++ b/configs/sama5d3x-ek/scripts/isram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/isram.ld
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -69,13 +70,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > isram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > isram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > isram
@@ -88,7 +91,8 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -96,7 +100,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > isram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -104,7 +109,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > isram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > isram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3x-ek/scripts/nor-ddram.ld b/configs/sama5d3x-ek/scripts/nor-ddram.ld
index ecebee5930f..1787e05a194 100644
--- a/configs/sama5d3x-ek/scripts/nor-ddram.ld
+++ b/configs/sama5d3x-ek/scripts/nor-ddram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/nor-ddram.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -60,7 +60,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -78,13 +79,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > norflash
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > norflash
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > norflash
@@ -97,7 +100,8 @@ SECTIONS
} > norflash
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -107,7 +111,8 @@ SECTIONS
_eronly = LOADADDR(.data);
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -115,7 +120,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3x-ek/scripts/nor-isram.ld b/configs/sama5d3x-ek/scripts/nor-isram.ld
index c8681562e28..6d667f5e095 100644
--- a/configs/sama5d3x-ek/scripts/nor-isram.ld
+++ b/configs/sama5d3x-ek/scripts/nor-isram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/nor-isram.ld
*
- * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -56,7 +56,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -74,13 +75,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > norflash
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > norflash
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > norflash
@@ -93,7 +96,8 @@ SECTIONS
} > norflash
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -103,7 +107,8 @@ SECTIONS
_eronly = LOADADDR(.data);
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -111,7 +116,8 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > isram
- .ramfunc ALIGN(4): {
+ .ramfunc ALIGN(4):
+ {
_sramfuncs = ABSOLUTE(.);
*(.ramfunc .ramfunc.*)
_eramfuncs = ABSOLUTE(.);
@@ -119,7 +125,17 @@ SECTIONS
_framfuncs = LOADADDR(.ramfunc);
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > isram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d3x-ek/scripts/pg-sram.ld b/configs/sama5d3x-ek/scripts/pg-sram.ld
index 549802619fe..31c49abb347 100644
--- a/configs/sama5d3x-ek/scripts/pg-sram.ld
+++ b/configs/sama5d3x-ek/scripts/pg-sram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d3x-ek/scripts/pg-isram.ld
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -79,7 +79,8 @@ ENTRY(_stext)
SECTIONS
{
- .locked : {
+ .locked :
+ {
_slocked = ABSOLUTE(.);
*(.vectors)
up_head.o locked.r (.text .text.*)
@@ -95,7 +96,8 @@ SECTIONS
_elocked = ABSOLUTE(.);
} >locked
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
@@ -110,7 +112,8 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
- .paged : {
+ .paged :
+ {
_spaged = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
@@ -127,7 +130,8 @@ SECTIONS
_epaged = ABSOLUTE(.);
} > paged
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -135,14 +139,26 @@ SECTIONS
_edata = ABSOLUTE(.);
} > data AT > locked
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
_ebss = ABSOLUTE(.);
} > data
- /* Stabs debugging sections. */
+
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > data
+
+ /* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d4-ek/scripts/dramboot.ld b/configs/sama5d4-ek/scripts/dramboot.ld
index 4ca01c6b88f..2e19a34be30 100644
--- a/configs/sama5d4-ek/scripts/dramboot.ld
+++ b/configs/sama5d4-ek/scripts/dramboot.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d4-ek/scripts/dramboot.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -54,7 +54,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -72,13 +73,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -91,7 +94,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -99,7 +103,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -107,7 +112,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d4-ek/scripts/gnu-elf.ld b/configs/sama5d4-ek/scripts/gnu-elf.ld
index 6d402a750d7..6cab7801d10 100644
--- a/configs/sama5d4-ek/scripts/gnu-elf.ld
+++ b/configs/sama5d4-ek/scripts/gnu-elf.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d4-ek/scripts/gnu-elf.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -76,6 +76,15 @@ SECTIONS
_edata = . ;
}
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = . ;
+ *(.noinit*)
+ _enoinit = . ;
+ }
+
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
diff --git a/configs/sama5d4-ek/scripts/isram.ld b/configs/sama5d4-ek/scripts/isram.ld
index 85bc4dfc4f0..70689842f29 100644
--- a/configs/sama5d4-ek/scripts/isram.ld
+++ b/configs/sama5d4-ek/scripts/isram.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d4-ek/scripts/isram.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -51,7 +51,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -69,13 +70,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > isram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > isram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > isram
@@ -88,7 +91,8 @@ SECTIONS
} > isram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -96,7 +100,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > isram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -104,7 +109,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > isram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > isram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/sama5d4-ek/scripts/uboot.ld b/configs/sama5d4-ek/scripts/uboot.ld
index 530be22418e..2a76487ccf8 100644
--- a/configs/sama5d4-ek/scripts/uboot.ld
+++ b/configs/sama5d4-ek/scripts/uboot.ld
@@ -1,7 +1,7 @@
/****************************************************************************
* configs/sama5d4-ek/scripts/uboot.ld
*
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -55,7 +55,8 @@ ENTRY(_stext)
SECTIONS
{
- .text : {
+ .text :
+ {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
@@ -73,13 +74,15 @@ SECTIONS
_etext = ABSOLUTE(.);
} > sdram
- .init_section : {
+ .init_section :
+ {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > sdram
- .ARM.extab : {
+ .ARM.extab :
+ {
*(.ARM.extab*)
} > sdram
@@ -92,7 +95,8 @@ SECTIONS
} > sdram
PROVIDE_HIDDEN (__exidx_end = .);
- .data : {
+ .data :
+ {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
@@ -100,7 +104,8 @@ SECTIONS
_edata = ABSOLUTE(.);
} > sdram
- .bss : {
+ .bss :
+ {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
@@ -108,7 +113,17 @@ SECTIONS
_ebss = ABSOLUTE(.);
} > sdram
+ /* Uninitialized data */
+
+ .noinit :
+ {
+ _snoinit = ABSOLUTE(.);
+ *(.noinit*)
+ _enoinit = ABSOLUTE(.);
+ } > sdram
+
/* Stabs debugging sections. */
+
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
diff --git a/configs/stm32ldiscovery/src/stm32_boot.c b/configs/stm32ldiscovery/src/stm32_boot.c
index 375d9de3297..df34cb340a2 100644
--- a/configs/stm32ldiscovery/src/stm32_boot.c
+++ b/configs/stm32ldiscovery/src/stm32_boot.c
@@ -1,5 +1,5 @@
/************************************************************************************
- * configs/stm32ldiscovery/src/up_boot.c
+ * configs/stm32ldiscovery/src/stm32_boot.c
*
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/configs/teensy-lc/src/kl_boardinitialize.c b/configs/teensy-lc/src/kl_boardinitialize.c
index c99ef366731..119a2d4ca6c 100644
--- a/configs/teensy-lc/src/kl_boardinitialize.c
+++ b/configs/teensy-lc/src/kl_boardinitialize.c
@@ -1,5 +1,5 @@
/************************************************************************************
- * configs/teensy-lc/src/up_boot.c
+ * configs/teensy-lc/src/kl_boardinitialize.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h
index da9296af2d0..b2066b162a3 100644
--- a/include/nuttx/arch.h
+++ b/include/nuttx/arch.h
@@ -1644,7 +1644,7 @@ int up_timer_start(FAR const struct timespec *ts);
*
* Description:
* Return the TLS information structure for the currently executing thread.
- * When TLS is enabled, up_createstack() will align allocated stacks to
+ * When TLS is enabled, up_create_stack() will align allocated stacks to
* the TLS_STACK_ALIGN value. An instance of the following structure will
* be implicitly positioned at the "lower" end of the stack. Assuming a
* "push down" stack, this is at the "far" end of the stack (and can be
@@ -1722,6 +1722,51 @@ int up_cpu_index(void);
# define up_cpu_index() (0)
#endif
+/****************************************************************************
+ * Name: up_cpu_idlestack
+ *
+ * Description:
+ * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ * setup up stack-related information in the IDLE task's TCB. This
+ * function is always called before up_cpu_start(). This function is
+ * only called for the CPU's initial IDLE task; up_create_task is used for
+ * all normal tasks, pthreads, and kernel threads for all CPUs.
+ *
+ * The initial IDLE task is a special case because the CPUs can be started
+ * in different wans in different environments:
+ *
+ * 1. The CPU may already have been started and waiting in a low power
+ * state for up_cpu_start(). In this case, the IDLE thread's stack
+ * has already been allocated and is already in use. Here
+ * up_cpu_idlestack() only has to provide information about the
+ * already allocated stack.
+ *
+ * 2. The CPU may be disabled but started when up_cpu_start() is called.
+ * In this case, a new stack will need to be created for the IDLE
+ * thread and this function is then equivalent to:
+ *
+ * up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ *
+ * The following TCB fields must be initialized by this function:
+ *
+ * - adj_stack_size: Stack size after adjustment for hardware, processor,
+ * etc. This value is retained only for debug purposes.
+ * - stack_alloc_ptr: Pointer to allocated stack
+ * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of
+ * the stack pointer.
+ *
+ * Inputs:
+ * - cpu: CPU index that indicates which CPU the IDLE task is
+ * being created for.
+ * - tcb: The TCB of new CPU IDLE task
+ * - stack_size: The requested stack size for the IDLE task. At least
+ * this much must be allocated. This should be
+ * CONFIG_SMP_IDLETHREAD_STACKSIZE.
+ *
+ ****************************************************************************/
+
+int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size);
+
/****************************************************************************
* Name: up_cpu_start
*
@@ -1753,28 +1798,6 @@ int up_cpu_index(void);
int up_cpu_start(int cpu);
#endif
-/****************************************************************************
- * Name: up_cpu_initialize
- *
- * Description:
- * After the CPU has been started (via up_cpu_start()) the system will
- * call back into the architecture-specific code with this function on the
- * thread of execution of the newly started CPU. This gives the
- * architecture-specific a chance to perform ny initial, CPU-specific
- * initialize on that thread.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Zero on success; a negated errno value on failure.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_SMP
-int up_cpu_initialize(void);
-#endif
-
/****************************************************************************
* Name: up_cpu_pause
*
diff --git a/sched/init/os_smpstart.c b/sched/init/os_smpstart.c
index f613344b5f1..c8be9c1cb18 100644
--- a/sched/init/os_smpstart.c
+++ b/sched/init/os_smpstart.c
@@ -98,13 +98,7 @@ void os_idle_trampoline(void)
{
#ifdef CONFIG_SCHED_INSTRUMENTATION
FAR struct tcb_s *tcb = this_task();
-#endif
- /* Perform architecture-specific initialization for this CPU */
-
- up_cpu_initialize();
-
-#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Announce that the IDLE task has started */
sched_note_start(tcb);
@@ -209,8 +203,7 @@ int os_smp_start(void)
FAR struct tcb_s *tcb = current_task(cpu);
DEBUGASSERT(tcb != NULL);
- ret = up_create_stack(tcb, CONFIG_SMP_IDLETHREAD_STACKSIZE,
- TCB_FLAG_TTYPE_KERNEL);
+ ret = up_cpu_idlestack(cpu, tcb, CONFIG_SMP_IDLETHREAD_STACKSIZE);
if (ret < 0)
{
sdbg("ERROR: Failed to allocate stack for CPU%d\n", cpu);