Merge remote-tracking branch 'origin/nuttx-7.27'

arch/arm/src/imxrt/chip/imxrt_gpt.h

@@ -0,0 +1,182 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/chip/imxrt_gpt.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define IMXRT_GPT_CR_OFFSET                 0xc000  /* GPT Control Register */
+#define IMXRT_GPT_PR_OFFSET                 0xc004  /* GPT Prescaler Register */
+#define IMXRT_GPT_SR_OFFSET                 0xc008  /* GPT Status Register */
+#define IMXRT_GPT_IR_OFFSET                 0xc00c  /* GPT Interrupt Register */
+#define IMXRT_GPT_OCR1_OFFSET               0xc010  /* GPT Output Compare Register 1 */
+#define IMXRT_GPT_OCR2_OFFSET               0xc014  /* GPT Output Compare Register 2 */
+#define IMXRT_GPT_OCR3_OFFSET               0xc018  /* GPT Output Compare Register 3 */
+#define IMXRT_GPT_ICR1_OFFSET               0xc01c  /* GPT Input Capture Register 1 */
+#define IMXRT_GPT_ICR2_OFFSET               0xc020  /* GPT Input Capture Register 2 */
+#define IMXRT_GPT_CNT_OFFSET                0xc024  /* GPT Counter Register */
+
+/* Register addresses ***********************************************************************/
+
+#define IMXRT_GPT1_CR                       (IMXRT_GPT1_BASE + IMXRT_GPT1_CR_OFFSET)    /* GPT 1 Control Register */
+#define IMXRT_GPT1_PR                       (IMXRT_GPT1_BASE + IMXRT_GPT1_PR_OFFSET)    /* GPT 1 Prescaler Register */
+#define IMXRT_GPT1_SR                       (IMXRT_GPT1_BASE + IMXRT_GPT1_SR_OFFSET)    /* GPT 1 Status Register */
+#define IMXRT_GPT1_IR                       (IMXRT_GPT1_BASE + IMXRT_GPT1_IR_OFFSET)    /* GPT 1 Interrupt Register */
+#define IMXRT_GPT1_OCR1                     (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR1_OFFSET)  /* GPT 1 Output Compare Register 1 */
+#define IMXRT_GPT1_OCR2                     (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR2_OFFSET)  /* GPT 1 Output Compare Register 2 */
+#define IMXRT_GPT1_OCR3                     (IMXRT_GPT1_BASE + IMXRT_GPT1_OCR3_OFFSET)  /* GPT 1 Output Compare Register 3 */
+#define IMXRT_GPT1_ICR1                     (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR1_OFFSET)  /* GPT 1 Input Capture Register 1 */
+#define IMXRT_GPT1_ICR2                     (IMXRT_GPT1_BASE + IMXRT_GPT1_ICR2_OFFSET)  /* GPT 1 Input Capture Register 2 */
+#define IMXRT_GPT1_CNT                      (IMXRT_GPT1_BASE + IMXRT_GPT1_CNT_OFFSET)   /* GPT 1 Counter Register */
+#define IMXRT_GPT2_CR                       (IMXRT_GPT2_BASE + IMXRT_GPT2_CR_OFFSET)    /* GPT 2 Control Register */
+#define IMXRT_GPT2_PR                       (IMXRT_GPT2_BASE + IMXRT_GPT2_PR_OFFSET)    /* GPT 2 Prescaler Register */
+#define IMXRT_GPT2_SR                       (IMXRT_GPT2_BASE + IMXRT_GPT2_SR_OFFSET)    /* GPT 2 Status Register */
+#define IMXRT_GPT2_IR                       (IMXRT_GPT2_BASE + IMXRT_GPT2_IR_OFFSET)    /* GPT 2 Interrupt Register */
+#define IMXRT_GPT2_OCR1                     (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR1_OFFSET)  /* GPT 2 Output Compare Register 1 */
+#define IMXRT_GPT2_OCR2                     (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR2_OFFSET)  /* GPT 2 Output Compare Register 2 */
+#define IMXRT_GPT2_OCR3                     (IMXRT_GPT2_BASE + IMXRT_GPT2_OCR3_OFFSET)  /* GPT 2 Output Compare Register 3 */
+#define IMXRT_GPT2_ICR1                     (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR1_OFFSET)  /* GPT 2 Input Capture Register 1 */
+#define IMXRT_GPT2_ICR2                     (IMXRT_GPT2_BASE + IMXRT_GPT2_ICR2_OFFSET)  /* GPT 2 Input Capture Register 2 */
+#define IMXRT_GPT2_CNT                      (IMXRT_GPT2_BASE + IMXRT_GPT2_CNT_OFFSET)   /* GPT 2 Counter Register */
+
+/* GPT Control Register */
+
+/* Register Bit Definitions *********************************************************/
+
+#define GPT_CR_EN                  (1 << 0)   /* Bit: 0  GPT Enable. */
+#define GPT_CR_ENMOD               (1 << 1)   /* Bit: 1  GPT Enable mode. */
+#define GPT_CR_DBGEN               (1 << 2)   /* Bit: 2  GPT debug mode enable. */
+#define GPT_CR_WAITEN              (1 << 3)   /* Bit: 3  GPT Wait Mode enable. */
+#define GPT_CR_DOZEEN              (1 << 4)   /* Bit: 4  GPT Doze Mode Enable. */
+#define GPT_CR_STOPEN              (1 << 5)   /* Bit: 5  GPT Stop Mode enable. */
+#define GPT_CR_CLKSRC_SHIFT        (6)        /* Bits: 6-8  Clock Source select. */
+#define GPT_CR_CLKSRC_MASK         (7 << GPT_CR_CLKSRC_SHIFT)
+#  define GPT_CR_CLKSRC(n)         ((uint32_t)(n) << GPT_CR_CLKSRC_SHIFT)
+#  define GPT_CR_CLKSRC_NONE       (0 << GPT_CR_CLKSRC_SHIFT)  /* No clock */
+#  define GPT_CR_CLKSRC_IPG        (1 << GPT_CR_CLKSRC_SHIFT)  /* Peripheral Clock (ipg_clk) */
+#  define GPT_CR_CLKSRC_IPG_HFR    (2 << GPT_CR_CLKSRC_SHIFT)  /* High Frequency Reference Clock (ipg_clk_highfreq) */
+#  define GPT_CR_CLKSRC_EXT        (3 << GPT_CR_CLKSRC_SHIFT)  /* External Clock */
+#  define GPT_CR_CLKSRC_IPG_LFR    (4 << GPT_CR_CLKSRC_SHIFT)  /* Low Frequency Reference Clock (ipg_clk_32k) */
+#  define GPT_CR_CLKSRC_IPG_24M    (5 << GPT_CR_CLKSRC_SHIFT)  /* Crystal oscillator as Reference Clock (ipg_clk_24M) */
+#define GPT_CR_FRR                 (1 << 9)   /* Bit: 9  Free-Run or Restart mode. */
+#define GPT_CR_EN_24M              (1 << 10)  /* Bit: 10 Enable 24 MHz clock input from crystal. */
+                                              /* Bits: 11-14  Reserved */
+#define GPT_CR_SWR                 (1 << 15)  /* Bit: 15 Software reset. */
+#define GPT_CR_IM1_SHIFT           (16)       /* Bits: 16-17  See IM2 */
+#define GPT_CR_IM1_MASK            (3 << GPT_CR_IM1_SHIFT)
+#  define GPT_CR_IM1(n)            ((uint32_t)(n) << GPT_CR_IM1_SHIFT)
+#  define GPT_CR_IM1_DIS           (0 << GPT_CR_IM1_SHIFT)  /* Capture disabled */
+#  define GPT_CR_IM1_RISING        (1 << GPT_CR_IM1_SHIFT)  /* Capture on rising edge */
+#  define GPT_CR_IM1_FALLING       (2 << GPT_CR_IM1_SHIFT)  /* Capture on falling edge */
+#  define GPT_CR_IM1_BOTH          (3 << GPT_CR_IM1_SHIFT)  /* Capture on both edges */
+#define GPT_CR_IM2_SHIFT           (18)       /* Bits: 18-19  IM2 (bits 19-18, Input Capture Channel 2 operating mode) */
+#define GPT_CR_IM2_MASK            (3 << GPT_CR_IM2_SHIFT)
+#  define GPT_CR_IM2(n)            ((uint32_t)(n) << GPT_CR_IM2_SHIFT)
+#  define GPT_CR_IM2_DIS           (0 << GPT_CR_IM2_SHIFT)  /* Capture disabled */
+#  define GPT_CR_IM2_RISING        (1 << GPT_CR_IM2_SHIFT)  /* Capture on rising edge */
+#  define GPT_CR_IM2_FALLING       (2 << GPT_CR_IM2_SHIFT)  /* Capture on falling edge */
+#  define GPT_CR_IM2_BOTH          (3 << GPT_CR_IM2_SHIFT)  /* Capture on both edges */
+#define GPT_CR_OM1_SHIFT           (20)       /* Bits: 20-22  See OM3 */
+#define GPT_CR_OM1_MASK            (7 << GPT_CR_OM1_SHIFT)
+#  define GPT_CR_OM1(n)            ((uint32_t)(n) << GPT_CR_OM1_SHIFT)
+#  define GPT_CR_OM1_DIS           (0 << GPT_CR_OM1_SHIFT)  /* Output disconnected. No response on pin. */
+#  define GPT_CR_OM1_TOGGLE        (1 << GPT_CR_OM1_SHIFT)  /* Toggle output pin */
+#  define GPT_CR_OM1_CLEAR         (2 << GPT_CR_OM1_SHIFT)  /* Clear output pin */
+#  define GPT_CR_OM1_SET           (3 << GPT_CR_OM1_SHIFT)  /* Set output pin */
+#  define GPT_CR_OM1_PULSE         (4 << GPT_CR_OM1_SHIFT)  /* Generate an active low pulse */
+#define GPT_CR_OM2_SHIFT           (23)       /* Bits: 23-25  See OM3 */
+#define GPT_CR_OM2_MASK            (7 << GPT_CR_OM2_SHIFT)
+#  define GPT_CR_OM2(n)            ((uint32_t)(n) << GPT_CR_OM2_SHIFT)
+#  define GPT_CR_OM2_DIS           (0 << GPT_CR_OM2_SHIFT)  /* Output disconnected. No response on pin. */
+#  define GPT_CR_OM2_TOGGLE        (1 << GPT_CR_OM2_SHIFT)  /* Toggle output pin */
+#  define GPT_CR_OM2_CLEAR         (2 << GPT_CR_OM2_SHIFT)  /* Clear output pin */
+#  define GPT_CR_OM2_SET           (3 << GPT_CR_OM2_SHIFT)  /* Set output pin */
+#  define GPT_CR_OM2_PULSE         (4 << GPT_CR_OM2_SHIFT)  /* Generate an active low pulse */
+#define GPT_CR_OM3_SHIFT           (26)       /* Bits: 26-28  OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode. */
+#define GPT_CR_OM3_MASK            (7 << GPT_CR_OM3_SHIFT)
+#  define GPT_CR_OM3(n)            ((uint32_t)(n) << GPT_CR_OM3_SHIFT)
+#  define GPT_CR_OM3_DIS           (0 << GPT_CR_OM3_SHIFT)  /* Output disconnected. No response on pin. */
+#  define GPT_CR_OM3_TOGGLE        (1 << GPT_CR_OM3_SHIFT)  /* Toggle output pin */
+#  define GPT_CR_OM3_CLEAR         (2 << GPT_CR_OM3_SHIFT)  /* Clear output pin */
+#  define GPT_CR_OM3_SET           (3 << GPT_CR_OM3_SHIFT)  /* Set output pin */
+#  define GPT_CR_OM3_PULSE         (4 << GPT_CR_OM3_SHIFT)  /* Generate an active low pulse */
+#define GPT_CR_FO1                 (1 << 29)  /* Bit: 29 See F03 */
+#define GPT_CR_FO2                 (1 << 30)  /* Bit: 30 See F03 */
+#define GPT_CR_FO3                 (1 << 31)  /* Bit: 31 FO3 Force Output Compare Channel 3 */
+
+/* GPT Prescaler Register */
+
+#define GPT_PR_PRESCALER_SHIFT     (0)        /* Bits: 0-11  Prescaler bits. */
+#define GPT_PR_PRESCALER_MASK      (0xfff << GPT_PR_PRESCALER_SHIFT)
+#  define GPT_PR_PRESCALER(n)      ((uint32_t)(n) << GPT_PR_PRESCALER_SHIFT)
+#define GPT_PR_PRESCALER24M_SHIFT  (12)       /* Bits: 12-15  Prescaler bits. */
+#define GPT_PR_PRESCALER24M_MASK   (0xf << GPT_PR_PRESCALER24M_SHIFT)
+#  define GPT_PR_PRESCALER24M(n)   ((uint32_t)(n) << GPT_PR_PRESCALER24M_SHIFT)
+                                              /* Bits: 16-31  Reserved */
+
+/* GPT Status Register */
+
+#define GPT_SR_OF1                 (1 << 0)   /* Bit: 0  Output Compare 1 Flag*/
+#define GPT_SR_OF2                 (1 << 1)   /* Bit: 1  Output Compare 2 Flag*/
+#define GPT_SR_OF3                 (1 << 2)   /* Bit: 2  Output Compare 3 Flag */
+#define GPT_SR_IF1                 (1 << 3)   /* Bit: 3  Input capture 1 Flag */
+#define GPT_SR_IF2                 (1 << 4)   /* Bit: 4  Input capture 2 Flag */
+#define GPT_SR_ROV                 (1 << 5)   /* Bit: 5  Rollover Flag. */
+                                              /* Bits: 6-31  Reserved */
+
+/* GPT Interrupt Register */
+
+#define GPT_IR_OF1IE               (1 << 0)   /* Bit: 0  Output Compare 1 Interrupt Enable  */
+#define GPT_IR_OF2IE               (1 << 1)   /* Bit: 1  Output Compare 2 Interrupt Enable  */
+#define GPT_IR_OF3IE               (1 << 2)   /* Bit: 2  Output Compare 3 Interrupt Enable */
+#define GPT_IR_IF1IE               (1 << 3)   /* Bit: 3  Input capture 1 Interrupt Enable */
+#define GPT_IR_IF2IE               (1 << 4)   /* Bit: 4  Input capture 2 Interrupt Enable */
+#define GPT_IR_ROVIE               (1 << 5)   /* Bit: 5  Rollover Interrupt Enable. */
+                                              /* Bits: 6-31  Reserved */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H */

arch/arm/src/imxrt/chip/imxrt_pit.h

@@ -0,0 +1,131 @@
+/************************************************************************************
+ * arch/arm/src/imxrt/chip/imxrt_pit.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
+#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip/imxrt_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define IMXRT_PIT_MCR_OFFSET       0x0000 /* PIT Module Control Register */
+#define IMXRT_PIT_LTMR64H_OFFSET   0x00e0 /* PIT Upper Lifetime Timer Register */
+#define IMXRT_PIT_LTMR64L_OFFSET   0x00e4 /* PIT Lower Lifetime Timer Register */
+#define IMXRT_PIT_LDVAL0_OFFSET    0x0100 /* Timer Load Value Register */
+#define IMXRT_PIT_CVAL0_OFFSET     0x0104 /* Current Timer Value Register */
+#define IMXRT_PIT_TCTRL0_OFFSET    0x0108 /* Timer Control Register */
+#define IMXRT_PIT_TFLG0_OFFSET     0x010c /* Timer Flag Register */
+#define IMXRT_PIT_LDVAL1_OFFSET    0x0110 /* Timer Load Value Register */
+#define IMXRT_PIT_CVAL1_OFFSET     0x0114 /* Current Timer Value Register */
+#define IMXRT_PIT_TCTRL1_OFFSET    0x0118 /* Timer Control Register */
+#define IMXRT_PIT_TFLG1_OFFSET     0x011c /* Timer Flag Register */
+#define IMXRT_PIT_LDVAL2_OFFSET    0x0120 /* Timer Load Value Register */
+#define IMXRT_PIT_CVAL2_OFFSET     0x0124 /* Current Timer Value Register */
+#define IMXRT_PIT_TCTRL2_OFFSET    0x0128 /* Timer Control Register */
+#define IMXRT_PIT_TFLG2_OFFSET     0x012c /* Timer Flag Register */
+#define IMXRT_PIT_LDVAL3_OFFSET    0x0130 /* Timer Load Value Register */
+#define IMXRT_PIT_CVAL3_OFFSET     0x0134 /* Current Timer Value Register */
+#define IMXRT_PIT_TCTRL3_OFFSET    0x0138 /* Timer Control Register */
+#define IMXRT_PIT_TFLG3_OFFSET     0x013c /* Timer Flag Register */
+
+/* Register Addresses ***************************************************************/
+
+#define IMXRT_PIT_MCR              (IMXRT_PIT_BASE+IMXRT_PIT_MCR_OFFSET)
+#define IMXRT_PIT_LTMR64H          (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64H_OFFSET)
+#define IMXRT_PIT_LTMR64L          (IMXRT_PIT_BASE+IMXRT_PIT_LTMR64L_OFFSET)
+#define IMXRT_PIT_LDVAL0           (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL0_OFFSET)
+#define IMXRT_PIT_CVAL0            (IMXRT_PIT_BASE+IMXRT_PIT_CVAL0_OFFSET)
+#define IMXRT_PIT_TCTRL0           (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL0_OFFSET)
+#define IMXRT_PIT_TFLG0            (IMXRT_PIT_BASE+IMXRT_PIT_TFLG0_OFFSET)
+#define IMXRT_PIT_LDVAL1           (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL1_OFFSET)
+#define IMXRT_PIT_CVAL1            (IMXRT_PIT_BASE+IMXRT_PIT_CVAL1_OFFSET)
+#define IMXRT_PIT_TCTRL1           (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL1_OFFSET)
+#define IMXRT_PIT_TFLG1            (IMXRT_PIT_BASE+IMXRT_PIT_TFLG1_OFFSET)
+#define IMXRT_PIT_LDVAL2           (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL2_OFFSET)
+#define IMXRT_PIT_CVAL2            (IMXRT_PIT_BASE+IMXRT_PIT_CVAL2_OFFSET)
+#define IMXRT_PIT_TCTRL2           (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL2_OFFSET)
+#define IMXRT_PIT_TFLG2            (IMXRT_PIT_BASE+IMXRT_PIT_TFLG2_OFFSET)
+#define IMXRT_PIT_LDVAL3           (IMXRT_PIT_BASE+IMXRT_PIT_LDVAL3_OFFSET)
+#define IMXRT_PIT_CVAL3            (IMXRT_PIT_BASE+IMXRT_PIT_CVAL3_OFFSET)
+#define IMXRT_PIT_TCTRL3           (IMXRT_PIT_BASE+IMXRT_PIT_TCTRL3_OFFSET)
+#define IMXRT_PIT_TFLG3            (IMXRT_PIT_BASE+IMXRT_PIT_TFLG3_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* PIT Module Control Register */
+
+#define PIT_MCR_FRZ                (1 << 0)  /* Bit 0:  Freeze */
+#define PIT_MCR_MDIS               (1 << 1)  /* Bit 1:  Module Disable */
+                                             /* Bits 2-31: Reserved */
+
+/* Timer Load Value Register (32-bit Timer Start Value Bits) */
+/* Current Timer Value Register (32-bit Current Timer Value) */
+
+/* Timer Control Register */
+
+#define PIT_TCTRL_TEN              (1 << 0)  /* Bit 0:  Timer Enable Bit */
+#define PIT_TCTRL_TIE              (1 << 1)  /* Bit 1:  Timer Interrupt Enable Bit */
+                                             /* Bits 2-31: Reserved */
+#define PIT_TCTRL_CHN              (1 << 2)  /* Bit 2:  Chain Mode */
+                                             /* Bits 3-31: Reserved */
+
+/* Timer Flag Register */
+
+#define PIT_TFLG_TIF               (1 << 0)  /* Bit 0:  Timer Interrupt Flag */
+                                             /* Bits 1-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H */

drivers/input/button_upper.c

@@ -198,7 +198,7 @@ static inline int btn_takesem(sem_t *sem)
 #if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void btn_enable(FAR struct btn_upperhalf_s *priv)
 {
-  FAR const struct btn_lowerhalf_s *lower = priv->bu_lower;
+  FAR const struct btn_lowerhalf_s *lower;
   FAR struct btn_open_s *opriv;
   btn_buttonset_t press;
   btn_buttonset_t release;
@@ -280,7 +280,7 @@ static void btn_interrupt(FAR const struct btn_lowerhalf_s *lower,
 
 static void btn_sample(FAR struct btn_upperhalf_s *priv)
 {
-  FAR const struct btn_lowerhalf_s *lower = priv->bu_lower;
+  FAR const struct btn_lowerhalf_s *lower;
   FAR struct btn_open_s *opriv;
   btn_buttonset_t sample;
 #if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)

libs/libc/netdb/Kconfig

@@ -54,13 +54,6 @@ menuconfig NETDB_DNSCLIENT
 
 if NETDB_DNSCLIENT
 
-config NETDB_DNSCLIENT_RECV_TIMEOUT
-	int "DNS receive tiemout"
-	default 30
-	---help---
-		This the timeout value when DNS receive response after
-		dns_send_query, unit: seconds
-
 config NETDB_DNSCLIENT_ENTRIES
 	int "Number of DNS resolver entries"
 	default 0 if DEFAULT_SMALL
@@ -109,6 +102,19 @@ config NETDB_DNSCLIENT_MAXRESPONSE
 		can be received by the DNS resolver.  The default is 96 but may
 		need to be larger on enterprise networks (perhaps 176).
 
+config NETDB_DNSCLIENT_RECV_TIMEOUT
+	int "DNS receive timeout"
+	default 30
+	---help---
+		This is the timeout value when DNS receives response after
+		dns_send_query, unit: seconds
+
+config NETDB_DNSCLIENT_RETRIES
+	int "Number of retries for DNS request"
+	default 3
+	---help---
+		This setting determines how many times resolver retries request
+		until failing.
 
 config NETDB_RESOLVCONF
 	bool "DNS resolver file support"

libs/libc/netdb/lib_dnsquery.c

@@ -63,10 +63,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-/* The maximum number of retries when asking for a name */
-
-#define MAX_RETRIES      8
-
 /* Buffer sizes
  *
  * The SEND_BUFFER_SIZE depends the configured DNS name size,
@@ -172,7 +168,7 @@ static FAR uint8_t *dns_parse_name(FAR uint8_t *query, FAR uint8_t *queryend)
 static int dns_send_query(int sd, FAR const char *name,
                           FAR union dns_server_u *uaddr, uint16_t rectype)
 {
-  register FAR struct dns_header_s *hdr;
+  FAR struct dns_header_s *hdr;
   FAR uint8_t *dest;
   FAR uint8_t *nptr;
   FAR const char *src;
@@ -192,11 +188,11 @@ static int dns_send_query(int sd, FAR const char *name,
   /* Initialize the request header */
 
   hdr               = (FAR struct dns_header_s *)buffer;
-  memset(hdr, 0, sizeof(struct dns_header_s));
+  memset(hdr, 0, sizeof(*hdr));
   hdr->id           = htons(seqno);
   hdr->flags1       = DNS_FLAG1_RD;
   hdr->numquestions = HTONS(1);
-  dest              = buffer + 12;
+  dest              = buffer + sizeof(*hdr);
 
   /* Convert hostname into suitable query format. */
 
@@ -294,7 +290,7 @@ static int dns_recv_response(int sd, FAR struct sockaddr *addr,
       return errcode;
     }
 
-  if (ret < 12)
+  if (ret < sizeof(*hdr))
     {
       /* DNS header can't fit in received data */
 
@@ -491,7 +487,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
 
   /* Loop while receive timeout errors occur and there are remaining retries */
 
-  for (retries = 0; retries < 3; retries++)
+  for (retries = 0; retries < CONFIG_NETDB_DNSCLIENT_RETRIES; retries++)
     {
 #ifdef CONFIG_NET_IPv4
       /* Is this an IPv4 address? */
@@ -503,7 +499,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           if (addrlen < sizeof(struct sockaddr_in))
             {
               /* Return zero to skip this address and try the next
-               * namserver address in resolv.conf.
+               * nameserver address in resolv.conf.
                */
 
               nerr("ERROR: Invalid IPv4 address size: %d\n", addrlen);
@@ -519,7 +515,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           if (ret < 0)
             {
               /* Return zero to skip this address and try the next
-               * namserver address in resolv.conf.
+               * nameserver address in resolv.conf.
                */
 
               nerr("ERROR: IPv4 dns_send_query failed: %d\n", ret);
@@ -563,7 +559,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           else if (ret != -EAGAIN)
             {
               /* Some failure other than receive timeout occurred.  Return
-               * zero to skip this address and try the next namserver
+               * zero to skip this address and try the next nameserver
                * address in resolv.conf.
                */
 
@@ -575,7 +571,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
 #endif /* CONFIG_NET_IPv4 */
 
 #ifdef CONFIG_NET_IPv6
-      /* Is this an IPv4 address? */
+      /* Is this an IPv6 address? */
 
       if (query->addr->sa_family == AF_INET6)
         {
@@ -584,7 +580,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           if (addrlen < sizeof(struct sockaddr_in6))
             {
               /* Return zero to skip this address and try the next
-               * namserver address in resolv.conf.
+               * nameserver address in resolv.conf.
                */
 
               nerr("ERROR: Invalid IPv6 address size: %d\n", addrlen);
@@ -600,7 +596,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           if (ret < 0)
             {
               /* Return zero to skip this address and try the next
-               * namserver address in resolv.conf.
+               * nameserver address in resolv.conf.
                */
 
               nerr("ERROR: IPv6 dns_send_query failed: %d\n", ret);
@@ -644,7 +640,7 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
           else if (ret != -EAGAIN)
             {
               /* Some failure other than receive timeout occurred.  Return
-               * zero to skip this address and try the next namserver
+               * zero to skip this address and try the next nameserver
                * address in resolv.conf.
                */
 
@@ -663,9 +659,9 @@ static int dns_query_callback(FAR void *arg, FAR struct sockaddr *addr,
         }
     }
 
-  /* We tried three times and could not communicate with this nameserver.
+  /* We tried and could not communicate with this nameserver. Perhaps it
-   * Perhaps it is down?  Return zero to continue with the next address
+   * is down?  Return zero to continue with the next address in the
-   * in the resolv.conf file.
+   * resolv.conf file.
    */
 
   query->result = -ETIMEDOUT;

libs/libc/netdb/lib_gethostbynamer.c

@@ -352,6 +352,7 @@ static int lib_localhost(FAR const char *name, FAR struct hostent *host,
  ****************************************************************************/
 
 #ifdef CONFIG_NETDB_DNSCLIENT
+#if CONFIG_NETDB_DNSCLIENT_ENTRIES > 0
 static int lib_find_answer(FAR const char *name, FAR struct hostent *host,
                            FAR char *buf, size_t buflen)
 {
@@ -443,6 +444,7 @@ static int lib_find_answer(FAR const char *name, FAR struct hostent *host,
   host->h_name = ptr;
   return OK;
 }
+#endif
 #endif /* CONFIG_NETDB_DNSCLIENT */
 
 /****************************************************************************