diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h
index 55014618f23..630a4526311 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h
@@ -48,6 +48,8 @@
 #include "chip.h"
 #include "hardware/stm32_pwr.h"
 
+#ifdef CONFIG_STM32F0L0G0_PWR
+
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
@@ -234,4 +236,5 @@ void stm32_pwr_disablepvd(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32F0L0G0_PWR */
 #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c
index a3647a8b940..02c64f58fc0 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.c
@@ -63,6 +63,7 @@
 #    error RNG requires CLK48 enabled
 #  endif
 #endif
+
 #ifdef CONFIG_STM32F0L0G0_USB
 #  ifndef STM32_USE_CLK48
 #    error USB requires CLK48 enabled
diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
index ea363448200..9d39a606680 100644
--- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
+++ b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c
@@ -338,7 +338,6 @@ void stm32_pwr_setvos(uint16_t vos)
     {
     }
 }
-#endif
 
 /****************************************************************************
  * Name: stm32_pwr_setpvd
@@ -359,7 +358,6 @@ void stm32_pwr_setvos(uint16_t vos)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
 void stm32_pwr_setpvd(uint16_t pls)
 {
   uint16_t regval;
diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
index 7d50ea03c70..b944b838882 100644
--- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
@@ -447,7 +447,9 @@ static void stm32_stdclockconfig(void)
 #if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
   uint16_t pwrcr;
 #endif
+#ifdef CONFIG_STM32F0L0G0_PWR
   uint32_t pwr_vos;
+#endif
   uint32_t flash_ws;
 
   /* Enable PWR clock from APB1 to give access to PWR_CR register */
@@ -482,7 +484,9 @@ static void stm32_stdclockconfig(void)
 
   if (STM32_SYSCLK_FREQUENCY > 16000000)
     {
+#ifdef CONFIG_STM32F0L0G0_PWR
       pwr_vos = PWR_CR1_VOS_RANGE1;
+#endif
 
       if (STM32_HCLK_FREQUENCY <= 24000000)
         {
@@ -499,7 +503,9 @@ static void stm32_stdclockconfig(void)
     }
   else
     {
+#ifdef CONFIG_STM32F0L0G0_PWR
       pwr_vos = PWR_CR1_VOS_RANGE2;
+#endif
 
       if (STM32_HCLK_FREQUENCY <= 8000000)
         {
@@ -511,7 +517,9 @@ static void stm32_stdclockconfig(void)
         }
     }
 
+#ifdef CONFIG_STM32F0L0G0_PWR
   stm32_pwr_setvos(pwr_vos);
+#endif
 
 #if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
   /* If RTC / LCD selects HSE as clock source, the RTC prescaler
diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig
index 7b3b1ac0e6e..9a72415a70a 100644
--- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig
+++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_EXAMPLES_HELLO=y
@@ -48,6 +47,7 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_STM32F0L0G0_PWR=y
 CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0