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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3499 42af7a65-404d-4744-a932-0658087f49c3
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@@ -1685,4 +1685,7 @@
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} >sram
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} >sram
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+ __exidx_end = ABSOLUTE(.);
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+ __exidx_end = ABSOLUTE(.);
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* arch/arm/src/lpc17xx: Correct some typos/bugs in configuration of LPC17xx
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UART2 and UART3.
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@@ -115,7 +115,7 @@
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#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
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#define LPC17_IRQ_I2C0 (LPC17_IRQ_EXTINT+10) /* I2C0 SI (state change) */
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#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
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#define LPC17_IRQ_I2C1 (LPC17_IRQ_EXTINT+11) /* I2C1 SI (state change) */
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#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
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#define LPC17_IRQ_I2C2 (LPC17_IRQ_EXTINT+12) /* I2C2 SI (state change) */
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#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
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#define LPC17_IRQ_SPIF (LPC17_IRQ_EXTINT+13) /* SPI SPI Interrupt Flag (SPIF)
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* Mode Fault (MODF) */
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* Mode Fault (MODF) */
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#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
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#define LPC17_IRQ_SSP0 (LPC17_IRQ_EXTINT+14) /* SSP0 Tx FIFO half empty of SSP0
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* Rx FIFO half full of SSP0
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* Rx FIFO half full of SSP0
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@@ -1,7 +1,7 @@
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/****************************************************************************
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_serial.c
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* arch/arm/src/lpc17xx/lpc17_serial.c
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*
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@@ -595,7 +595,7 @@ static inline uint32_t lpc17_uartcclkdiv(uint32_t baud)
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}
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}
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/************************************************************************************
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/************************************************************************************
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* Name: lpc17_uart0config, uart1config, uart2config, nad uart3config
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* Name: lpc17_uart0config, uart1config, uart2config, and uart3config
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*
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*
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* Descrption:
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* Descrption:
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* Configure the UART. UART0/1/2/3 peripherals are configured using the following
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* Configure the UART. UART0/1/2/3 peripherals are configured using the following
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@@ -1283,6 +1283,7 @@ void up_earlyserialinit(void)
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#endif
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#endif
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up_disableuartint(&g_uart0priv, NULL);
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up_disableuartint(&g_uart0priv, NULL);
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#endif
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#endif
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#ifdef CONFIG_LPC17_UART1
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#ifdef CONFIG_LPC17_UART1
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g_uart1priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD);
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g_uart1priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART1_BAUD);
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#ifndef CONFIG_UART1_SERIAL_CONSOLE
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#ifndef CONFIG_UART1_SERIAL_CONSOLE
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@@ -1290,6 +1291,7 @@ void up_earlyserialinit(void)
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#endif
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#endif
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up_disableuartint(&g_uart1priv, NULL);
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up_disableuartint(&g_uart1priv, NULL);
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#endif
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#endif
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#ifdef CONFIG_LPC17_UART2
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#ifdef CONFIG_LPC17_UART2
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g_uart2priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD);
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g_uart2priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART2_BAUD);
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#ifndef CONFIG_UART2_SERIAL_CONSOLE
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#ifndef CONFIG_UART2_SERIAL_CONSOLE
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@@ -1297,6 +1299,7 @@ void up_earlyserialinit(void)
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#endif
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#endif
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up_disableuartint(&g_uart2priv, NULL);
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up_disableuartint(&g_uart2priv, NULL);
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#endif
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#endif
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#ifdef CONFIG_LPC17_UART3
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#ifdef CONFIG_LPC17_UART3
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g_uart3priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD);
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g_uart3priv.cclkdiv = lpc17_uartcclkdiv(CONFIG_UART3_BAUD);
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#ifndef CONFIG_UART3_SERIAL_CONSOLE
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#ifndef CONFIG_UART3_SERIAL_CONSOLE
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@@ -538,6 +538,24 @@ selected as follow:
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Where <subdir> is one of the following:
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Where <subdir> is one of the following:
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nsh:
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Configures the NuttShell (nsh) located at examples/nsh. The
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Configuration enables both the serial and telnet NSH interfaces.
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Support for the board's SPI-based MicroSD card is included
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(but not passing tests as of this writing).
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ostest:
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ostest:
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This configuration directory, performs a simple OS test using
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This configuration directory, performs a simple OS test using
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examples/ostest.
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examples/ostest.
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NOTE: The OSTest runs on the LPCXpresso if it is not installed
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on the base board (using an add-on MAX232 RS232 driver connected
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to:
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P0[0]/RD1/TXD3/SDA1 J6-9
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P0[1]/TD1/RXD3/SCL J6-10
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I suspect that this test does not run on with the base board
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attached because OSTest blasts out a lot of serial data and
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overruns the FTDI chip before it has a chance to establish the
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connection with the host.
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