mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 16:50:55 +08:00
Add support for STM32L152CC, STM32L152RC and STM32L152VC. Update some bits and comments for other STM32L1 parts in chip.h
This commit is contained in:
Juha Niskanen
committed by
Gregory Nutt
Gregory Nutt
parent
e631ee4582
commit
9d0ecedf7d
@@ -108,7 +108,7 @@
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# define STM32_NLCD 0 /* No LCD */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 16-channels */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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@@ -228,10 +228,10 @@
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x16 */
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# define STM32_NLCD 1 /* LCD 4x18 */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 16-channels */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */
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@@ -310,7 +310,7 @@
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 24-channels */
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@@ -322,6 +322,46 @@
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152CC)
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# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
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# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
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* and STM32L15xxx */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# define CONFIG_STM32_MEDIUMPLUSDENSITY 1 /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x18 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 37 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 14-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
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# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
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# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
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@@ -336,6 +376,7 @@
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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@@ -349,13 +390,53 @@
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
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# define STM32_NLCD 1 /* LCD 4x32, 8x28 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 24-channels */
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# define STM32_NGPIO 51 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 21-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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#elif defined(CONFIG_ARCH_CHIP_STM32L152VC)
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# define CONFIG_STM32_STM32L15XX 1 /* STM32L151xx and STM32L152xx family */
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# define CONFIG_STM32_ENERGYLITE 1 /* STM32L EnergyLite family */
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# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
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* and STM32L15xxx */
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# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# define CONFIG_STM32_MEDIUMPLUSDENSITY 1 /* STM32L15xxC w/ 32/256 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
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# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */
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# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-E,H */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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@@ -375,6 +456,7 @@
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 1 /* FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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@@ -389,13 +471,13 @@
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 0 /* No CAN */
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# define STM32_NSDIO 1 /* SDIO */
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# define STM32_NLCD 1 /* LCD 4x44, 8x40*/
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# define STM32_NLCD 1 /* LCD 4x44, 8x40 */
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 115 /* GPIOA-G,H */
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# define STM32_NADC 1 /* ADC1, 24-channels */
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# define STM32_NADC 1 /* ADC1, 40-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */
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# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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@@ -415,6 +497,7 @@
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
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# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
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# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* No FSMC */
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# define STM32_NATIM 0 /* No advanced timers */
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@@ -433,8 +516,8 @@
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# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */
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# define STM32_NGPIO 83 /* GPIOA-G,H */
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# define STM32_NADC 1 /* ADC1, up to 40-channels (medium+ and high density). See for more information RM0038 Reference manual */
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# define STM32_NDAC 1 /* DAC 1, 2 channels. See for more information RM0038 Reference manual */
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# define STM32_NADC 1 /* ADC1, 25-channels */
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# define STM32_NDAC 2 /* DAC 1-2, 2 channels */
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/* (2) Comparators */
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# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */
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# define STM32_NCRC 1 /* CRC */
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