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EFM32: More USB register name corrections. Still incomplete

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This commit is contained in:
Gregory Nutt
2014-11-12 09:46:58 -06:00
parent 79cb947879
commit 9d0eb576c7
3 changed files with 37 additions and 36 deletions
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arch/arm/src/efm32/chip/efm32_usb.h
+1
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@@ -846,6 +846,7 @@
#define _USB_GUSBCFG_USBTRDTIM_MASK 0x3c00UL /* Bit mask for USB_USBTRDTIM */ #define _USB_GUSBCFG_USBTRDTIM_MASK 0x3c00UL /* Bit mask for USB_USBTRDTIM */
#define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /* Mode DEFAULT for USB_GUSBCFG */ #define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /* Mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GUSBCFG */ #define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /* Shifted mode DEFAULT for USB_GUSBCFG */
#define USB_GUSBCFG_USBTRDTIM(n) ((uint32_t)(n) << 10) /* Variable setting for USB_GUSBCFG */
#define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /* TermSel DLine Pulsing Selection (device only) */ #define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /* TermSel DLine Pulsing Selection (device only) */
#define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /* Shift value for USB_TERMSELDLPULSE */ #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /* Shift value for USB_TERMSELDLPULSE */
#define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /* Bit mask for USB_TERMSELDLPULSE */ #define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /* Bit mask for USB_TERMSELDLPULSE */
arch/arm/src/efm32/efm32_usbdev.c
+17 -17
View File
@@ -3116,7 +3116,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
/* Disable the Rx status queue level interrupt */ /* Disable the Rx status queue level interrupt */
regval = efm32_getreg(EFM32_USB_GINTMSK); regval = efm32_getreg(EFM32_USB_GINTMSK);
regval &= ~USB_GINTMSK_RXFLVL; regval &= ~USB_GINTMSK_RXFLVLMSK;
efm32_putreg(regval, EFM32_USB_GINTMSK); efm32_putreg(regval, EFM32_USB_GINTMSK);
/* Get the status from the top of the FIFO */ /* Get the status from the top of the FIFO */
@@ -3280,8 +3280,8 @@ static inline void efm32_enuminterrupt(FAR struct efm32_usbdev_s *priv)
/* Set USB turn-around time for the full speed device with internal PHY interface. */ /* Set USB turn-around time for the full speed device with internal PHY interface. */
regval = efm32_getreg(EFM32_USB_GUSBCFG); regval = efm32_getreg(EFM32_USB_GUSBCFG);
regval &= ~_USB_GUSBCFG_TRDT_MASK; regval &= ~_USB_GUSBCFG_USBTRDTIM_MASK;
regval |= USB_GUSBCFG_TRDT(5); regval |= USB_GUSBCFG_USBTRDTIM(5);
efm32_putreg(regval, EFM32_USB_GUSBCFG); efm32_putreg(regval, EFM32_USB_GUSBCFG);
} }
@@ -3533,22 +3533,22 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
* interrupt is pending on one of the OUT endpoints of the core. * interrupt is pending on one of the OUT endpoints of the core.
*/ */
if ((regval & USB_GINTSTS_OEP) != 0) if ((regval & USB_GINTSTS_OEPINT) != 0)
{ {
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT), (uint16_t)regval); usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPOUT), (uint16_t)regval);
efm32_epout_interrupt(priv); efm32_epout_interrupt(priv);
efm32_putreg(USB_GINTSTS_OEP, EFM32_USB_GINTSTS); efm32_putreg(USB_GINTSTS_OEPINT, EFM32_USB_GINTSTS);
} }
/* IN endpoint interrupt. The core sets this bit to indicate that /* IN endpoint interrupt. The core sets this bit to indicate that
* an interrupt is pending on one of the IN endpoints of the core. * an interrupt is pending on one of the IN endpoints of the core.
*/ */
if ((regval & USB_GINTSTS_IEP) != 0) if ((regval & USB_GINTSTS_IEPINT) != 0)
{ {
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN), (uint16_t)regval); usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_EPIN), (uint16_t)regval);
efm32_epin_interrupt(priv); efm32_epin_interrupt(priv);
efm32_putreg(USB_GINTSTS_IEP, EFM32_USB_GINTSTS); efm32_putreg(USB_GINTSTS_IEPINT, EFM32_USB_GINTSTS);
} }
/* Host/device mode mismatch error interrupt */ /* Host/device mode mismatch error interrupt */
@@ -3563,11 +3563,11 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
/* Resume/remote wakeup detected interrupt */ /* Resume/remote wakeup detected interrupt */
if ((regval & USB_GINTSTS_WKUP) != 0) if ((regval & USB_GINTSTS_WKUPINT) != 0)
{ {
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_WAKEUP), (uint16_t)regval); usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_WAKEUP), (uint16_t)regval);
efm32_resumeinterrupt(priv); efm32_resumeinterrupt(priv);
efm32_putreg(USB_GINTSTS_WKUP, EFM32_USB_GINTSTS); efm32_putreg(USB_GINTSTS_WKUPINT, EFM32_USB_GINTSTS);
} }
/* USB suspend interrupt */ /* USB suspend interrupt */
@@ -3616,11 +3616,11 @@ static int efm32_usbinterrupt(int irq, FAR void *context)
/* Enumeration done interrupt */ /* Enumeration done interrupt */
if ((regval & USB_GINTSTS_ENUMDNE) != 0) if ((regval & USB_GINTSTS_ENUMDONE) != 0)
{ {
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_ENUMDNE), (uint16_t)regval); usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_ENUMDNE), (uint16_t)regval);
efm32_enuminterrupt(priv); efm32_enuminterrupt(priv);
efm32_putreg(USB_GINTSTS_ENUMDNE, EFM32_USB_GINTSTS); efm32_putreg(USB_GINTSTS_ENUMDONE, EFM32_USB_GINTSTS);
} }
/* Incomplete isochronous IN transfer interrupt. When the core finds /* Incomplete isochronous IN transfer interrupt. When the core finds
@@ -3782,19 +3782,19 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
switch (maxpacket) switch (maxpacket)
{ {
case 8: case 8:
mpsiz = USB_DOEP0CTL_MPS_8; mpsiz = USB_DOEP0CTL_MPS_8B;
break; break;
case 16: case 16:
mpsiz = USB_DOEP0CTL_MPS_16; mpsiz = USB_DOEP0CTL_MPS_16B;
break; break;
case 32: case 32:
mpsiz = USB_DOEP0CTL_MPS_32; mpsiz = USB_DOEP0CTL_MPS_32B;
break; break;
case 64: case 64:
mpsiz = USB_DOEP0CTL_MPS_64; mpsiz = USB_DOEP0CTL_MPS_64B;
break; break;
default: default:
@@ -5241,8 +5241,8 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
/* Force Device Mode */ /* Force Device Mode */
regval = efm32_getreg(EFM32_USB_GUSBCFG); regval = efm32_getreg(EFM32_USB_GUSBCFG);
regval &= ~USB_GUSBCFG_FHMOD; regval &= ~_USB_GUSBCFG_FORCEHSTMODE_MASK;
regval |= USB_GUSBCFG_FDMOD; regval |= USB_GUSBCFG_FORCEDEVMODE;
efm32_putreg(regval, EFM32_USB_GUSBCFG); efm32_putreg(regval, EFM32_USB_GUSBCFG);
up_mdelay(50); up_mdelay(50);
arch/arm/src/efm32/efm32_usbhost.c
+19 -19
View File
@@ -809,7 +809,7 @@ static void efm32_chan_configure(FAR struct efm32_usbhost_s *priv, int chidx)
/* Make sure host channel interrupts are enabled. */ /* Make sure host channel interrupts are enabled. */
efm32_modifyreg(EFM32_USB_GINTMSK, 0, USB_GINTMSK_HCHINTMSK); efm32_modifyreg(EFM32_USB_GINTMSK, 0, USB_GINTMSK_PTXFEMPMSKHCHINTMSK);
/* Program the HCCHAR register */ /* Program the HCCHAR register */
@@ -2329,7 +2329,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Disable the RxFIFO non-empty interrupt */ /* Disable the RxFIFO non-empty interrupt */
intmsk = efm32_getreg(EFM32_USB_GINTMSK); intmsk = efm32_getreg(EFM32_USB_GINTMSK);
intmsk &= ~USB_GINTMSK_RXFLVLMSK; intmsk &= ~USB_GINTMSK_PTXFEMPMSKRXFLVLMSK;
efm32_putreg(EFM32_USB_GINTMSK, intmsk); efm32_putreg(EFM32_USB_GINTMSK, intmsk);
/* Read and pop the next status from the Rx FIFO */ /* Read and pop the next status from the Rx FIFO */
@@ -2402,7 +2402,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Re-enable the RxFIFO non-empty interrupt */ /* Re-enable the RxFIFO non-empty interrupt */
intmsk |= USB_GINTMSK_RXFLVLMSK; intmsk |= USB_GINTMSK_PTXFEMPMSKRXFLVLMSK;
efm32_putreg(EFM32_USB_GINTMSK, intmsk); efm32_putreg(EFM32_USB_GINTMSK, intmsk);
} }
@@ -2446,7 +2446,7 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
{ {
/* Disable further Tx FIFO empty interrupts and bail. */ /* Disable further Tx FIFO empty interrupts and bail. */
efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_NPTXFE, 0); efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFEMPMSKNPTXFEMPMSK, 0);
return; return;
} }
@@ -2484,7 +2484,7 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
else else
{ {
efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_NPTXFE, 0); efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFEMPMSKNPTXFEMPMSK, 0);
} }
/* Write the next group of packets into the Tx FIFO */ /* Write the next group of packets into the Tx FIFO */
@@ -2535,7 +2535,7 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
{ {
/* Disable further Tx FIFO empty interrupts and bail. */ /* Disable further Tx FIFO empty interrupts and bail. */
efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFE, 0); efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFEMPMSKPTXFEMPMSK, 0);
return; return;
} }
@@ -2573,7 +2573,7 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
else else
{ {
efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFE, 0); efm32_modifyreg(EFM32_USB_GINTMSK, USB_GINTMSK_PTXFEMPMSKPTXFEMPMSK, 0);
} }
/* Write the next group of packets into the Tx FIFO */ /* Write the next group of packets into the Tx FIFO */
@@ -2782,7 +2782,7 @@ static inline void efm32_gint_discisr(FAR struct efm32_usbhost_s *priv)
/* Clear the dicsonnect interrupt */ /* Clear the dicsonnect interrupt */
efm32_putreg(EFM32_USB_GINTSTS, USB_GINTSTS_DISC); efm32_putreg(EFM32_USB_GINTSTS, USB_GINTSTS_DISCONNINT);
} }
/******************************************************************************* /*******************************************************************************
@@ -2807,7 +2807,7 @@ static inline void efm32_gint_ipxfrisr(FAR struct efm32_usbhost_s *priv)
/* Clear the incomplete isochronous OUT interrupt */ /* Clear the incomplete isochronous OUT interrupt */
efm32_putreg(EFM32_USB_GINTSTS, USB_GINTSTS_IPXFR); efm32_putreg(EFM32_USB_GINTSTS, USB_GINTSTS_INCOMPLP);
} }
/******************************************************************************* /*******************************************************************************
@@ -2877,7 +2877,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
/* Handle the non-periodic TxFIFO empty interrupt */ /* Handle the non-periodic TxFIFO empty interrupt */
if ((pending & USB_GINTSTS_NPTXFE) != 0) if ((pending & USB_GINTSTS_NPTXFEMP) != 0)
{ {
usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0);
efm32_gint_nptxfeisr(priv); efm32_gint_nptxfeisr(priv);
@@ -2885,7 +2885,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
/* Handle the periodic TxFIFO empty interrupt */ /* Handle the periodic TxFIFO empty interrupt */
if ((pending & USB_GINTSTS_PTXFE) != 0) if ((pending & USB_GINTSTS_PTXFEMP) != 0)
{ {
usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0);
efm32_gint_ptxfeisr(priv); efm32_gint_ptxfeisr(priv);
@@ -2893,7 +2893,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
/* Handle the host channels interrupt */ /* Handle the host channels interrupt */
if ((pending & USB_GINTSTS_HC) != 0) if ((pending & USB_GINTSTS_HCHINT) != 0)
{ {
usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0);
efm32_gint_hcisr(priv); efm32_gint_hcisr(priv);
@@ -2901,14 +2901,14 @@ static int efm32_gint_isr(int irq, FAR void *context)
/* Handle the host port interrupt */ /* Handle the host port interrupt */
if ((pending & USB_GINTSTS_HPRT) != 0) if ((pending & USB_GINTSTS_PRTINT) != 0)
{ {
efm32_gint_hprtisr(priv); efm32_gint_hprtisr(priv);
} }
/* Handle the disconnect detected interrupt */ /* Handle the disconnect detected interrupt */
if ((pending & USB_GINTSTS_DISC) != 0) if ((pending & USB_GINTSTS_DISCONNINT) != 0)
{ {
usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0);
efm32_gint_discisr(priv); efm32_gint_discisr(priv);
@@ -2916,7 +2916,7 @@ static int efm32_gint_isr(int irq, FAR void *context)
/* Handle the incomplete periodic transfer */ /* Handle the incomplete periodic transfer */
if ((pending & USB_GINTSTS_IPXFR) != 0) if ((pending & USB_GINTSTS_INCOMPLP) != 0)
{ {
usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0);
efm32_gint_ipxfrisr(priv); efm32_gint_ipxfrisr(priv);
@@ -3076,12 +3076,12 @@ static void efm32_txfe_enable(FAR struct efm32_usbhost_s *priv, int chidx)
default: default:
case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */ case OTGFS_EPTYPE_CTRL: /* Non periodic transfer */
case OTGFS_EPTYPE_BULK: case OTGFS_EPTYPE_BULK:
regval |= USB_GINTMSK_NPTXFE; regval |= USB_GINTMSK_NPTXFEMPMSK;
break; break;
case OTGFS_EPTYPE_INTR: /* Periodic transfer */ case OTGFS_EPTYPE_INTR: /* Periodic transfer */
case OTGFS_EPTYPE_ISOC: case OTGFS_EPTYPE_ISOC:
regval |= USB_GINTMSK_PTXFE; regval |= USB_GINTMSK_PTXFEMPMSK;
break; break;
} }
@@ -4332,8 +4332,8 @@ static inline int efm32_hw_initialize(FAR struct efm32_usbhost_s *priv)
/* Force Host Mode */ /* Force Host Mode */
regval = efm32_getreg(EFM32_USB_GUSBCFG); regval = efm32_getreg(EFM32_USB_GUSBCFG);
regval &= ~USB_GUSBCFG_FDMOD; regval &= ~_USB_GUSBCFG_FORCEDEVMODE_MASK;
regval |= USB_GUSBCFG_FHMOD; regval |= USB_GUSBCFG_FORCEHSTMODE;
efm32_putreg(EFM32_USB_GUSBCFG, regval); efm32_putreg(EFM32_USB_GUSBCFG, regval);
up_mdelay(50); up_mdelay(50);