diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig
index a17e8157549..c385f976b45 100644
--- a/arch/arm/src/tiva/Kconfig
+++ b/arch/arm/src/tiva/Kconfig
@@ -265,10 +265,6 @@ config LM_REVA2
 		Some early silicon returned an increase LDO voltage or 2.75V to work
 		around a PLL bug
 
-config TIVA_BOARD_EARLYINIT
-	bool
-	default n
-
 menu "Tiva/Stellaris Peripheral Support"
 
 # MCU capabilities
diff --git a/arch/arm/src/tiva/common/tiva_start.c b/arch/arm/src/tiva/common/tiva_start.c
index f9bca0ae047..46491ca551d 100644
--- a/arch/arm/src/tiva/common/tiva_start.c
+++ b/arch/arm/src/tiva/common/tiva_start.c
@@ -218,12 +218,8 @@ void __start(void)
 
   /* Configure the UART so that we can get debug output as soon as possible */
 
-#ifdef CONFIG_TIVA_BOARD_EARLYINIT
-  board_earlyinit();
-#else
   up_clockconfig();
   up_lowsetup();
-#endif
   tiva_fpuconfig();
   showprogress('A');
 
diff --git a/arch/arm/src/tiva/tiva_start.h b/arch/arm/src/tiva/tiva_start.h
index 0510c1b370f..64c449db3de 100644
--- a/arch/arm/src/tiva/tiva_start.h
+++ b/arch/arm/src/tiva/tiva_start.h
@@ -75,19 +75,4 @@ extern const uintptr_t g_idle_topstack;
 
 void tiva_boardinitialize(void);
 
-/****************************************************************************
- * Name: board_earlyinit
- *
- * Description:
- *   If CONFIG_TIVA_BOARD_EARLYINIT, then board-specific logic must provide
- *   the function board_earlyinit() to provide very customized lower-level
- *   board bringup.  board_earlyinit() will be called by the start-up logic
- *   instead of up_clockconfig() and up_lowsetup().
- *
- ****************************************************************************/
-
-#ifdef CONFIG_TIVA_BOARD_EARLYINIT
-void board_earlyinit(void);
-#endif
-
 #endif /* __ARCH_ARM_SRC_TIVA_TIVA_START_H */
diff --git a/configs/dk-tm4c129x/include/board.h b/configs/dk-tm4c129x/include/board.h
index c52a8f3b3ef..408df435dae 100644
--- a/configs/dk-tm4c129x/include/board.h
+++ b/configs/dk-tm4c129x/include/board.h
@@ -92,7 +92,7 @@
 /* When the PLL is active, the system clock frequency (SysClk) is calculated using
  * the following equation:
  *
- *   SysClk = Fvco/ (sysdiv + 1)
+ *   SysClk = Fvco / (sysdiv + 1)
  *
  * The following setup generates Sysclk = 120MHz:
  */