diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index 220ec740283..caf30bac22e 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -4553,15 +4553,15 @@ endif # SAMA5_DDRCS_RESERVE
 config SAMA5_DDRCS_PGHEAP
 	bool "Include DDR-SDRAM in page cache"
 	default y
-	depends on SAMA5_DDRCS && ARCH_ADDRENV
+	depends on (SAMA5_DDRCS || SAMA5_BOOT_SDRAM) && ARCH_ADDRENV
 	---help---
 		Include a portion of DDR-SDRAM memory in the page cache.
 
 if SAMA5_DDRCS_PGHEAP
 
 config SAMA5_DDRCS_PGHEAP_OFFSET
-	int "DDR-SDRAM heap offset"
-	default 0
+	hex "DDR-SDRAM heap offset"
+	default 0x0
 	---help---
 		Preserve this number of bytes at the beginning of SDRAM.  The
 		portion of DRAM beginning at this offset from the DDRCS base will
diff --git a/arch/arm/src/sama5/sam_pgalloc.c b/arch/arm/src/sama5/sam_pgalloc.c
index 6531aed8bf6..ba344c645af 100644
--- a/arch/arm/src/sama5/sam_pgalloc.c
+++ b/arch/arm/src/sama5/sam_pgalloc.c
@@ -57,11 +57,11 @@
  * handle any other possibility.
  */
 
-#ifdef CONFIG_SAMA5_DDRCS_PGHEAP
+#ifndef CONFIG_SAMA5_DDRCS_PGHEAP
 #  error CONFIG_SAMA5_DDRCS_PGHEAP must be selected
 #endif
 
-#ifdef CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET
+#ifndef CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET
 #  error CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET must be specified
 #endif
 
@@ -69,7 +69,7 @@
 #  warning CONFIG_SAMA5_DDRCS_PGHEAP_OFFSET is not aligned to a page boundary
 #endif
 
-#ifdef CONFIG_SAMA5_DDRCS_PGHEAP_SIZE
+#ifndef CONFIG_SAMA5_DDRCS_PGHEAP_SIZE
 #  error CONFIG_SAMA5_DDRCS_PGHEAP_SIZE must be specified
 #endif