From 98088a7456b8f6280dc5dd6bdfa8e05969b948b5 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Wed, 9 Nov 2016 19:52:29 +0100 Subject: [PATCH] typos --- arch/arm/src/stm32l4/stm32l4_qencoder.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 647d151fb37..4e0ebb0283c 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -402,7 +402,7 @@ static const struct stm32l4_qeconfig_s g_tim5config = .width = TIM5_BITWIDTH, #endif .base = STM32L4_TIM5_BASE, - .psc = CONFIG_STM32L4_TI55_QEPSC, + .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, #if TIM5_BITWIDTH == 16 @@ -787,10 +787,10 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) * The prescaler value is then that CLKIN value divided by the configured * CLKOUT value (minus one). * - * It was determined that this configration makes no sense for a qencoder. + * It was determined that this configuration makes no sense for a qencoder. * If we are doing precise shaft positioning, each qe pulse is important. * So the STM32L4 has direct config control on the pulse count prescaler, - * instead of deriving this value from an obscure "output"setting AND the + * instead of deriving this value from an obscure "output" setting AND the * timer input clock. This input clock just limits the incoming pulse rate, * which should be lower than the peripheral clock due to resynchronization, * but it is the responsibility of the system designer to decide the