arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and

irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>

arch/xtensa/src/esp32/esp32_cpuint.c

@@ -154,6 +154,16 @@ uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
 uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
 #endif
 
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+#ifdef CONFIG_SMP
+uint32_t g_intenable[CONFIG_SMP_NCPUS];
+#else
+uint32_t g_intenable[1];
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/

arch/xtensa/src/esp32/esp32_cpuint.h

@@ -46,6 +46,16 @@ extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
 extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
 #endif
 
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+#ifdef CONFIG_SMP
+extern uint32_t g_intenable[CONFIG_SMP_NCPUS];
+#else
+extern uint32_t g_intenable[1];
+#endif
+
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/

arch/xtensa/src/esp32/esp32_irq.c

@@ -59,16 +59,6 @@
  * Public Data
  ****************************************************************************/
 
-/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
- * content.
- */
-
-#ifdef CONFIG_SMP
-static uint32_t g_intenable[CONFIG_SMP_NCPUS];
-#else
-static uint32_t g_intenable[1];
-#endif
-
 /* g_current_regs[] holds a reference to the current interrupt level
  * register storage structure.  It is non-NULL only during interrupt
  * processing.  Access to g_current_regs[] must be through the macro