diff --git a/arch/Kconfig b/arch/Kconfig index a3c43d12d8b..32ecb064106 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -74,6 +74,11 @@ config ARCH_X86 ---help--- Intel x86 architectures. +config ARCH_XTENSA + bool "Xtensa" + ---help--- + Cadence® Tensilica® Xtensa® actictures. + config ARCH_Z16 bool "ZNEO" select ARCH_HAVE_HEAP2 @@ -99,6 +104,7 @@ config ARCH default "risc-v" if ARCH_RISCV default "sim" if ARCH_SIM default "x86" if ARCH_X86 + default "xtensa" if ARCH_XTENSA default "z16" if ARCH_Z16 default "z80" if ARCH_Z80 @@ -111,6 +117,7 @@ source arch/renesas/Kconfig source arch/risc-v/Kconfig source arch/sim/Kconfig source arch/x86/Kconfig +source arch/xtensa/Kconfig source arch/z16/Kconfig source arch/z80/Kconfig diff --git a/arch/README.txt b/arch/README.txt index 60676699764..4d4fe01ec13 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -253,6 +253,21 @@ arch/x86 - Intel x86 architectures arch/x86/include/i486 and arch/x86/src/i486 arch/x86/include/qemu and arch/x86/src/qemu +arch/xtensa + + Implementations based on the Cadence® Tensilica® Xtensa® processors, + such as the Xtensa LX6 dataplane processing units (DPUs). At + present, this includes the following subdirectories: + + Common XTENSA support: + arch/xtensa/include and arch/xtensa/src/common + + LX6 DPU support: + arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6 + + Expressif ESP32 implemenation of the LX6 DPU: + arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32 + arch/z16 - ZiLOG 16-bit processors This directory holds related, 16-bit architectures from ZiLOG. At present, this includes the following subdirectories: diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig new file mode 100644 index 00000000000..7d6ab3d343b --- /dev/null +++ b/arch/xtensa/Kconfig @@ -0,0 +1,60 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_XTENSA + +choice + prompt "XTENSA architecture selection" + default ARCH_CHIP_ESP32 + +config ARCH_CHIP_ESP32 + bool "Expressif ESP32" + select ARCH_FAMILY_LX6 + select XTENSA_HAVE_INTERRUPTS + select ARCH_HAVE_MULTICPU + ---help--- + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory + and peripherals are located on the data bus and/or the instruction + bus of these CPUs. With some minor exceptions, the address mapping + of two CPUs is symmetric, meaning they use the same addresses to + access the same memory. + +endchoice # XTENSA chip selection + +config ARCH_FAMILY_LX6 + bool + default n + ---help--- + Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). + The LX6 is a configurable and extensible processor core. + +config XTENSA_NCOPROCESSORS + int "Number of co-processors" + default 1 + +config XTENSA_CALL0_ABI + bool "CALL0 ABI" + default y + ---help--- + The Window ABI is not supported. Only the CALL0 ABI is supported in the + current implementation. + +config XTENSA_USE_OVLY + bool + default n + ---help--- + Enable code overlay support. This option is currently unsupported. + +config ARCH_CHIP + string + default "esp32" if ARCH_CHIP_ESP32 + +source arch/xtensa/src/lx6/Kconfig +if ARCH_CHIP_ESP32 +source arch/xtensa/src/esp32/Kconfig +endif + +endif # ARCH_XTENSA diff --git a/arch/xtensa/include/.gitignore b/arch/xtensa/include/.gitignore new file mode 100644 index 00000000000..e6460c4a678 --- /dev/null +++ b/arch/xtensa/include/.gitignore @@ -0,0 +1,3 @@ +/board +/chip + diff --git a/arch/xtensa/include/arch.h b/arch/xtensa/include/arch.h new file mode 100644 index 00000000000..760e52ff709 --- /dev/null +++ b/arch/xtensa/include/arch.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/xtensa/include/arch.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/arch.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ARCH_H +#define __ARCH_XTENSA_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_INCLUDE_ARCH_H */ diff --git a/arch/xtensa/include/esp32/chip.h b/arch/xtensa/include/esp32/chip.h new file mode 100644 index 00000000000..95e9e2cac3b --- /dev/null +++ b/arch/xtensa/include/esp32/chip.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/chip.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H +#define __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H */ diff --git a/arch/xtensa/include/esp32/core-isa.h b/arch/xtensa/include/esp32/core-isa.h new file mode 100644 index 00000000000..1204a26b8d6 --- /dev/null +++ b/arch/xtensa/include/esp32/core-isa.h @@ -0,0 +1,640 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/core-isa.h + * Xtensa processor CORE configuration + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H +#define __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option + * is configured, and a value of 0 otherwise. These macros are always + * defined. + */ + +/* ISA **********************************************************************/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +/* Misc. ********************************************************************/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + * (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ + +#define XCHAL_CORE_ID "esp32_v3_49_prod" + /* alphanum core name + * (CoreID) set in the Xtensa + * Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005fe96 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xc2bcfffe /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1cc5fe96 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260003 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 + +/* If software targets a *range* of hardware versions, these are the bounds: */ + +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ + +/* Cache ********************************************************************/ + +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + +/* Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code */ + +#ifndef XCHAL_HAL_NON_PRIVILEGED_ONLY + +/* Cache ********************************************************************/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ +#define XCHAL_HAVE_AXI 0 /* AXI bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ + +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ + +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ + +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ + +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits for decoded bits): */ + +#define XCHAL_CA_BITS 4 + +/* Internal I/D RAM/ROMs and XLMI *******************************************/ + +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ + +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ + +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 1: */ + +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data ROM 0: */ + +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + +/* Data RAM 1: */ + +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ + +/* XLMI Port 0: */ + +#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + +/* Interrupts and Timers ****************************************************/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_INT_NLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ + +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ + +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ + +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + * EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ + +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ + +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 + +/* Interrupt numbers assigned to specific interrupt sources: */ + +#define XTHAL_TIMER_UNCONFIGURED -1 /* REVISIT: should be in hal.h */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ + +#define XCHAL_INTLEVEL7_NUM 14 + +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + +/* External interrupt mapping. + * + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ + +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ + +/* Exceptions and Vectors ***************************************************/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + * number: 1 == XEA1 (old) + * 2 == XEA2 (new) + * 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + +/* Debug Module *************************************************************/ + +/* Misc */ + +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ + +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ + +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + +/* MMU **********************************************************************/ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + * [autorefill] and protection) + * usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XCHAL_HAL_NON_PRIVILEGED_ONLY */ + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H */ diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h new file mode 100644 index 00000000000..b394e8d6ba6 --- /dev/null +++ b/arch/xtensa/include/esp32/irq.h @@ -0,0 +1,226 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H +#define __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Exceptions + * + * IRAM Offset Description + * 0x0000 Windows + * 0x0180 Level 2 interrupt + * 0x01c0 Level 3 interrupt + * 0x0200 Level 4 interrupt + * 0x0240 Level 5 interrupt + * 0x0280 Debug exception + * 0x02c0 NMI exception + * 0x0300 Kernel exception + * 0x0340 User exception + * 0x03c0 Double exception + * + * REVISIT: In more architectures supported by NuttX, exception errors + * tie into the normal interrupt handling via special IRQ numbers. I + * is still to be determined what will be done for the the ESP32. + */ + +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ + +/* Interrupt Matrix + * + * The Interrupt Matrix embedded in the ESP32 independently allocates + * peripheral interrupt sources to the two CPUs’ peripheral interrupts. This + * configuration is highly flexible in order to meet many different needs. + * + * Features + * - Accepts 71 peripheral interrupt sources as input. + * - Generates 26 peripheral interrupt sources per CPU as output (52 total). + * - CPU NMI Interrupt Mask. + * - Queries current interrupt status of peripheral interrupt sources. + * + * Peripheral Interrupt Source + * + * ESP32 has 71 peripheral interrupt sources in total. 67 of 71 ESP32 + * peripheral interrupt sources can be allocated to either CPU. The four + * remaining peripheral interrupt sources are CPU-specific, two per CPU. + * + * - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to + * PRO_CPU. + * - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to + * APP_CPU. + * + * As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt + * sources. + */ + +/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ + +#define XTENSA_IRQ_SREG0 3 +#define XTENSA_IRQ_MAC 3 /* INTR_STATUS_REG_0, bit 0 */ +#define XTENSA_IRQ_MAC_NMI 4 /* INTR_STATUS_REG_0, bit 1 */ +#define XTENSA_IRQ_BB 5 /* INTR_STATUS_REG_0, bit 2 */ +#define XTENSA_IRQ_BB_MAC 6 /* INTR_STATUS_REG_0, bit 3 */ +#define XTENSA_IRQ_BT_BB 7 /* INTR_STATUS_REG_0, bit 4 */ +#define XTENSA_IRQ_BT_BB_NMI 8 /* INTR_STATUS_REG_0, bit 5 */ +#define XTENSA_IRQ_RWBT_IRQ 9 /* INTR_STATUS_REG_0, bit 6 */ +#define XTENSA_IRQ_RWBLE_IRQ 10 /* INTR_STATUS_REG_0, bit 7 */ +#define XTENSA_IRQ_RWBT_NMI 11 /* INTR_STATUS_REG_0, bit 8 */ +#define XTENSA_IRQ_RWBLE_NMI 12 /* INTR_STATUS_REG_0, bit 9 */ + +#define XTENSA_IRQ_SLC0 13 /* INTR_STATUS_REG_0, bit 10 */ +#define XTENSA_IRQ_SLC1 14 /* INTR_STATUS_REG_0, bit 11 */ +#define XTENSA_IRQ_UHCI0 15 /* INTR_STATUS_REG_0, bit 12 */ +#define XTENSA_IRQ_UHCI1 16 /* INTR_STATUS_REG_0, bit 13 */ +#define XTENSA_IRQ_TG_T0_LEVEL 17 /* INTR_STATUS_REG_0, bit 14 */ +#define XTENSA_IRQ_TG_T1_LEVEL 18 /* INTR_STATUS_REG_0, bit 15 */ +#define XTENSA_IRQ_TG_WDT_LEVEL 19 /* INTR_STATUS_REG_0, bit 16 */ +#define XTENSA_IRQ_TG_LACT_LEVEL 20 /* INTR_STATUS_REG_0, bit 17 */ +#define XTENSA_IRQ_TG1_T0_LEVEL 21 /* INTR_STATUS_REG_0, bit 18 */ +#define XTENSA_IRQ_TG1_T1_LEVEL 22 /* INTR_STATUS_REG_0, bit 19 */ + +#define XTENSA_IRQ_TG1_WDT_LEVEL 23 /* INTR_STATUS_REG_0, bit 20 */ +#define XTENSA_IRQ_G1_LACT_LEVEL 24 /* INTR_STATUS_REG_0, bit 21 */ +#define XTENSA_IRQ_CPU_GPIO 25 /* INTR_STATUS_REG_0, bit 22 */ +#define XTENSA_IRQ_CPU_NMI 26 /* INTR_STATUS_REG_0, bit 23 */ +#define XTENSA_IRQ_CPU_CPU0 27 /* INTR_STATUS_REG_0, bit 24 */ +#define XTENSA_IRQ_CPU_CPU1 28 /* INTR_STATUS_REG_0, bit 25 */ +#define XTENSA_IRQ_CPU_CPU2 29 /* INTR_STATUS_REG_0, bit 26 */ +#define XTENSA_IRQ_CPU_CPU3 30 /* INTR_STATUS_REG_0, bit 27 */ +#define XTENSA_IRQ_SPI0 31 /* INTR_STATUS_REG_0, bit 28 */ +#define XTENSA_IRQ_SPI1 32 /* INTR_STATUS_REG_0, bit 29 */ + +#define XTENSA_IRQ_SPI2 33 /* INTR_STATUS_REG_0, bit 30 */ +#define XTENSA_IRQ_SPI3 34 /* INTR_STATUS_REG_0, bit 31 */ + +/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ + +#define XTENSA_IRQ_SREG1 35 +#define XTENSA_IRQ_I2S0 35 /* INTR_STATUS_REG_1, bit 0 */ +#define XTENSA_IRQ_I2S1 36 /* INTR_STATUS_REG_1, bit 1 */ +#define XTENSA_IRQ_UART 37 /* INTR_STATUS_REG_1, bit 2 */ +#define XTENSA_IRQ_UART1 38 /* INTR_STATUS_REG_1, bit 3 */ +#define XTENSA_IRQ_UART2 39 /* INTR_STATUS_REG_1, bit 4 */ +#define XTENSA_IRQ_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 5 */ +#define XTENSA_IRQ_EMAC 41 /* INTR_STATUS_REG_1, bit 6 */ +#define XTENSA_IRQ_PWM0 42 /* INTR_STATUS_REG_1, bit 7 */ +#define XTENSA_IRQ_PWM1 43 /* INTR_STATUS_REG_1, bit 8 */ +#define XTENSA_IRQ_PWM2 44 /* INTR_STATUS_REG_1, bit 9 */ + +#define XTENSA_IRQ_PWM3 45 /* INTR_STATUS_REG_1, bit 10 */ +#define XTENSA_IRQ_LEDC 46 /* INTR_STATUS_REG_1, bit 11 */ +#define XTENSA_IRQ_EFUSE 47 /* INTR_STATUS_REG_1, bit 12 */ +#define XTENSA_IRQ_CAN 48 /* INTR_STATUS_REG_1, bit 13 */ +#define XTENSA_IRQ_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 14 */ +#define XTENSA_IRQ_RMT 50 /* INTR_STATUS_REG_1, bit 15 */ +#define XTENSA_IRQ_PCNT 51 /* INTR_STATUS_REG_1, bit 16 */ +#define XTENSA_IRQ_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 17 */ +#define XTENSA_IRQ_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 18 */ +#define XTENSA_IRQ_RSA 54 /* INTR_STATUS_REG_1, bit 19 */ + +#define XTENSA_IRQ_SPI1_DMA 55 /* INTR_STATUS_REG_1, bit 20 */ +#define XTENSA_IRQ_SPI2_DMA 56 /* INTR_STATUS_REG_1, bit 21 */ +#define XTENSA_IRQ_SPI3_DMA 57 /* INTR_STATUS_REG_1, bit 22 */ +#define XTENSA_IRQ_WDG 58 /* INTR_STATUS_REG_1, bit 23 */ +#define XTENSA_IRQ_TIMER1 59 /* INTR_STATUS_REG_1, bit 24 */ +#define XTENSA_IRQ_TIMER2 60 /* INTR_STATUS_REG_1, bit 25 */ +#define XTENSA_IRQ_TG_T0_EDGE 61 /* INTR_STATUS_REG_1, bit 26 */ +#define XTENSA_IRQ_TG_T1_EDGE 62 /* INTR_STATUS_REG_1, bit 27 */ +#define XTENSA_IRQ_TG_WDT_EDGE 63 /* INTR_STATUS_REG_1, bit 28 */ +#define XTENSA_IRQ_TG_LACT_EDGE 64 /* INTR_STATUS_REG_1, bit 29 */ + +#define XTENSA_IRQ_TG1_T0_EDGE 65 /* INTR_STATUS_REG_1, bit 30 */ +#define XTENSA_IRQ_TG1_T1_EDGE 66 /* INTR_STATUS_REG_1, bit 31 */ + +/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ + +#define XTENSA_IRQ_SREG2 67 +#define XTENSA_IRQ_TG1_WDT_EDGE 67 /* INTR_STATUS_REG_2, bit 0 */ +#define XTENSA_IRQ_TG1_LACT_EDGE 68 /* INTR_STATUS_REG_2, bit 1 */ +#define XTENSA_IRQ_MMU_IA 69 /* INTR_STATUS_REG_2, bit 2 */ +#define XTENSA_IRQ_MPU_IA 70 /* INTR_STATUS_REG_2, bit 3 */ +#define XTENSA_IRQ_CACHE_IA 71 /* INTR_STATUS_REG_2, bit 4 */ + +/* Total number of interrupts */ + +#define NR_IRQS 72 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h new file mode 100644 index 00000000000..7432441f94b --- /dev/null +++ b/arch/xtensa/include/irq.h @@ -0,0 +1,306 @@ +/**************************************************************************** + * arch/xtensa/include/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_IRQ_H +#define __ARCH_XTENSA_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include NuttX-specific IRQ definitions */ + +#include +#include +#include +#include +#include +#include + +/* Include architecture-specific IRQ definitions */ + +#ifdef CONFIG_ARCH_FAMILY_LX6 +# include + +/* Include implementation-specific IRQ definitions (including IRQ numbers) */ + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# include +# else +# error Unknown LX6 implementation +# endif + +#else +# error Unknown XTENSA architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ Stack Frame Format. Each value is a uint32_t register index */ + +#define REG_PC (0) /* Return PC */ +#define REG_PS (1) /* Return PS */ +#define REG_A0 (2) +#define REG_A1 (3) /* Stack pointer before interrupt */ +#define REG_A2 (4) +#define REG_A3 (5) +#define REG_A4 (6) +#define REG_A5 (7) +#define REG_A6 (8) +#define REG_A7 (9) +#define REG_A8 (10) +#define REG_A9 (11) +#define REG_A10 (12) +#define REG_A11 (13) +#define REG_A12 (14) +#define REG_A13 (15) +#define REG_A14 (16) +#define REG_A15 (17) +#define REG_SAR (18) +#define REG_EXCCAUSE (19) +#define REG_EXCVADDR (20) + +#define _REG_LOOPS_START (21) + +#ifdef XCHAL_HAVE_LOOPS +# define REG_LBEG (_REG_LOOPS_START + 0) +# define REG_LEND (_REG_LOOPS_START + 1) +# define REG_LCOUNT (_REG_LOOPS_START + 2) +# define _REG_CALL0_START (_REG_LOOPS_START + 3) +#else +# define _REG_CALL0_START _REG_LOOPS_START +#endif + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* Temporary space for saving stuff during window spill */ + +# define REG_TMP0 (_REG_CALL0_START + 0) +# define REG_TMP1 (_REG_CALL0_START + 1) +# define REG_TMP2 (_REG_CALL0_START + 2) +# define _REG_OVLY_START (_REG_CALL0_START + 3) +#else +# define _REG_OVLY_START _REG_CALL0_START +#endif + +#ifdef CONFIG_XTENSA_USE_OVLY +/* Storage for overlay state */ + +# error Overlays not supported +# define XCPTCONTEXT_REGS _REG_OVLY_START +#else +# define XCPTCONTEXT_REGS _REG_OVLY_START +#endif + +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* This struct defines the way the registers are stored. */ + +struct xcptcontext +{ + /* The following function pointer is non-zero if there are pending signals + * to be processed. + */ + +#ifndef CONFIG_DISABLE_SIGNALS + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These are saved copies of registers used during signal processing. */ + + uint32_t saved_pc; + uint32_t saved_ps; +#endif + + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; + +#ifdef CONFIG_LIB_SYSCALL + /* The following array holds the return address and the exc_return value + * needed to return from each nested system call. + */ + + uint8_t nsyscalls; + struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST]; +#endif +}; + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/* Return the current value of the PS register */ + +static inline uint32_t xtensa_getps(void) +{ + uint32_t ps; + + __asm__ __volatile__ + ( + "rsr %0, PS" : "=r"(ps) + ); + + return ps; +} + +/* Set the value of the PS register */ + +static inline void xtensa_setps(uint32_t ps) +{ + __asm__ __volatile__ + ( + "wsr %0, PS" : : "r"(ps) + ); +} + +/* Restore the value of the PS register */ + +static inline void up_irq_restore(uint32_t ps) +{ + __asm__ __volatile__ + ( + "wsr %0, PS" : : "r"(ps) + ); +} + +/* Disable interrupts and return the previous value of the PS register */ + +static inline uint32_t up_irq_save(void) +{ + /* Get the current value of the PS for return */ + + uint32_t ps = xtensa_getps(); + + /* Disable all low- and medium-priority interrupts. High priority + * interrupts should not interfere with ongoing RTOS operations and + * are not disabled. + * + * NOTE: We also assume that since we were called from C logic, the + * EXCM must already be cleared. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); +#endif + + /* Return the previous PS value so that it can be restored with + * up_irq_restore(). + */ + + return ps; +} + +/* Enable interrupts at all levels */ + +static inline void up_irq_enable(void) +{ +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(0) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif +} + +/* Disable low- and medium- priority interrupts */ + +static inline void up_irq_disable(void) +{ +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); +#endif +} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_enable_interrupts + * + * Description: + * Enables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + +irqstate_t xtensa_enable_interrupts(irqstate_t mask); + +/**************************************************************************** + * Name: xtensa_disable_interrupts + * + * Description: + * Disables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + +irqstate_t xtensa_disable_interrupts(irqstate_t mask); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_IRQ_H */ diff --git a/arch/xtensa/include/limits.h b/arch/xtensa/include/limits.h new file mode 100644 index 00000000000..f3eb3b4795c --- /dev/null +++ b/arch/xtensa/include/limits.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/xtensa/include/limits.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_LIMITS_H +#define __ARCH_XTENSA_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* __ARCH_XTENSA_INCLUDE_LIMITS_H */ + diff --git a/arch/xtensa/include/lx6/chip.h b/arch/xtensa/include/lx6/chip.h new file mode 100644 index 00000000000..a3cb0e3e846 --- /dev/null +++ b/arch/xtensa/include/lx6/chip.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/xtensa/include/lx6/chip.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_LX6_CHIP_H +#define __ARCH_XTENSA_INCLUDE_LX6_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX6_CHIP_H */ diff --git a/arch/xtensa/include/lx6/irq.h b/arch/xtensa/include/lx6/irq.h new file mode 100644 index 00000000000..ddc87e0c2bc --- /dev/null +++ b/arch/xtensa/include/lx6/irq.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/xtensa/include/lx6/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_LX6_IRQ_H +#define __ARCH_XTENSA_INCLUDE_LX6_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX6_IRQ_H */ diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h new file mode 100644 index 00000000000..9d0ef213d01 --- /dev/null +++ b/arch/xtensa/include/spinlock.h @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/xtensa/include/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SP_UNLOCKED 0 /* The Un-locked state */ +#define SP_LOCKED 1 /* The Locked state */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* The Type of a spinlock. + * + * This must be a uint32_ becaue it will be set using S32C1I instruction. + * That instruction atomically stores to a memory location only if its + * current value is the expected one. The state register (SCOMPARE1) is + * used to provide the additional comparison operand. Some implementations + * also have a state register (ATOMCTL) for further control of the atomic + * operation in cache and on the PIF bus. + */ + +typedef uint32_t spinlock_t; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logoic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * as previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +/* See prototype in nuttx/include/nuttx/spinlock.h */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_INCLUDE_SPINLOCK_H */ diff --git a/arch/xtensa/include/syscall.h b/arch/xtensa/include/syscall.h new file mode 100644 index 00000000000..fe2d71e6def --- /dev/null +++ b/arch/xtensa/include/syscall.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/xtensa/include/syscall.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_SYSCALL_H +#define __ARCH_XTENSA_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_XTENSA_INCLUDE_SYSCALL_H */ diff --git a/arch/xtensa/include/types.h b/arch/xtensa/include/types.h new file mode 100644 index 00000000000..55d2fee188d --- /dev/null +++ b/arch/xtensa/include/types.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/xtensa/include/types.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through stdint.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_TYPES_H +#define __ARCH_XTENSA_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed long _int32_t; +typedef unsigned long _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed long _intptr_t; +typedef unsigned long _uintptr_t; + +/* This is the size of the interrupt state save returned by up_irq_save(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_XTENSA_INCLUDE_TYPES_H */ diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h new file mode 100644 index 00000000000..ae9f01ab302 --- /dev/null +++ b/arch/xtensa/include/xtensa/core.h @@ -0,0 +1,1455 @@ +/**************************************************************************** + * arch/xtensa/include/core.h + * + * Leveraged to NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * + * This file derives from code provided Cadence Design Systems, Inc.: + * + * Copyright (c) 2005-2014 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +/* This header file is sometimes referred to as the "compile-time HAL" or CHAL. + * It pulls definitions tailored for a specific Xtensa processor configuration. + * + * Sources for binaries meant to be configuration-independent generally avoid + * including this file (they may use the configuration-specific HAL library). + * It is normal for the HAL library source itself to include this file. + */ + +#ifndef __ARCH_XTENSA_INCUDE_XTENSA_CORE_H +#define __ARCH_XTENSA_INCUDE_XTENSA_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Configuration independent definitions: */ + +#warning REVISIT: Missing header files: +//#include +//#include + +/* Configuration specific definitions: */ + +#include +//#include +//#include + +#ifdef __ASSEMBLY__ +//# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General ******************************************************************/ + +/* Separators for macros that expand into arrays. + * These can be predefined by files that #include this one, + * when different separators are required. + */ + +/* Element separator for macros that expand into 1-dimensional arrays: */ +#ifndef XCHAL_SEP +# define XCHAL_SEP , +#endif + +/* Array separator for macros that expand into 2-dimensional arrays: */ +#ifndef XCHAL_SEP2 +# define XCHAL_SEP2 },{ +#endif + +/* ISA **********************************************************************/ + +#if XCHAL_HAVE_BE +# define XCHAL_HAVE_LE 0 +# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN +#else +# define XCHAL_HAVE_LE 1 +# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN +#endif + +/* Interrupts ***************************************************************/ + +/* Indexing macros: */ + +#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK +#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK +#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM +#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ +#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL +#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ +#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE +#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ +#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT +#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ + +#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS +#define XCHAL_NUM_LOWPRI_LEVELS 1 /* Number of low-priority + * interrupt levels (always 1) */ +#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) + /* Level of first high-priority + * interrupt (always 2) */ + +/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ + +/* These values are constant for existing Xtensa processor implementations: */ + +#define XCHAL_INTLEVEL0_MASK 0x00000000 +#define XCHAL_INTLEVEL8_MASK 0x00000000 +#define XCHAL_INTLEVEL9_MASK 0x00000000 +#define XCHAL_INTLEVEL10_MASK 0x00000000 +#define XCHAL_INTLEVEL11_MASK 0x00000000 +#define XCHAL_INTLEVEL12_MASK 0x00000000 +#define XCHAL_INTLEVEL13_MASK 0x00000000 +#define XCHAL_INTLEVEL14_MASK 0x00000000 +#define XCHAL_INTLEVEL15_MASK 0x00000000 + +/* Array of masks of interrupts at each interrupt level: */ + +#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_MASK + +/* These values are constant for existing Xtensa processor implementations: */ + +#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 +#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK + +/* Mask of all low-priority interrupts: */ + +#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK + +/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ + +#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) + +/* Array of masks of interrupts at each range 1..n of interrupt levels: */ + +#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK + +#if 0 /* XCHAL_HAVE_NMI */ + +/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ + +# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) +#endif + +/* Array of levels of each possible interrupt: */ + +#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ + XCHAL_SEP XCHAL_INT1_LEVEL \ + XCHAL_SEP XCHAL_INT2_LEVEL \ + XCHAL_SEP XCHAL_INT3_LEVEL \ + XCHAL_SEP XCHAL_INT4_LEVEL \ + XCHAL_SEP XCHAL_INT5_LEVEL \ + XCHAL_SEP XCHAL_INT6_LEVEL \ + XCHAL_SEP XCHAL_INT7_LEVEL \ + XCHAL_SEP XCHAL_INT8_LEVEL \ + XCHAL_SEP XCHAL_INT9_LEVEL \ + XCHAL_SEP XCHAL_INT10_LEVEL \ + XCHAL_SEP XCHAL_INT11_LEVEL \ + XCHAL_SEP XCHAL_INT12_LEVEL \ + XCHAL_SEP XCHAL_INT13_LEVEL \ + XCHAL_SEP XCHAL_INT14_LEVEL \ + XCHAL_SEP XCHAL_INT15_LEVEL \ + XCHAL_SEP XCHAL_INT16_LEVEL \ + XCHAL_SEP XCHAL_INT17_LEVEL \ + XCHAL_SEP XCHAL_INT18_LEVEL \ + XCHAL_SEP XCHAL_INT19_LEVEL \ + XCHAL_SEP XCHAL_INT20_LEVEL \ + XCHAL_SEP XCHAL_INT21_LEVEL \ + XCHAL_SEP XCHAL_INT22_LEVEL \ + XCHAL_SEP XCHAL_INT23_LEVEL \ + XCHAL_SEP XCHAL_INT24_LEVEL \ + XCHAL_SEP XCHAL_INT25_LEVEL \ + XCHAL_SEP XCHAL_INT26_LEVEL \ + XCHAL_SEP XCHAL_INT27_LEVEL \ + XCHAL_SEP XCHAL_INT28_LEVEL \ + XCHAL_SEP XCHAL_INT29_LEVEL \ + XCHAL_SEP XCHAL_INT30_LEVEL \ + XCHAL_SEP XCHAL_INT31_LEVEL + +/* Array of types of each possible interrupt: */ + +#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ + XCHAL_SEP XCHAL_INT1_TYPE \ + XCHAL_SEP XCHAL_INT2_TYPE \ + XCHAL_SEP XCHAL_INT3_TYPE \ + XCHAL_SEP XCHAL_INT4_TYPE \ + XCHAL_SEP XCHAL_INT5_TYPE \ + XCHAL_SEP XCHAL_INT6_TYPE \ + XCHAL_SEP XCHAL_INT7_TYPE \ + XCHAL_SEP XCHAL_INT8_TYPE \ + XCHAL_SEP XCHAL_INT9_TYPE \ + XCHAL_SEP XCHAL_INT10_TYPE \ + XCHAL_SEP XCHAL_INT11_TYPE \ + XCHAL_SEP XCHAL_INT12_TYPE \ + XCHAL_SEP XCHAL_INT13_TYPE \ + XCHAL_SEP XCHAL_INT14_TYPE \ + XCHAL_SEP XCHAL_INT15_TYPE \ + XCHAL_SEP XCHAL_INT16_TYPE \ + XCHAL_SEP XCHAL_INT17_TYPE \ + XCHAL_SEP XCHAL_INT18_TYPE \ + XCHAL_SEP XCHAL_INT19_TYPE \ + XCHAL_SEP XCHAL_INT20_TYPE \ + XCHAL_SEP XCHAL_INT21_TYPE \ + XCHAL_SEP XCHAL_INT22_TYPE \ + XCHAL_SEP XCHAL_INT23_TYPE \ + XCHAL_SEP XCHAL_INT24_TYPE \ + XCHAL_SEP XCHAL_INT25_TYPE \ + XCHAL_SEP XCHAL_INT26_TYPE \ + XCHAL_SEP XCHAL_INT27_TYPE \ + XCHAL_SEP XCHAL_INT28_TYPE \ + XCHAL_SEP XCHAL_INT29_TYPE \ + XCHAL_SEP XCHAL_INT30_TYPE \ + XCHAL_SEP XCHAL_INT31_TYPE + +/* Array of masks of interrupts for each type of interrupt: */ + +#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ + XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ + XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ + XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ + XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR + +/* Interrupts that can be cleared using the INTCLEAR special register: */ + +#define XCHAL_INTCLEARABLE_MASK \ + (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) + +/* Interrupts that can be triggered using the INTSET special register: */ + +#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE + +/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ + +#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER3_INTERRUPT + +/* For backward compatibility and for the array macros, define macros for + * each unconfigured interrupt number (unfortunately, the value of + * XTHAL_INTTYPE_UNCONFIGURED is not zero): + */ + +#if XCHAL_NUM_INTERRUPTS == 0 +# define XCHAL_INT0_LEVEL 0 +# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +# define XCHAL_INT1_LEVEL 0 +# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +# define XCHAL_INT2_LEVEL 0 +# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +# define XCHAL_INT3_LEVEL 0 +# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +# define XCHAL_INT4_LEVEL 0 +# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +# define XCHAL_INT5_LEVEL 0 +# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +# define XCHAL_INT6_LEVEL 0 +# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +# define XCHAL_INT7_LEVEL 0 +# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +# define XCHAL_INT8_LEVEL 0 +# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +# define XCHAL_INT9_LEVEL 0 +# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +# define XCHAL_INT10_LEVEL 0 +# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +# define XCHAL_INT11_LEVEL 0 +# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +# define XCHAL_INT12_LEVEL 0 +# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +# define XCHAL_INT13_LEVEL 0 +# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +# define XCHAL_INT14_LEVEL 0 +# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +# define XCHAL_INT15_LEVEL 0 +# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +# define XCHAL_INT16_LEVEL 0 +# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +# define XCHAL_INT17_LEVEL 0 +# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +# define XCHAL_INT18_LEVEL 0 +# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +# define XCHAL_INT19_LEVEL 0 +# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +# define XCHAL_INT20_LEVEL 0 +# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +# define XCHAL_INT21_LEVEL 0 +# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +# define XCHAL_INT22_LEVEL 0 +# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +# define XCHAL_INT23_LEVEL 0 +# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +# define XCHAL_INT24_LEVEL 0 +# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +# define XCHAL_INT25_LEVEL 0 +# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +# define XCHAL_INT26_LEVEL 0 +# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +# define XCHAL_INT27_LEVEL 0 +# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +# define XCHAL_INT28_LEVEL 0 +# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +# define XCHAL_INT29_LEVEL 0 +# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +# define XCHAL_INT30_LEVEL 0 +# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +# define XCHAL_INT31_LEVEL 0 +# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif + +/* Masks and levels corresponding to each *external* interrupt. */ + +#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) +#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) + +/* Exceptions and Vectors ***************************************************/ + +/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ + +#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if + * old exception + * architecture (XEA1), + * 0 otherwise (eg. + * XEA2) */ +#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if + * PS.EXCM bit exists + * (currently equals + * XCHAL_HAVE_TLBS) */ +#ifdef XCHAL_USER_VECTOR_VADDR +# define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +# define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#endif +#ifdef XCHAL_USER_VECTOR_PADDR +# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +#endif + +#if 0 +# if XCHAL_HAVE_DEBUG +# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) + +/* This one should only get defined if the corresponding intlevel paddr macro exists: */ + +# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) +# endif +#endif + +/* Indexing macros: */ + +#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR +#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ + +/* General Exception Causes: + * + * Values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors. + * + * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros + * defined in . (Note that these have slightly + * different names, they don't just have the XCHAL_ prefix removed.) + */ + +#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ +#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ +#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ +#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ +#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ +#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ + /* 10..15 reserved */ +#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ +#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ +#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ +#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ + /* 21..23 reserved */ +#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ +#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ +#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ +#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ +#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ + /* 30..31 reserved */ +#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ + /* 40..63 reserved */ + +/* Miscellaneous special register fields. + * + * For each special register, and each field within each register: + * XCHAL__VALIDMASK is the set of bits defined in the register. + * XCHAL___BITS is the number of bits in the field. + * XCHAL___NUM is 2^bits, the number of possible values + * of the field. + * XCHAL___SHIFT is the position of the field within + * the register, starting from the least significant bit. + * + * DEPRECATED. Please use the equivalent macros defined in + * . (Note that these have different names.) + */ + +/* DBREAKC (special register number 160): */ + +#define XCHAL_DBREAKC_VALIDMASK 0xC000003F +#define XCHAL_DBREAKC_MASK_BITS 6 +#define XCHAL_DBREAKC_MASK_NUM 64 +#define XCHAL_DBREAKC_MASK_SHIFT 0 +#define XCHAL_DBREAKC_MASK_MASK 0x0000003F +#define XCHAL_DBREAKC_LOADBREAK_BITS 1 +#define XCHAL_DBREAKC_LOADBREAK_NUM 2 +#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 +#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 +#define XCHAL_DBREAKC_STOREBREAK_BITS 1 +#define XCHAL_DBREAKC_STOREBREAK_NUM 2 +#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 +#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 + +/* PS (special register number 230): */ + +#define XCHAL_PS_VALIDMASK 0x00070F3F +#define XCHAL_PS_INTLEVEL_BITS 4 +#define XCHAL_PS_INTLEVEL_NUM 16 +#define XCHAL_PS_INTLEVEL_SHIFT 0 +#define XCHAL_PS_INTLEVEL_MASK 0x0000000F +#define XCHAL_PS_EXCM_BITS 1 +#define XCHAL_PS_EXCM_NUM 2 +#define XCHAL_PS_EXCM_SHIFT 4 +#define XCHAL_PS_EXCM_MASK 0x00000010 +#define XCHAL_PS_UM_BITS 1 +#define XCHAL_PS_UM_NUM 2 +#define XCHAL_PS_UM_SHIFT 5 +#define XCHAL_PS_UM_MASK 0x00000020 +#define XCHAL_PS_RING_BITS 2 +#define XCHAL_PS_RING_NUM 4 +#define XCHAL_PS_RING_SHIFT 6 +#define XCHAL_PS_RING_MASK 0x000000C0 +#define XCHAL_PS_OWB_BITS 4 +#define XCHAL_PS_OWB_NUM 16 +#define XCHAL_PS_OWB_SHIFT 8 +#define XCHAL_PS_OWB_MASK 0x00000F00 +#define XCHAL_PS_CALLINC_BITS 2 +#define XCHAL_PS_CALLINC_NUM 4 +#define XCHAL_PS_CALLINC_SHIFT 16 +#define XCHAL_PS_CALLINC_MASK 0x00030000 +#define XCHAL_PS_WOE_BITS 1 +#define XCHAL_PS_WOE_NUM 2 +#define XCHAL_PS_WOE_SHIFT 18 +#define XCHAL_PS_WOE_MASK 0x00040000 + +/* EXCCAUSE (special register number 232): */ + +#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F +#define XCHAL_EXCCAUSE_BITS 6 +#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_SHIFT 0 +#define XCHAL_EXCCAUSE_MASK 0x0000003F + +/* DEBUGCAUSE (special register number 233): */ + +#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F +#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 +#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 +#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 +#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 +#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 +#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 +#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 +#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 +#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 +#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 +#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 +#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 +#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 +#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 +#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 +#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 + +/* Timers *******************************************************************/ + +/* #define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT */ + +/* Internal I/D RAMS/ROMS and XLMI ******************************************/ + +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ + +#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ + +/* Cache ********************************************************************/ + +/* Default PREFCTL value to enable prefetch. */ + +#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* Enabled, not aggressive */ +#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */ +#elif XCHAL_PREFETCH_ENTRIES >= 16 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ +#elif XCHAL_PREFETCH_ENTRIES >= 8 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ +#else +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ +#endif + +/* Max for both I-cache and D-cache (used for general alignment): */ + +#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE +#else +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE +#endif + +#define XCHAL_ICACHE_SETSIZE (1 << XCHAL_ICACHE_SETWIDTH) +#define XCHAL_DCACHE_SETSIZE (1 << XCHAL_DCACHE_SETWIDTH) + +/* Max for both I and D caches (used for cache-coherency page alignment): */ + +#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE +#else +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE +#endif + +/* Instruction cache tag bits: */ + +#define XCHAL_ICACHE_TAG_V_SHIFT 0 +#define XCHAL_ICACHE_TAG_V 0x1 /* Valid bit */ +#if XCHAL_ICACHE_WAYS > 1 +# define XCHAL_ICACHE_TAG_F_SHIFT 1 +# define XCHAL_ICACHE_TAG_F 0x2 /* Fill (LRU) bit */ +#else +# define XCHAL_ICACHE_TAG_F_SHIFT 0 +# define XCHAL_ICACHE_TAG_F 0 /* No fill (LRU) bit */ +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE +# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) +# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* Lock bit */ +#else +# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT +# define XCHAL_ICACHE_TAG_L 0 /* No lock bit */ +#endif + +/* Data cache tag bits: */ + +#define XCHAL_DCACHE_TAG_V_SHIFT 0 +#define XCHAL_DCACHE_TAG_V 0x1 /* Valid bit */ +#if XCHAL_DCACHE_WAYS > 1 +# define XCHAL_DCACHE_TAG_F_SHIFT 1 +# define XCHAL_DCACHE_TAG_F 0x2 /* Fill (LRU) bit */ +#else +# define XCHAL_DCACHE_TAG_F_SHIFT 0 +# define XCHAL_DCACHE_TAG_F 0 /* No fill (LRU) bit */ +#endif +#if XCHAL_DCACHE_IS_WRITEBACK +# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) +# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* Dirty bit */ +#else +# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT +# define XCHAL_DCACHE_TAG_D 0 /* No dirty bit */ +#endif +#if XCHAL_DCACHE_LINE_LOCKABLE +# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) +# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* Lock bit */ +#else +# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT +# define XCHAL_DCACHE_TAG_L 0 /* No lock bit */ +#endif + +/* Whether MEMCTL register has anything useful */ + +#define XCHAL_USE_MEMCTL \ + (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + +/* Default MEMCTL values: */ + +#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS + +/* NOTE: constant defined this way to allow movi instead of l32r in reset code. */ + +# define XCHAL_CACHE_MEMCTL_DEFAULT 0xFFFFFF00 /* Init all possible ways */ +#else +# define XCHAL_CACHE_MEMCTL_DEFAULT 0x00000000 /* Nothing to do */ +#endif + +#if XCHAL_DCACHE_IS_COHERENT +# define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ +#else +# define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ +#endif + +#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 +# define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ +#else +# define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ +#endif + +#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) + +/* MMU **********************************************************************/ + +/* See for more details. */ + +/* Has different semantic in open source headers (where it means HAVE_PTP_MMU), + * so comment out starting with RB-2008.3 release; later, might get + * get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: + */ + +/* #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*//* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ + +/* Indexing macros: */ + +#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what +#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) +#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what +#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) +#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what +#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) +#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what +#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) + +/* Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) + * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. + */ + +/* Number of entries per autorefill way: */ + +#define XCHAL_ITLB_ARF_ENTRIES (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2) +#define XCHAL_DTLB_ARF_ENTRIES (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2) + +/* Determine whether we have a full MMU (with Page Table and Protection) + * usable for an MMU-based OS: + */ + +#if 0 +# if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && \ + XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 +# define XCHAL_HAVE_PTP_MMU 1 /* Have full MMU (with page table + * [autorefill] and protection) */ +# else +# define XCHAL_HAVE_PTP_MMU 0 /* Don't have full MMU */ +# endif +#endif + +/* For full MMUs, report kernel RAM segment and kernel I/O segment static + * page mappings: + */ + +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +# define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel + * RAM cached static + * map */ +# define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of + * kseg_cached */ +# define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of + * kseg_cached (assumed + * power of 2!!!) */ +# define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel + * RAM bypass + * (uncached) static + * map */ +# define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of + * kseg_bypass */ +# define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of + * kseg_bypass (assumed + * power of 2!!!) */ +# define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel + * I/O cached static + * map */ +# define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of + * kio_cached */ +# define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached + * (assumed power of 2!!!) */ +# define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel + * I/O bypass + * (uncached) static + * map */ +# define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of + * kio_bypass */ +# define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass + * (assumed power of 2!!!) */ +# define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest + * non-static-mapped virtual + * addr area */ +# define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ + +/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of + * descending size. + */ +#endif + +/* Misc. **************************************************** + +/* Data alignment required if used for instructions: */ + +#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH +# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH +#else +# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH +#endif + +/* Names kept for backward compatibility. + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ + +#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR +#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR +#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME + +/* Co-processors and extra state ********************************************/ + +#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE +#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN +#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE +#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN + +#ifdef __ASSEMBLY__ + +/* Invoked at start of save area load/store sequence macro to setup macro + * internal offsets. Not usually invoked directly. continue 0 for 1st + * sequence, 1 for subsequent consecutive ones. totofs offset from + * original ptr to next load/store location. + */ + + .macro xchal_sa_start continue totofs + .ifeq \continue + .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ + .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ + .endif + .if \totofs + 1 /* if totofs specified (not -1) */ + .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ + .endif + .endm + +/* Align portion of save area and bring ptr in range if necessary. Used by + * save area load/store sequences. Not usually invoked directly. Allows + * combining multiple (sub-)sequences arbitrarily. ptr pointer to save + * area (may be off, see .Lxchal_pofs_) minofs,maxofs range of offset from + * cur ptr to next load/store loc; minofs <= 0 <= maxofs (0 must always be + * valid offset) range must be within +/- 30kB or so. ofsalign alignment + * granularity of minofs .. maxofs (pow of 2) (restriction on offset from + * ptr to next load/store loc) totalign align from orig ptr to next + * load/store loc (pow of 2) + */ + + .macro xchal_sa_align ptr minofs maxofs ofsalign totalign + + /* First align where we start accessing the next register + * per \totalign relative to original ptr (i.e. start of the save area): + */ + + .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ + + /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ + + .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) + .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ + addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) + .endif + .endm + +/* We could optimize for addi to expand to only addmi instead of + * "addmi;addi", where possible. Here's a partial example how: + * + * .set .Lmaxmask, -(\ofsalign) & -(\totalign) + * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) + * .set .Ligmask, 0xFFFFFF00 + * .elif ... ditto for negative ofs range ... + * .set .Ligmask, 0xFFFFFF00 + * .set ... adjust per offset ... + * .else + * .set .Ligmask, 0xFFFFFFFF + * .endif + * + +/* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ + + .macro xchal_sa_ptr_restore ptr + .if .Lxchal_pofs_ + addi \ptr, \ptr, - .Lxchal_pofs_ + .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + .set .Lxchal_pofs_, 0 + .endif + .endm + +/* Use as eg: + * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * xchal_ncp_load a2, a0,a3,a4,a5 + * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * + * Specify only the ARs you *haven't* saved/restored already, up to 4. + * They *must* be the *last* ARs (in same order) specified to save area + * load/store sequences. In the example above, a0 and a3 were already + * saved/restored and unused (thus available) but a4 and a5 were not. + */ + +#define xchal_atmps_store xchal_atmps_loadstore s32i, +#define xchal_atmps_load xchal_atmps_loadstore l32i, + + .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 + .set .Lnsaved_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif + .endr + .set .Laofs_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifgt (\nreq)-.Lnsaved_ + \inst \reg, \ptr, .Laofs_+\offset + .set .Laofs_,.Laofs_+4 + .set .Lnsaved_,.Lnsaved_+1 + .endif + .endr + .endm + + +/* #define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 */ +/* #define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 */ +# define xchal_extratie_load xchal_ncptie_load +# define xchal_extratie_store xchal_ncptie_store +# define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 +# define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 +# define xchal_extra_load xchal_ncp_load +# define xchal_extra_store xchal_ncp_store +# define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 +# define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 +# define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 +# define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 +# define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 +# define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 +# define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 +# define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 +# define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 +# define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 +# define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 +# define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 +# define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 +# define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 +# define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 +# define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 +# define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 +# define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 +# define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 +# define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 + +/* Empty placeholder macros for undefined coprocessors: */ + +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 +# if XCHAL_CP0_SA_SIZE == 0 + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP1_SA_SIZE == 0 + .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP2_SA_SIZE == 0 + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP3_SA_SIZE == 0 + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP4_SA_SIZE == 0 + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP5_SA_SIZE == 0 + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP6_SA_SIZE == 0 + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP7_SA_SIZE == 0 + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +#endif + +/* Macros to create functions that save and restore the state of *any* TIE + * coprocessor (by dynamic index). + */ + +/* Macro that expands to the body of a function that stores the selected + * coprocessor's state (registers etc). + * + * Entry: a2 = ptr to save area in which to save cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + + .macro xchal_cpi_store_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_store_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_store_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_store_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_store_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_store_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_store_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_store_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_store_a2 + j 90f +99: +# endif +90: +#endif + +/* Macro that expands to the body of a function that loads the selected coprocessor's state + * (registers etc). + * + * Entry: a2 = ptr to save area from which to restore cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + + .macro xchal_cpi_load_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_load_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_load_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_load_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_load_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_load_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_load_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_load_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_load_a2 + j 90f +99: +# endif +90: +#endif + .endm + +#endif /* __ASSEMBLY__ */ + +/* Other default macros for undefined coprocessors: */ + +#ifndef XCHAL_CP0_NAME +# define XCHAL_CP0_NAME 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP1_NAME +# define XCHAL_CP1_NAME 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP2_NAME +# define XCHAL_CP2_NAME 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP3_NAME +# define XCHAL_CP3_NAME 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP4_NAME +# define XCHAL_CP4_NAME 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP5_NAME +# define XCHAL_CP5_NAME 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP6_NAME +# define XCHAL_CP6_NAME 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP7_NAME +# define XCHAL_CP7_NAME 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ +#endif + +#if XCHAL_CP_MASK == 0 +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ + +# define XCHAL_CP0_SA_SIZE 0 +# define XCHAL_CP0_SA_ALIGN 1 +# define XCHAL_CP1_SA_SIZE 0 +# define XCHAL_CP1_SA_ALIGN 1 +# define XCHAL_CP2_SA_SIZE 0 +# define XCHAL_CP2_SA_ALIGN 1 +# define XCHAL_CP3_SA_SIZE 0 +# define XCHAL_CP3_SA_ALIGN 1 +# define XCHAL_CP4_SA_SIZE 0 +# define XCHAL_CP4_SA_ALIGN 1 +# define XCHAL_CP5_SA_SIZE 0 +# define XCHAL_CP5_SA_ALIGN 1 +# define XCHAL_CP6_SA_SIZE 0 +# define XCHAL_CP6_SA_ALIGN 1 +# define XCHAL_CP7_SA_SIZE 0 +# define XCHAL_CP7_SA_ALIGN 1 +#endif + +/* Indexing macros: */ + +#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE +#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ +#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN +#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ +#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ + +/* Link-time HAL global variables that report coprocessor numbers by name + * (names are case-preserved from the original TIE): + */ + + #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +# define _XCJOIN(a,b) a ## b +# define XCJOIN(a,b) _XCJOIN(a,b) +# ifdef XCHAL_CP0_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP0_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP0_IDENT); +# endif +# ifdef XCHAL_CP1_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP1_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP1_IDENT); +# endif +# ifdef XCHAL_CP2_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP2_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP2_IDENT); +# endif +# ifdef XCHAL_CP3_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP3_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP3_IDENT); +# endif +# ifdef XCHAL_CP4_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP4_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP4_IDENT); +# endif +# ifdef XCHAL_CP5_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP5_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP5_IDENT); +# endif +# ifdef XCHAL_CP6_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP6_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP6_IDENT); +# endif +# ifdef XCHAL_CP7_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP7_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP7_IDENT); +# endif +#endif + +/* Derived ******************************************************************/ + +#if XCHAL_HAVE_BE +# define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, + * msb-first */ +# define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, + * 1st byte */ +# define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, + * 2nd byte */ +#else +# define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, + * lsb-first */ +# define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, + * 1st byte */ +# define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, + * 2nd byte */ +#endif + +/* Belongs in xtensa/hal.h: */ + +#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ + +/* Because information as to exactly which hardware version is targeted + * by a given software build is not always available, compile-time HAL + * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ + +#if XCHAL_HW_CONFIGID_RELIABLE +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +#else +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ + : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ + : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ + ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +#endif + +/* Specific errata: */ + +/* Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; + * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): + */ + +#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN \ + (XCHAL_HAVE_XEA1 && \ + (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 || \ + XCHAL_HW_RELEASE_AT(1050,0))) + +/* Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. + * Applies to specific set of configuration options. + * Part of the workaround is to add ISYNC at certain points in the code. + * The workaround gated by this macro can be disabled if not needed, e.g. if + * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. + */ + +#if (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ + XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ + XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ + XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453)) +# define XCHAL_ERRATUM_453 1 +#else +# define XCHAL_ERRATUM_453 0 +#endif + +/* Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 + * Applies to specific set of configuration options. + * Workaround is to add MEMWs after at most 8 cache WB instructions + */ + +#if (((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ + (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2)) && \ + XCHAL_DCACHE_IS_WRITEBACK && \ + XCHAL_HAVE_AXI && \ + XCHAL_HAVE_PIF_WR_RESP && \ + XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497)) +# define XCHAL_ERRATUM_497 1 +#else +# define XCHAL_ERRATUM_497 0 +#endif + +#endif /*__ARCH_XTENSA_INCUDE_XTENSA_CORE_H*/ diff --git a/arch/xtensa/include/xtensa/xtensa_corebits.h b/arch/xtensa/include/xtensa/xtensa_corebits.h new file mode 100644 index 00000000000..24f92d9a586 --- /dev/null +++ b/arch/xtensa/include/xtensa/xtensa_corebits.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/xtensa/include/xtensa/xtensa_corebits.h + * Xtensa Special Register field positions, masks, values. + * NOTE: This file may be processor configuration dependent. + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Tensilica Inc. + * + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H +#define __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EXCCAUSE register fields: */ + +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3f + +/* EXCCAUSE register values: + * + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ + +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10-11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ +/* Reserved 19 *//* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ +/* Reserved 27 *//* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ +/* Reserved 30-31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ +# define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ +# define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ +# define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ +# define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ +# define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ +# define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ +# define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ +# define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ +/* Reserved 40..63 */ + +/* PS register fields: */ + +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK + +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)< + * + * Derives from logic originally provided by Tensilica Inc. + * + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H +#define __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Special registers: */ + +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define LITBASE 5 +#define SCOMPARE1 12 +#define ACCLO 16 +#define ACCHI 17 +#define MR_0 32 +#define MR_1 33 +#define MR_2 34 +#define MR_3 35 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define PTEVADDR 83 +#define RASID 90 +#define ITLBCFG 91 +#define DTLBCFG 92 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEATTR 98 +#define ATOMCTL 99 +#define DDR 104 +#define MECR 110 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define CONFIGID0 176 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define CONFIGID1 208 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTREAD INTERRUPT /* Alternate name for backward compatibility */ +#define INTSET INTERRUPT /* Alternate name for backward compatibility */ +#define INTCLEAR 227 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ + +#define MR 32 +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 +#define MISC_REG 244 + +/* Tensilica-defined user registers: */ + +#if 0 +/*#define ... 21..24 */ /* (545CK) */ +/*#define ... 140..143 */ /* (545CK) */ +#define EXPSTATE 230 /* Diamond */ +#define THREADPTR 231 /* threadptr option */ +#define FCR 232 /* FPU */ +#define FSR 233 /* FPU */ +#define AE_OVF_SAR 240 /* HiFi2 */ +#define AE_BITHEAD 241 /* HiFi2 */ +#define AE_TS_FTS_BU_BP 242 /* HiFi2 */ +#define AE_SD_NO 243 /* HiFi2 */ +#define VSAR 240 /* VectraLX */ +#define ROUND_LO 242 /* VectraLX */ +#define ROUND_HI 243 /* VectraLX */ +#define CBEGIN 246 /* VectraLX */ +#define CEND 247 /* VectraLX */ +#endif + +#endif /* __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H */ diff --git a/arch/xtensa/src/.gitignore b/arch/xtensa/src/.gitignore new file mode 100644 index 00000000000..8d209f76a44 --- /dev/null +++ b/arch/xtensa/src/.gitignore @@ -0,0 +1,4 @@ +/.depend +/Make.dep +/board +/chip diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile new file mode 100644 index 00000000000..e6f288ebc5d --- /dev/null +++ b/arch/xtensa/src/Makefile @@ -0,0 +1,188 @@ +############################################################################ +# arch/xtensa/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include chip/Make.defs + +ifeq ($(CONFIG_ARCH_FAMILY_LX6),y) +ARCH_SUBDIR = lx6 +endif + +CPPFLAGS += $(EXTRADEFINES) +CFLAGS += $(EXTRADEFINES) +CXXFLAGS += $(EXTRADEFINES) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src + NUTTX = $(TOPDIR)\nuttx$(EXEEXT) + CFLAGS += -I$(ARCH_SRCDIR)\chip + CFLAGS += -I$(ARCH_SRCDIR)\common + CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)\sched +else + ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" + CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}" +else + NUTTX = $(TOPDIR)/nuttx$(EXEEXT) + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)/sched +endif +endif + +HEAD_AOBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +HEAD_COBJ = $(HEAD_CSRC:.c=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_AOBJ) $(HEAD_COBJ) + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# Override in Make.defs if linker is not 'ld' + +LDSTARTGROUP ?= --start-group +LDENDGROUP ?= --end-group + +LDFLAGS += $(ARCHSCRIPT) +EXTRA_LIBS ?= +LINKLIBS ?= + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BOARDMAKE = $(if $(wildcard .\board\Makefile),y,) + LIBPATHS += -L"$(TOPDIR)\lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board" +endif + +else + BOARDMAKE = $(if $(wildcard ./board/Makefile),y,) + +ifeq ($(WINTOOL),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}" +endif + +else + LIBPATHS += -L"$(TOPDIR)/lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board" +endif +endif +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif + +LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +VPATH = chip:common:$(ARCH_SUBDIR) + +all: $(STARTUP_OBJS) libarch$(LIBEXT) + +.PHONY: board/libboard$(LIBEXT) + +$(AOBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(HEAD_COBJ): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libarch$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) + +nuttx$(EXEEXT): $(STARTUP_OBJS) board/libboard$(LIBEXT) + @echo "LD: nuttx" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(STARTUP_OBJS) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX)$(EXEEXT) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target + +export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup"; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi + +# Dependencies + +.depend: Makefile chip/Make.defs $(SRCS) +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend +endif + $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ + "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean +endif + $(call DELFILE, libarch$(LIBEXT)) + $(call CLEAN) + +distclean: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h new file mode 100644 index 00000000000..3065911cf0c --- /dev/null +++ b/arch/xtensa/src/common/xtensa.h @@ -0,0 +1,320 @@ +/**************************************************************************** + * arch/xtensa/common/xtensa.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bring-up debug configurations. These are here (vs defconfig) + * because these should only be controlled during low level + * board bring-up and not part of normal platform configuration. + */ + +#undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */ +#undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */ +#undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */ +#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ +#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0 +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# undef CONFIG_RAMLOG_CONSOLE +#else +# if defined(CONFIG_RAMLOG_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# elif defined(CONFIG_DEV_LOWCONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* If some other device is used as the console, then the serial driver may + * still be needed. Let's assume that if the upper half serial driver is + * built, then the lower half will also be needed. There is no need for + * the early serial initialization in this case. + */ + +#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) +# define USE_SERIALDRIVER 1 +#endif + +/* Check if an interrupt stack size is configured */ + +#ifndef CONFIG_ARCH_INTERRUPTSTACK +# define CONFIG_ARCH_INTERRUPTSTACK 0 +#endif + +/* In the XTENSA model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. + */ + +#define xtensa_savestate(regs) xtensa_copystate(regs, (uint32_t*)CURRENT_REGS) +#define xtensa_restorestate(regs) do { CURRENT_REGS = regs; } while (0) + +/* Register access macros */ + +# define getreg8(a) (*(volatile uint8_t *)(a)) +# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +# define getreg16(a) (*(volatile uint16_t *)(a)) +# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +# define getreg32(a) (*(volatile uint32_t *)(a)) +# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*xtensa_vector_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +#ifdef CONFIG_SMP +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +int up_cpu_index(void); /* See include/nuttx/arch.h */ +extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +# define CURRENT_REGS (g_current_regs[up_cpu_index()]) + +#else + +extern volatile uint32_t *g_current_regs[1]; +# define CURRENT_REGS (g_current_regs[0]) + +#endif + +/* This is the beginning of heap as provided from *_head.S. This is the + * first address in DRAM after the loaded program+bss+idle stack. The end + * of the heap is CONFIG_RAM_END + */ + +extern uint32_t g_idle_topstack; + +/* Address of the saved user stack pointer */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +extern void g_intstackbase; +#endif + +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in the + * following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declaration extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it is + * not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _init_start; /* Start of initialization logic */ +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End+1 of .text + .rodata */ +extern const uint32_t _data_loaddr; /* Start of .data in FLASH */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ +#ifdef CONFIG_ARCH_RAMFUNCS +extern uint32_t _sramfunc; /* Start of ramfuncs */ +extern uint32_t _eramfunc; /* End+1 of ramfuncs */ +extern uint32_t _ramfunc_loadaddr; /* Start of ramfuncs in FLASH */ +extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ +#endif /* CONFIG_ARCH_RAMFUNCS */ +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* Common Functions *********************************************************/ +/* Common functions defined in arch/xtensa/src/common. These may be replaced + * with chip-specific functions of the same name if needed. See also + * functions prototyped in include/nuttx/arch.h. + */ + +/* Atomic modification of registers */ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + +/* Context switching */ + +void xtensa_copystate(uint32_t *dest, uint32_t *src); + +/* Serial output */ + +void up_puts(const char *str); +void up_lowputs(const char *str); + +/* Defined in drivers/lowconsole.c */ + +#ifdef CONFIG_DEV_LOWCONSOLE +void lowconsole_init(void); +#else +# define lowconsole_init() +#endif + +/* Debug */ + +#ifdef CONFIG_ARCH_STACKDUMP +void xtensa_dumpstate(void); +#else +# define xtensa_dumpstate() +#endif + +/* Common XTENSA functions */ +/* IRQs */ + +uint32_t *xtensa_int_decode(uint32_t *regs); +uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); + +/* Software interrupt handler */ + +int xtensa_swint(int irq, FAR void *context); + +/* Synchronous context switching */ + +int xtensa_context_save(uint32_t *regs); +void xtensa_context_restore(uint32_t *regs) noreturn_function; + +/* Signals */ + +void xtensa_sigdeliver(void); + +/* Chip-specific functions **************************************************/ +/* Chip specific functions defined in arch/xtensa/src/ */ +/* IRQs */ + +void xtensa_irq_initialize(void); +bool xtensa_pending_irq(int irq); +void xtensa_clrpend_irq(int irq); + +/* DMA */ + +#ifdef CONFIG_ARCH_DMA +void weak_function xtensa_dma_initialize(void); +#endif + +/* Memory management */ + +#if CONFIG_MM_REGIONS > 1 +void xtensa_add_region(void); +#else +# define xtensa_add_region() +#endif + +/* Serial output */ + +void up_lowputc(char ch); +#if CONFIG_NFILE_DESCRIPTORS > 0 +void xtensa_earlyserialinit(void); +void xtensa_serial_initialize(void); +#else +# define xtensa_earlyserialinit() +# define xtensa_serial_initialize() +#endif + +/* System timer */ + +void xtensa_timer_initialize(void); + +/* Network */ + +#ifdef CONFIG_NET +void up_netinitialize(void); +#else +# define up_netinitialize() +#endif + +/* USB */ + +#ifdef CONFIG_USBDEV +void up_usbinitialize(void); +void up_usbuninitialize(void); +#else +# define up_usbinitialize() +# define up_usbuninitialize() +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_H */ diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c new file mode 100644 index 00000000000..98c5562d924 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_assert.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "sched/sched.h" +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* USB trace dumping */ + +#ifndef CONFIG_USBDEV_TRACE +# undef CONFIG_ARCH_USBDUMP +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_assert + ****************************************************************************/ + +static void xtensa_assert(int errorcode) noreturn_function; +static void xtensa_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (CURRENT_REGS || this_task()->pid == 0) + { + (void)up_irq_save(); + for (; ; ) + { +#ifdef CONFIG_ARCH_LEDS + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + _alert("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + + xtensa_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + xtensa_assert(EXIT_FAILURE); +} diff --git a/arch/xtensa/src/common/xtensa_attr.h b/arch/xtensa/src/common/xtensa_attr.h new file mode 100644 index 00000000000..72cce41da91 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_attr.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_irq.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFN_ATTR + +/* Normally, the linker script will put all code and rodata in flash, + * and all variables in shared RAM. These macros can be used to redirect + * particular functions/variables to other memory regions. + */ + +/* Forces code into IRAM instead of flash */ + +#define IRAM_ATTR __attribute__((section(".iram1"))) + +/* Forces data into DRAM instead of flash */ + +#define DRAM_ATTR __attribute__((section(".dram1"))) + +/* Forces code into RTC fast memory */ + +#define RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) + +/* Forces data into RTC slow memory + * Any variable marked with this attribute will keep its value + * during a deep sleep / wake cycle. */ + +#define RTC_DATA_ATTR __attribute__((section(".rtc.data"))) + +/* Forces read-only data into RTC slow memory + * Makes constant data available to RTC wake stubs. + */ + +#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */ diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c new file mode 100644 index 00000000000..82eb5e30c9d --- /dev/null +++ b/arch/xtensa/src/common/xtensa_blocktask.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_blocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of + * the ready to run list must be stopped. Save its context + * and move it to the inactive list specified by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally + * the task at the head of the list). It most be + * stopped, its context saved and moved into one of the + * waiting task lists. It it was the task at the head + * of the ready-to-run list, then a context to the new + * ready to run task must be performed. + * task_state: Specifies which waiting task list should be + * hold the blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && + (tcb->task_state <= LAST_READY_TO_RUN_STATE)); + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the ready-to-run + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the user C context into the TCB at the (old) head of the + * ready-to-run Task list. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S new file mode 100644 index 00000000000..c3c08352320 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_context.S @@ -0,0 +1,421 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_context.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_context.S" + +/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES + * + * Low-level Call0 functions for handling generic context save and restore + * of registers not specifically addressed by the interrupt vectors and + * handlers. Those registers (not handled by these functions) are PC, PS, + * A0, A1 (SP). + * + * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- + * save regs (A12-A15), which is always the case if the handlers are coded in C. + * However A12, A13 are made available as scratch registers for interrupt dispatch + * code, so are presumed saved anyway, and are always restored even in Call0 ABI. + * Only A14, A15 are truly handled as callee-save regs. + * + * Because Xtensa is a configurable architecture, this port supports all user + * generated configurations (except restrictions stated in the release notes). + * This is accomplished by conditional compilation using macros and functions + * defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + * Only the processor state included in your configuration is saved and restored, + * including any processor state added by user configuration options or TIE. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided +#define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: _xtensa_context_save + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * This function saves Xtensa processor state: xtensa_context_save + * saves all registers except PC, PS, A0, A1 (SP), and A2 + * + * This function is called directly by interrupt handling logic and from + * xtensa_context_save() below with interrupts disabled. In either calling + * context, caller saves saves PC, PS, A0, A1 (SP), and A2. This + * logic also executes indirectly from xtena_context_save() by falling + * through from above. + * + * The counterpart to this function is _xtensa_context_restore(). + * + * Entry Conditions: + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * - Other processor state except PC, PS, A0, A1 (SP), and A2 are as at + * the point of interruption. + * + * Exit conditions: + * - A0 = Return address in caller. + * - A2, A12-A15 as at entry (preserved). + * + * Assumptions: + * - Caller is expected to have saved PC, PS, A0, A1 (SP), and A2. + * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). + * + ****************************************************************************/ + + .global _xtensa_context_save + .type _xtensa_context_save, @function + + .align 4 + .literal_position + .align 4 + +_xtensa_context_save: + + s32i a2, a2, (4 * REG_A2) + s32i a3, a2, (4 * REG_A3) + s32i a4, a2, (4 * REG_A4) + s32i a5, a2, (4 * REG_A5) + s32i a6, a2, (4 * REG_A6) + s32i a7, a2, (4 * REG_A7) + s32i a8, a2, (4 * REG_A8) + s32i a9, a2, (4 * REG_A9) + s32i a10, a2, (4 * REG_A10) + s32i a11, a2, (4 * REG_A11) + + /* Call0 ABI callee-saved regs a12-15 */ + + s32i a12, a2, (4 * REG_A12) + s32i a13, a2, (4 * REG_A13) + s32i a14, a2, (4 * REG_A14) + s32i a15, a2, (4 * REG_A15) + + rsr a3, SAR + s32i a3, a2, (4 * REG_SAR) + +#ifdef XCHAL_HAVE_LOOPS + rsr a3, LBEG + s32i a3, a2, (4 * REG_LBEG) + rsr a3, LEND + s32i a3, a2, (4 * REG_LEND) + rsr a3, LCOUNT + s32i a3, a2, (4 * REG_LCOUNT) +#endif + +#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) + mov a9, a0 /* Preserve ret addr */ + #endif + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* To spill the reg windows, temp. need pre-interrupt stack ptr and + * a4-15. Need to save a9,12,13 temporarily (in frame temps) and + * recover originals. Interrupts need to be disabled below + * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions + * disabled (assured by PS.EXCM == 1). + */ + + s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ + s32i a13, a2, (4 * REG_TMP1) + s32i a9, a2, (4 * REG_TMP2) + +#ifdef CONFIG_XTENSA_USE_OVLY + /* Save the overlay state if we are supporting overlays. Since we just + * saved three registers, we can conveniently use them here. Note that + * as of now, overlays only work for windowed calling ABI. + */ + +#error Overly support is not implemented +#endif + + l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */ + l32i a13, a2, (4 * REG_A13) + l32i a9, a2, (4 * REG_A9) + +#warning REVISIT: The following is probably not correct due to changes in registers + addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */ + call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) + l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */ + l32i a13, sp, (4 * REG_TMP1) + l32i a9, sp, (4 * REG_TMP2) +#endif + +#if XTENSA_EXTRA_SA_SIZE > 0 + /* NOTE: Normally the xthal_save_extra_nw macro only affects address + * registers a2-a5. It is theoretically possible for Xtensa processor + * designers to write TIE that causes more address registers to be + * affected, but it is generally unlikely. If that ever happens, + * more registers need to be saved/restored around this macro invocation. + * Here we assume a9,12,13 are preserved. + * Future Xtensa tools releases might limit the regs that can be affected. + */ + + addi a2, a2, (4 * REG_EXTRA) /* Where to save it */ +#if XTENSA_EXTRA_SA_ALIGN > 16 + movi a3, -XTENSA_EXTRA_SA_ALIGN + and a2, a2, a3 /* Align dynamically >16 bytes */ +#endif + call0 xthal_save_extra_nw /* Destroys a0,2,3,4,5 */ +#endif + +#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) + mov a0, a9 /* Retrieve ret addr */ +#endif + + ret + +/**************************************************************************** + * Name: xtensa_context_save + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * This functions implements the moral equivalent of setjmp(). It is + * called from user code (with interrupts disabled) to save the current + * state of the running thread. This function always returns zero. + * However, it sets the saved value of the return address (A2) to 1. + * If the thread is restarted via _xtensa_contest_restore or + * xtensa_context_restore, it will appear as a second return from + * xtensa_context_save but with the returned value of 1 to distinguish + * the two cases. + * + * The counterpart to this function is xtensa_context_restore(). + * + * Entry Conditions: + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * + * Exit conditions: + * - A0 = Return address in caller. + * - A2 = 0 + * + * Assumptions: + * - Interrupts are disabled. + * + ****************************************************************************/ + + .global xtensa_context_save + .type xtensa_context_save, @function + + .align 4 + .literal_position + .align 4 + +xtensa_context_save: + + /* Set up for call to _xtensa_context_save() */ + + rsr a12, PS /* Save callee's PS */ + s32i a12, a2, (4 * REG_PS) + s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ + + s32i a0, a2, (4 * REG_A0) /* Save callee's a0 */ + s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ + movi a12, 1 /* Set saved A2 to 1 */ + s32i a12, a2, (4 * REG_A2) + + /* Save the rest of the processor state */ + + call0 _xtensa_context_save /* Save full register state */ + + /* Recover the return address and return zero */ + + l32i a0, a2, (4 * REG_A0) /* Recover return addess */ + movi a2, 0 /* Return zero */ + ret + +/**************************************************************************** + * Name: _xtensa_context_restore + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * These functions restores Xtensa processor state and differ in which + * registers are saved: _xtensa_context_restore() restores all registers + * except PC, PS, A0, and A2 + * + * The caller is responsible for restoring PC, PS, A0, and A2. + * + * _xtensa_context_save is the counterpart to this function. + * + * Entry Conditions: + * - A0 = Return address in caller. + * - A2 = Pointer to the processor state save area + * + * Exit conditions: + * - A0 = Return address in caller. + * - Other registers are restored as detailed above (including A1 and A2). + * + ****************************************************************************/ + + .global _xtensa_context_restore + .type _xtensa_context_restore,@function + + .align 4 + .literal_position + .align 4 + +_xtensa_context_restore: + +#if XTENSA_EXTRA_SA_SIZE > 0 + /* NOTE: Normally the xthal_restore_extra_nw macro only affects address + * registers a2-a5. It is theoretically possible for Xtensa processor + * designers to write TIE that causes more address registers to be + * affected, but it is generally unlikely. If that ever happens, + * more registers need to be saved/restored around this macro invocation. + * Here we only assume a13 is preserved. + * Future Xtensa tools releases might limit the regs that can be affected. + */ + + mov a13, a0 /* Preserve ret addr */ + addi a2, a2, (4 * REG_EXTRA) /* Where to find it */ + +#if XTENSA_EXTRA_SA_ALIGN > 16 + movi a3, -XTENSA_EXTRA_SA_ALIGN + and a2, a2, a3 /* Align dynamically >16 bytes */ +#endif + call0 xthal_restore_extra_nw /* Destroys a0,2,3,4,5 */ + mov a0, a13 /* Retrieve ret addr */ +#endif + +#ifdef XCHAL_HAVE_LOOPS + l32i a2, a2, (4 * REG_LBEG) + l32i a3, a2, (4 * REG_LEND) + wsr a2, LBEG + l32i a2, a2, (4 * REG_LCOUNT) + wsr a3, LEND + wsr a2, LCOUNT +#endif + +#ifdef CONFIG_XTENSA_USE_OVLY + /* If we are using overlays, this is a good spot to check if we need + * to restore an overlay for the incoming task. Here we have a bunch + * of registers to spare. Note that this step is going to use a few + * bytes of storage below SP (SP-20 to SP-32) if an overlay is going + * to be restored. + */ + +#error Overly support is not implemented +#endif + + l32i a3, a2, (4 * REG_SAR) + l32i sp, a2, (4 * REG_A1) + wsr a3, SAR + l32i a3, a2, (4 * REG_A3) + l32i a4, a2, (4 * REG_A4) + l32i a5, a2, (4 * REG_A5) + l32i a6, a2, (4 * REG_A6) + l32i a7, a2, (4 * REG_A7) + l32i a8, a2, (4 * REG_A8) + l32i a9, a2, (4 * REG_A9) + l32i a10, a2, (4 * REG_A10) + l32i a11, a2, (4 * REG_A11) + + /* Call0 ABI callee-saved regs a12-15 */ + + l32i a12, a2, (4 * REG_A12) + l32i a13, a2, (4 * REG_A13) + l32i a14, a2, (4 * REG_A14) + l32i a15, a2, (4 * REG_A15) + + /* Finally, restore A2 with the correct value */ + + l32i a2, a2, (4 * REG_A2) + + ret + +/**************************************************************************** + * Name: xtensa_context_restore + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * This functions implements the moral equivalent of longjmp(). It is + * called from user code (with interrupts disabled) to restor the current + * state of the running thread. This function always returns 1 because + * the saved value of A2 was set to 1 in xtensa_context_save(). + * + * The counterpart to this function is xtensa_context_save(). + * + * Entry Conditions: + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * + * Exit conditions: + * NOTE: That this function does NOT return to the caller but rather + * to a new threading context. + * + * Assumptions: + * - Interrupts are disabled. + * + ****************************************************************************/ + + .global xtensa_context_restore + .type xtensa_context_restore, @function + + .align 4 + .literal_position + .align 4 + +xtensa_context_restore: + + /* Restore the processor state */ + + call0 _xtensa_context_restore /* Restore full register state */ + + /* Restore PC, PS, A0, and A2. */ + + l32i a0, a2, (4 * REG_PS) /* Restore PS */ + wsr a0, PS + l32i a0, a2, (4 * REG_PC) /* Set up for RFE */ + rsr a0, EPC + l32i a0, a2, (4 * REG_A0) /* Restore a0 */ + l32i a2, a2, (4 * REG_A2) /* Restore A2 */ + rfe /* And return from "exception" */ diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S new file mode 100644 index 00000000000..7e9843c7960 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_coproc.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_coproc.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + diff --git a/arch/xtensa/src/common/xtensa_copystate.c b/arch/xtensa/src/common/xtensa_copystate.c new file mode 100644 index 00000000000..1e8cfa8c14a --- /dev/null +++ b/arch/xtensa/src/common/xtensa_copystate.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_copystate.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void xtensa_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + + /* In the XTENSA model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ + + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } +} + diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c new file mode 100644 index 00000000000..5e1ca5a4474 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_createstack.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + */ + +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size); + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + size_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* XTENSA uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The XTENSA stack must be aligned at word (4 byte) boundaries; for + * floating point use, the stack must be aligned to 8-byte addresses. + * If necessary top_of_stack must be rounded down to the next + * boundary to meet these alignment requirements. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c new file mode 100644 index 00000000000..74de6d74a55 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -0,0 +1,229 @@ +/**************************************************************************** + * arch/xtensa/src/mips32/xtensa_dumpstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifdef CONFIG_DEBUG_ALERT + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_getsp + ****************************************************************************/ + +/* I don't know if the builtin to get SP is enabled */ + +static inline uint32_t xtensa_getsp(void) +{ + register uint32_t sp; +#warning Missing logic + return sp; +} + +/**************************************************************************** + * Name: xtensa_stackdump + ****************************************************************************/ + +static void xtensa_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + +/**************************************************************************** + * Name: xtensa_registerdump + ****************************************************************************/ + +static inline void xtensa_registerdump(void) +{ + uint32_t *regs = (uint32_t *)CURRENT_REGS; /* Don't need volatile here */ + + /* Are user registers available from interrupt processing? */ + + if (regs != NULL) + { + _alert(" PC: %08lx PS: %08lx\n", + (unsigned long)regs[REG_PC], (unsigned long)regs[REG_PS]); + _alert(" A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", + (unsigned long)regs[REG_A0], (unsigned long)regs[REG_A1], + (unsigned long)regs[REG_A2], (unsigned long)regs[REG_A3]); + _alert(" A4: %08lx A5: %08lx A6: %08lx A7: %08lx\n", + (unsigned long)regs[REG_A4], (unsigned long)regs[REG_A5], + (unsigned long)regs[REG_A6], (unsigned long)regs[REG_A7]); + _alert(" A8: %08lx A9: %08lx A10: %08lx A11: %08lx\n", + (unsigned long)regs[REG_A8], (unsigned long)regs[REG_A9], + (unsigned long)regs[REG_A10], (unsigned long)regs[REG_A11]); + _alert(" A12: %08lx A13: %08lx A14: %08lx A15: %08lx\n", + (unsigned long)regs[REG_A12], (unsigned long)regs[REG_A13], + (unsigned long)regs[REG_A14], (unsigned long)regs[REG_A15]); + _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", + (unsigned long)regs[REG_SAR], (unsigned long)regs[REG_EXCCAUSE], + (unsigned long)regs[REG_EXCVADDR]); +#ifdef XCHAL_HAVE_LOOPS + _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", + (unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND], + (unsigned long)regs[REG_LCOUNT]); +#endif +#ifndef CONFIG_XTENSA_CALL0_ABI + _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", + (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1], + (unsigned long)regs[REG_TMP2]); +#endif + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_dumpstate + ****************************************************************************/ + +void xtensa_dumpstate(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t sp = xtensa_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#warning REVISIT interrupt stack +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + xtensa_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = g_intstackbase; + _alert("sp: %08x\n", sp); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 + _alert("ERROR: Stack pointer is not within allocated stack\n"); +#endif + } + else + { + xtensa_stackdump(sp, ustackbase); + } + + /* Then dump the registers (if available) */ + + xtensa_registerdump(); +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/xtensa/src/common/xtensa_etherstub.c b/arch/xtensa/src/common/xtensa_etherstub.c new file mode 100644 index 00000000000..9174a0e6d68 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_etherstub.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_etherstub.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_netinitialize (stub) + * + * Description: + * This is a stub version os up_netinitialize. Normally, up_netinitialize + * is defined in board/xyz_network.c for board-specific Ethernet + * implementations, or chip/xyx_ethernet.c for chip-specific Ethernet + * implementations. The stub version here is used in the corner case where + * the network is enable yet there is no Ethernet driver to be initialized. + * In this case, up_initialize will still try to call up_netinitialize() + * when one does not exist. This corner case would occur if, for example, + * only a USB network interface is being used or perhaps if a SLIP is + * being used). + * + * Use of this stub is deprecated. The preferred mechanism is to use + * CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in + * up_initialize(). Then this stub would not be needed. + * + ****************************************************************************/ + +void up_netinitialize(void) +{ +} diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c new file mode 100644 index 00000000000..e6c64aaecd2 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_exit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_DUMP_ON_EXIT +#include +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _xtensa_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _xtensa_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +{ +#if CONFIG_NFILE_DESCRIPTORS > 0 + FAR struct filelist *filelist; +#if CONFIG_NFILE_STREAMS > 0 + FAR struct streamlist *streamlist; +#endif + int i; +#endif + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + +#if CONFIG_NFILE_DESCRIPTORS > 0 + filelist = tcb->group->tg_filelist; + for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + { + struct inode *inode = filelist->fl_files[i].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefs); + } + } +#endif + +#if CONFIG_NFILE_STREAMS > 0 + streamlist = tcb->group->tg_streamlist; + for (i = 0; i < CONFIG_NFILE_STREAMS; i++) + { + struct file_struct *filep = &streamlist->sl_streams[i]; + if (filep->fs_fd >= 0) + { +#if CONFIG_STDIO_BUFFER_SIZE > 0 + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); +#else + sinfo(" fd=%d\n", filep->fs_fd); +#endif + } + } +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void _exit(int status) +{ + struct tcb_s *tcb; + + /* Disable interrupts. They will be restored when the next task is + * started. + */ + + (void)up_irq_save(); + + sinfo("TCB=%p exiting\n", this_task()); + +#ifdef CONFIG_DUMP_ON_EXIT + sinfo("Other tasks:\n"); + sched_foreach(_xtensa_dumponexit, NULL); +#endif + + /* Destroy the task at the head of the ready to run list. */ + + (void)task_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + (void)group_addrenv(tcb); +#endif + + /* Then switch contexts */ + + xtensa_context_restore(tcb->xcp.regs); + + /* xtensa_full_context_restore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} diff --git a/arch/xtensa/src/common/xtensa_idle.c b/arch/xtensa/src/common/xtensa_idle.c new file mode 100644 index 00000000000..894cdb606b5 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_idle.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_idle.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = enter_critical_section(); + leave_critical_section(flags); +#endif +#endif +} diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c new file mode 100644 index 00000000000..2041548b175 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_initialize.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_calibratedelay + * + * Description: + * Delay loops are provided for short timing loops. This function, if + * enabled, will just wait for 100 seconds. Using a stopwatch, you can + * can then determine if the timing loops are properly calibrated. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG_FEATURES) +static void up_calibratedelay(void) +{ + int i; + + _warn("Beginning 100s delay\n"); + for (i = 0; i < 100; i++) + { + up_mdelay(1000); + } + + _warn("End 100s delay\n"); +} +#else +# define up_calibratedelay() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ +#ifdef CONFIG_SMP + int i; + + /* Initialize global variables */ + + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + g_current_regs[i] = NULL; + } +#else + CURRENT_REGS = NULL; +#endif + + /* Calibrate the timing loop */ + + up_calibratedelay(); + + /* Add any extra memory fragments to the memory manager */ + + xtensa_add_region(); + + /* Initialize the interrupt subsystem */ + + xtensa_irq_initialize(); + +#ifdef CONFIG_PM + /* Initialize the power management subsystem. This MCU-specific function + * must be called *very* early in the initialization sequence *before* any + * other device drivers are initialized (since they may attempt to register + * with the power management subsystem). + */ + + up_pminitialize(); +#endif + +#ifdef CONFIG_ARCH_DMA + /* Initialize the DMA subsystem if the weak function xtensa_dma_initialize + * has been brought into the build + */ + +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (xtensa_dma_initialize) +#endif + { + xtensa_dma_initialize(); + } +#endif + + /* Initialize the system timer interrupt */ + +#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) + xtensa_timer_initialize(); +#endif + + /* Register devices */ + +#if CONFIG_NFILE_DESCRIPTORS > 0 + +#if defined(CONFIG_DEV_NULL) + devnull_register(); /* Standard /dev/null */ +#endif + +#if defined(CONFIG_DEV_RANDOM) + devrandom_register(); /* Standard /dev/random */ +#endif + +#if defined(CONFIG_DEV_URANDOM) + devurandom_register(); /* Standard /dev/urandom */ +#endif + +#if defined(CONFIG_DEV_ZERO) + devzero_register(); /* Standard /dev/zero */ +#endif + +#if defined(CONFIG_DEV_LOOP) + loop_register(); /* Standard /dev/loop */ +#endif +#endif /* CONFIG_NFILE_DESCRIPTORS */ + +#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \ + defined(CONFIG_DRIVER_NOTE) + note_register(); /* Non-standard /dev/note */ +#endif + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + xtensa_serial_initialize(); +#endif + + /* Initialize the console device driver (if it is other than the standard + * serial driver). + */ + +#if defined(CONFIG_DEV_LOWCONSOLE) + lowconsole_init(); +#elif defined(CONFIG_CONSOLE_SYSLOG) + syslog_console_init(); +#elif defined(CONFIG_RAMLOG_CONSOLE) + ramlog_consoleinit(); +#endif + +#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1) + /* Register the master pseudo-terminal multiplexor device */ + + (void)ptmx_register(); +#endif + + /* Early initialization of the system logging device. Some SYSLOG channel + * can be initialized early in the initialization sequence because they + * depend on only minimal OS initialization. + */ + + syslog_initialize(SYSLOG_INIT_EARLY); + +#if defined(CONFIG_CRYPTO) + /* Initialize the HW crypto and /dev/crypto */ + + up_cryptoinitialize(); +#endif + +#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV) + devcrypto_register(); +#endif + +#ifndef CONFIG_NETDEV_LATEINIT + /* Initialize the network */ + + up_netinitialize(); +#endif + +#ifdef CONFIG_NETDEV_LOOPBACK + /* Initialize the local loopback device */ + + (void)localhost_initialize(); +#endif + +#ifdef CONFIG_NET_TUN + /* Initialize the TUN device */ + + (void)tun_initialize(); +#endif + +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + + /* Initialize USB -- device and/or host */ + + up_usbinitialize(); + board_autoled_on(LED_IRQSENABLED); +} diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c new file mode 100644 index 00000000000..cce4e0c467c --- /dev/null +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_initialstate.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB has been created. This + * function is called to initialize the processor specific portions of the + * new TCB. + * + * This function must setup the intial architecture registers and/or stack + * so that execution will begin at tcb->start on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; +#if 0 /* REVISIT */ +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + uint32_t *ptr; +#endif +#endif /* REVISIT */ + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Set initial values of registers */ + + xcp->regs[REG_PC] = (uint32_t)tcb->start; /* Task entrypoint */ + xcp->regs[REG_A0] = 0; /* To terminate GDB backtrace */ + xcp->regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; /* Physical top of stack frame */ + + /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user + * mode. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + xcp->regs[REG_PS] = PS_UM | PS_EXCM; + +#else + /* For windowed ABI set WOE and CALLINC (pretend task was 'call4'd). */ + + xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); +#endif + +#warning REVISIT co-processor support +#if 0 /* REVISIT */ +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + /* Init the coprocessor save area (see xtensa_context.h) + * + * No access to TCB here, so derive indirectly. Stack growth is top to bottom. + * //ptr = (uint32_t *) xMPUSettings->coproc_area; + */ + + ptr = (uint32_t *)(((uint32_t)tcb->adj_stack_ptr - XT_CP_SIZE) & ~0xf); + ptr[0] = 0; + ptr[1] = 0; + ptr[2] = (((uint32_t)ptr) + 12 + XTENSA_TOTAL_SA_ALIGN - 1) & -XTENSA_TOTAL_SA_ALIGN; +#endif +#endif /* REVISIT */ +} diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c new file mode 100644 index 00000000000..8cf096f725e --- /dev/null +++ b/arch/xtensa/src/common/xtensa_interruptcontext.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_interruptcontext.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: Return true is we are currently executing in + * the interrupt handler context on this CPU. + * + ****************************************************************************/ + +bool up_interrupt_context(void) +{ + return CURRENT_REGS != NULL; +} diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S new file mode 100644 index 00000000000..31930188197 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -0,0 +1,772 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_inthandlers.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + + .file "xtensa_inthandlers.S" + +/* NOTES on the use of 'call0' for long jumps instead of 'j': + * + * 1. This file should be assembled with the -mlongcalls option to xt-xcc. + * + * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + * distance from the call to the destination. The linker then relaxes + * it back to 'call0 dest' if it determines that dest is within range. + * This allows more flexibility in locating code without the performance + * overhead of the 'l32r' literal data load in cases where the destination + * is in range of 'call0'. There is an additional benefit in that 'call0' + * has a longer range than 'j' due to the target being word-aligned, so + * the 'l32r' sequence is less likely needed. + * + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function + * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + * + * 4. This use of 'call0' is independent of the C function call ABI. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "xtensa_macros.h" +#include "xtensa_timer.h" + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +/**************************************************************************** + * Macro extract_msb - return the input with only the highest bit set. + * + * Entry Conditions/Side Effects: + * Input : "ain" - Input value, clobbered. + * Output : "aout" - Output value, has only one bit set, MSB of "ain". + * + * The two arguments must be different AR registers. + * + ****************************************************************************/ + + .macro extract_msb aout ain +1: + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* Repeat until ain == 0 */ + addi \aout, \aout, 1 /* Return aout + 1 */ + .endm + +/**************************************************************************** + * Macro dispatch_c_isr level mask + * + * Description: + * + * This will dispatch to user handlers (if any) that are registered in the + * XTOS dispatch table (_xtos_interrupt_table). These handlers would have + * been registered by calling _xtos_set_interrupt_handler(). There is one + * exception - the timer interrupt used by the OS will not be dispatched + * to a user handler - this must be handled by the caller of this macro. + * + * Level triggered and software interrupts are automatically deasserted by + * this code. + * + * Assumptions: + * - PS.INTLEVEL is set to "level" at entry + * - PS.EXCM = 0, C calling enabled + * + * Entry Conditions/Side Effects: + * This macro will use registers a0 and a2-a6. The arguments are: + * level - interrupt level + * mask - interrupt bitmask for this level + * + ****************************************************************************/ + + .macro dispatch_c_isr level mask + + /* Get mask of pending, enabled interrupts at this level into a2. */ + +.L_xt_user_int_&level&: + rsr a2, INTENABLE + rsr a3, INTERRUPT + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 5f /* Nothing to do */ + + /* This bit of code provides a nice debug backtrace in the debugger. + * It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + * if you want to save the cycles. + * / + +#if XT_DEBUG_BACKTRACE +#ifndef CONFIG_XTENSA_CALL0_ABI + rsr a0, EPC_1 + \level - 1 /* Return address */ + movi a4, 0xC0000000 /* Constant with top 2 bits set (call size) */ + or a0, a0, a4 /* Set top 2 bits */ + addx2 a0, a4, a0 /* Clear top bit -- simulating call4 size */ +#endif +#endif + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + +#ifdef CONFIG_XTENSA_CALL0_ABI + callx0 a4 + beqz a2, 5f +#else + mov a6, a2 + callx4 a4 + beqz a6, 5f + mov a2, a6 +#endif +2: +#endif + + /* If multiple bits are set then MSB has highest priority. */ + + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ + beq a3, a4, 4f /* If timer interrupt then skip table */ + + /* Call xtensa_int_decode with, passing that address of the register save + * area as a parameter (A2). + */ + + mov a2, sp /* Argument: Top of stack = register save area */ + call0 xtensa_int_decode /* Call xtensa_int_decode */ + + /* On return from xtensa_int_decode, A2 will contain the address of the new + * register save area. Usually this would be the same as the current SP. + * But in the event of a context switch, A2 will instead refer to the TCB + * register save area. + */ + + beq a2, sp, 3f /* If timer interrupt then skip table */ + + /* Switch stacks */ +#warning REVIST: Should use register save are on stack. + + l32i a4, sp, (4 * REG_A1) /* Retrieve stack ptr and replace */ + addi sp, a4, -(4 * XCPTCONTEXT_SIZE) + +3: + j .L_xt_user_int_&level& /* Check for more interrupts */ + +4: + + .ifeq XT_TIMER_INTPRI - \level + + /* Interrupt handler for the RTOS tick timer if at this level. + * We'll be reading the interrupt state again after this call + * so no need to preserve any registers except a6 (vpri_mask). + */ + + mov a12, a6 /* Preserve a6 */ + movi a2, XTENSA_IRQ_TIMER&level& /* Arg 1: IRQ number */ + mov a3, sp /* Arg 2: Top of stack = register save area */ + call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ + mov a6, a12 /* Preserve a6 */ + .endif + + j .L_xt_user_int_&level& /* Check for more interrupts */ + +5: + /* done */ + + .endm + +/**************************************************************************** + * Macro: ps_setup + * + * Description: + * Set up PS for C, enable interrupts above this level and clear EXCM. + * + * Entry Conditions: + * level - interrupt level + * tmp - scratch register + * + * Side Effects: + * PS and scratch register modified + * + * Assumptions: + * - PS.EXCM = 1, C calling disabled + * + ****************************************************************************/ + + .macro ps_setup level tmp + +#if 0 /* Nested interrupts no yet supported */ +# ifdef CONFIG_XTENSA_CALL0_ABI + /* Disable interrupts at level and below */ + + movi \tmp, PS_INTLEVEL(\level) | PS_UM +# else + movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE +# endif +#else +# ifdef CONFIG_XTENSA_CALL0_ABI + /* Disable all low- and medium-priority interrupts. Nested are not yet + * supported. + */ + + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +# else + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +# endif +#endif + + wsr \tmp, PS + rsync + + .endm + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * LOW PRIORITY (LEVEL 1) LOW LEVEL HANDLER. + ****************************************************************************/ + +#warning REVISIT level 1 interrupt handlers + +/**************************************************************************** + * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS. + * + * C Prototype: + * void _xtensa_levelN_handler(void) + * + * Description: + * Medium priority interrupts are by definition those with priority greater + * than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled + * by setting PS.EXCM and therefore can easily support a C environment for + * handlers in C, and interact safely with NuttX. + * + * Each vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the NuttX linker script. The vector logic performs + * the minimum necessary operations before jumping to the handler via + * a CALL0 instruction. See "NOTES on the use of call0 ..." above. + * + * The corresponding handler sets up the appropriate stack frame, saves + * a few vector-specific registers and calls _xtensa_context_save() + * to save the rest of the interrupted context. It then calls the C + * logic to decode the specific interrupt source and dispatch to the + * appropriate C interrupt handler. + * + ****************************************************************************/ + +#if XCHAL_EXCM_LEVEL >= 2 + .section .iram1,"ax" + .type _xtensa_level2_handler,@function + .align 4 + +_xtensa_level2_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_2 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_2 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 2 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_2 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_2 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_2 and jumps to + * the address in EPC_2. + */ + + rfi 2 + +#endif /* XCHAL_EXCM_LEVEL >= 2 */ + +#if XCHAL_EXCM_LEVEL >= 3 + .section .iram1,"ax" + .type _xtensa_level3_handler,@function + .align 4 + +_xtensa_level3_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_3 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_3 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_3 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 3 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_3 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_3 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_3 and jumps to + * the address in EPC_3. + */ + + rfi 3 + +#endif /* XCHAL_EXCM_LEVEL >= 3 */ + +#if XCHAL_EXCM_LEVEL >= 4 + .section .iram1,"ax" + .type _xtensa_level4_handler,@function + .align 4 + +_xtensa_level4_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_4 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_4 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_4 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 4 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_4 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_4 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_4 and jumps to + * the address in EPC_4. + */ + + rfi 4 + +#endif /* XCHAL_EXCM_LEVEL >= 4 */ + +#if XCHAL_EXCM_LEVEL >= 5 + .section .iram1,"ax" + .type _xtensa_level5_handler,@function + .align 4 + +_xtensa_level5_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_5 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_5 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_5 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 5 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_5 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_5 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_5 and jumps to + * the address in EPC_5. + */ + + rfi 5 + +#endif /* XCHAL_EXCM_LEVEL >= 2 */ + +#if XCHAL_EXCM_LEVEL >= 6 + .section .iram1,"ax" + .type _xtensa_level6_handler,@function + .align 4 + +_xtensa_level6_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_6 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_6 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_6 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 6 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_6 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_6 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_6 and jumps to + * the address in EPC_6. + */ + + rfi 6 + +#endif /* XCHAL_EXCM_LEVEL >= 6 */ + +/**************************************************************************** + * HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) LOW-LEVEL HANDLERS + * + * High priority interrupts are by definition those with priorities greater + * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority + * interrupts cannot interact with the RTOS, that is they must save all regs + * they use and not call any RTOS function. + * + * A further restriction imposed by the Xtensa windowed architecture is that + * high priority interrupts must not modify the stack area even logically + * "above" the top of the interrupted stack (they need to provide their + * own stack or static save area). + * + * Cadence Design Systems recommends high priority interrupt handlers be + * coded in assembly and used for purposes requiring very short service + * times. + * + * Here are templates for high priority (level 2+) interrupt vectors. + * They assume only one interrupt per level to avoid the burden of + * identifying which interrupts at this level are pending and enabled. This + * allows for minimum latency and avoids having to save/restore a2 in + * addition to a0. If more than one interrupt per high priority level is + * configured, this burden is on the handler which in any case must provide + * a way to save and restore registers it uses without touching the + * interrupted stack. + * + * Each vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the Xtensa linker support package (LSP). It performs + * the minimum necessary before jumping to the handler in the .text section. + * + ****************************************************************************/ + +/* +Currently only shells for high priority interrupt handlers are provided +here. However a template and example can be found in the Cadence Design Systems tools +documentation: "Microprocessor Programmer's Guide". +*/ + +#if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 + .section .iram1,"ax" + .type _xtensa_level2_handler, @function + .align 4 + +_xtensa_level2_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 2<<2 + beqz a0, 1f + +.Ln_xtensa_level2_handler_call_hook: + + callx0 a0 /* Must NOT disturb stack! */ + +1: +#endif + + /* USER_EDIT: + * ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 + + rsr a0, EXCSAVE_2 /* Restore a0 */ + rfi 2 + +#endif /* XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 */ + +#if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 + .section .iram1,"ax" + .type _xtensa_level3_handler, @function + .align 4 + +_xtensa_level3_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 3<<2 + beqz a0, 1f + +.Ln_xtensa_level3_handler_call_hook: + + callx0 a0 /* Must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + * ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 + + rsr a0, EXCSAVE_3 /* Restore a0 */ + rfi 3 + +#endif /* XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 */ + +#if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 + .section .iram1,"ax" + .type _xtensa_level4_handler,@function + .align 4 + +_xtensa_level4_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 4 << 2 + beqz a0, 1f + +.Ln_xtensa_level4_handler_call_hook: + + callx0 a0 /* Must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + * ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 + + rsr a0, EXCSAVE_4 /* Restore a0 */ + rfi 4 + +#endif /* XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 */ + +#if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 + .section .iram1,"ax" + .type _xtensa_level5_handler,@function + .align 4 + +_xtensa_level5_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 5 << 2 + beqz a0, 1f + +.Ln_xtensa_level5_handler_call_hook: + + callx0 a0 /* Must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ + + rsr a0, EXCSAVE_5 /* Restore a0 */ + rfi 5 + +#endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */ + +#if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 + .section .iram1,"ax" + .type _xtensa_level6_handler, @function + .align 4 + +_xtensa_level6_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 6 << 2 + beqz a0, 1f + +.Ln_xtensa_level6_handler_call_hook: + + callx0 a0 /* Must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + * ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ + + rsr a0, EXCSAVE_6 /* Restore a0 */ + rfi 6 + +#endif /* XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 */ diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S new file mode 100644 index 00000000000..103a35d8864 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_intvectors.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + + .file "xtensa_vectors.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xtensa_macros.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * C Prototype: + * void _xtensa_levelN_vector(void) + * + * Description: + * Xtensa interrupt vectors. Each vector goes at a predetermined location + * according to the Xtensa hardware configuration, which is ensured by its + * placement in a special section known to the NuttX linker script. The + * vector logic performs the minimum necessary operations before jumping + * to the handler. + * + ****************************************************************************/ + +#if XCHAL_EXCM_LEVEL >= 2 + .begin literal_prefix .xtensa_level2_vector + .section .xtensa_level2_vector.text, "ax" + .global _xtensa_level2_vector + .global _xtensa_level2_handler + .type _xtensa_level2_vector, @function + .align 4 + +_xtensa_level2_vector: + wsr a0, EXCSAVE_2 /* Preserve a0 */ + call0 _xtensa_level2_handler /* Call level 2 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level2_vector, . - _xtensa_level2_vector +#endif + +#if XCHAL_EXCM_LEVEL >= 3 + .begin literal_prefix .xtensa_level3_vector + .section .xtensa_level3_vector.text, "ax" + .global _xtensa_level3_vector + .global _xtensa_level3_handler + .type _xtensa_level3_vector, @function + .align 4 + +_xtensa_level3_vector: + wsr a0, EXCSAVE_3 /* Preserve a0 */ + call0 _xtensa_level3_handler /* Call level 3 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level3_vector, . - _xtensa_level3_vector +#endif + +#if XCHAL_EXCM_LEVEL >= 4 + .begin literal_prefix .xtensa_level4_vector + .section .xtensa_level4_vector.text, "ax" + .global _xtensa_level4_vector + .global _xtensa_level4_handler + .type _xtensa_level4_vector, @function + .align 4 + +_xtensa_level4_vector: + wsr a0, EXCSAVE_4 /* Preserve a0 */ + call0 _xtensa_level4_handler /* Call level 5 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level5_vector, . - _xtensa_level5_vector +#endif + +#if XCHAL_EXCM_LEVEL >= 5 + .begin literal_prefix .xtensa_level5_vector + .section .xtensa_level5_vector.text, "ax" + .global _xtensa_level5_vector + .global _xtensa_level5_handler + .type _xtensa_level5_vector, @function + .align 4 + +_xtensa_level5_vector: + wsr a0, EXCSAVE_5 /* Preserve a0 */ + call0 _xtensa_level5_handler /* Call level 5 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level5_vector, . - _xtensa_level5_vector +#endif + +#if XCHAL_EXCM_LEVEL >= 6 + .begin literal_prefix .xtensa_level6_vector + .section .xtensa_level6_vector.text, "ax" + .global _xtensa_level6_vector + .global _xtensa_level6_handler + .type _xtensa_level6_vector, @function + .align 4 + +_xtensa_level6_vector: + wsr a0, EXCSAVE_6 /* Preserve a0 */ + call0 _xtensa_level6_handler /* Call level 6 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level6_vector, . - _xtensa_level6_vector +#endif diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c new file mode 100644 index 00000000000..2a3e9920e0b --- /dev/null +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtena_irqdispatch.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "xtensa.h" + +#include "group/group.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Nested interrupts are not supported */ + + DEBUGASSERT(CURRENT_REGS == NULL); + + /* Current regs non-zero indicates that we are processing an interrupt; + * CURRENT_REGS is also used to manage interrupt level context switches. + */ + + CURRENT_REGS = regs; + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * CURRENT_REGS will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != CURRENT_REGS) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)CURRENT_REGS); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* Set CURRENT_REGS to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + regs = (uint32_t *)CURRENT_REGS; + CURRENT_REGS = NULL; +#endif + + board_autoled_off(LED_INIRQ); + return regs; +} diff --git a/arch/xtensa/src/common/xtensa_lowputs.c b/arch/xtensa/src/common/xtensa_lowputs.c new file mode 100644 index 00000000000..3daeadc3ef9 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_lowputs.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_lowputs.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_lowputs(const char *str) +{ + while (*str) + { + up_lowputc(*str++); + } +} diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h new file mode 100644 index 00000000000..aabe43b8484 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip_macros.h" + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ +/* Macros to handle ABI specifics of function entry and return. + * + * Convenient where the frame size requirements are the same for both ABIs. + * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + * ENTRY0, RET0 are for frameless functions (no locals, no calls). + * + * where size = size of stack frame in bytes (must be >0 and aligned to 16). + * For framed functions the frame is created and the return address saved at + * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + * For frameless functions, there is no frame and return address remains in a0. + * Note: Because CPP macros expand to a single line, macros requiring multi-line + * expansions are implemented as assembler macros. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + /* Call0 */ + + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + +# define ENTRY(sz) entry1 sz +# define ENTRY0 +# define RET(sz) ret1 sz +# define RET0 ret + +#else + /* Windowed */ + +# define ENTRY(sz) entry sp, sz +# define ENTRY0 entry sp, 0x10 +# define RET(sz) retw +# define RET0 retw + +#endif /* CONFIG_XTENSA_CALL0_ABI */ + +#endif /* __ASSEMBLY */ +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H */ diff --git a/arch/xtensa/src/common/xtensa_mdelay.c b/arch/xtensa/src/common/xtensa_mdelay.c new file mode 100644 index 00000000000..094ba97a79d --- /dev/null +++ b/arch/xtensa/src/common/xtensa_mdelay.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_mdelay.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + volatile int i; + volatile int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg16.c b/arch/xtensa/src/common/xtensa_modifyreg16.c new file mode 100644 index 00000000000..8554fda46fa --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg16.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg16.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg16 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) +{ + irqstate_t flags; + uint16_t regval; + + flags = enter_critical_section(); + regval = getreg16(addr); + regval &= ~clearbits; + regval |= setbits; + putreg16(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg32.c b/arch/xtensa/src/common/xtensa_modifyreg32.c new file mode 100644 index 00000000000..599e39db4bf --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg32.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg32.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg8.c b/arch/xtensa/src/common/xtensa_modifyreg8.c new file mode 100644 index 00000000000..24201b5e97a --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg8.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg8.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg8 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) +{ + irqstate_t flags; + uint8_t regval; + + flags = enter_critical_section(); + regval = getreg8(addr); + regval &= ~clearbits; + regval |= setbits; + putreg8(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_puts.c b/arch/xtensa/src/common/xtensa_puts.c new file mode 100644 index 00000000000..d9449f7ffdb --- /dev/null +++ b/arch/xtensa/src/common/xtensa_puts.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_puts.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_puts + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_puts(const char *str) +{ + while (*str) + { + up_putc(*str++); + } +} diff --git a/arch/xtensa/src/common/xtensa_releasepending.c b/arch/xtensa/src/common/xtensa_releasepending.c new file mode 100644 index 00000000000..99dc0c39b83 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_releasepending.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_releasepending.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = this_task(); + + sinfo("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the ready-to-run task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to + * switch contexts. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we operating in interrupt context? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the exception context into the TCB of the task that + * was currently active. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task + * restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/common/xtensa_releasestack.c b/arch/xtensa/src/common/xtensa_releasestack.c new file mode 100644 index 00000000000..94bb2d8cd8a --- /dev/null +++ b/arch/xtensa/src/common/xtensa_releasestack.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_releasestack.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parmeters + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr) + { +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + sched_kfree(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + sched_ufree(dtcb->stack_alloc_ptr); + } + + /* Mark the stack freed */ + + dtcb->stack_alloc_ptr = NULL; + } + + /* The size of the allocated stack is now zero */ + + dtcb->adj_stack_size = 0; +} diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c new file mode 100644 index 00000000000..3cc2978f478 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_reprioritizertr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(); + } + else + { + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + sinfo("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just + * remove the head of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the specified blocked task list. + * sched_addreadytorun will return true if the task was + * added to the new list. We will need to perform a context + * switch only if the EXCLUSIVE or of the two calls is non-zero + * (i.e., one and only one the calls changes the head of the + * ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the exception context into the TCB at the (old) head of the + * ready-to-run Task list. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } + } +} diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c new file mode 100644 index 00000000000..8090bb262da --- /dev/null +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_schedulesigaction.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'sigdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is being delivered + * to the currently executing task. + */ + + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and a task is + * signalling itself for some reason. + */ + + if (!CURRENT_REGS) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the interrupted + * task is the same as the one that must receive the signal, then + * we will have to modify the return state as well as the state + * in the TCB. + * + * Hmmm... there looks like a latent bug here: The following logic + * would fail in the strange case where we are in an interrupt + * handler, the thread is signalling itself, but a context switch + * to another task has occurred so that CURRENT_REGS does not + * refer to the thread of this_task()! + */ + + else + { + /* Save the return lr and cpsr and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + * + * NOTE: that hi-priority interrupts are not disabled. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = CURRENT_REGS[REG_PC]; + tcb->xcp.saved_ps = CURRENT_REGS[REG_PS]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + CURRENT_REGS[REG_PC] = (uint32_t)xtensa_sigdeliver; +#ifdef CONFIG_XTENSA_CALL0_ABI + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); +#else + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif + + /* And make sure that the saved context in the TCB is the same + * as the interrupt return context. + */ + + xtensa_savestate(tcb->xcp.regs); + } + } + + /* Otherwise, we are (1) signaling a task is not running from an + * interrupt handler or (2) we are not in an interrupt handler and the + * running task is signalling some non-running task. + */ + + else + { + /* Save the return lr and cpsr and one scratch register. These + * will be restored by the signal trampoline after the signals + * have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; + tcb->xcp.saved_ps = tcb->xcp.regs[REG_PS]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_PC] = (uint32_t)xtensa_sigdeliver; +#ifdef CONFIG_XTENSA_CALL0_ABI + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); +#else + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif + } + } + + leave_critical_section(flags); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c new file mode 100644 index 00000000000..5f54c4035c4 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_sigdeliver.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void xtensa_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + xtensa_copystate(regs, rtcb->xcp.regs); + regs[REG_PC] = rtcb->xcp.saved_pc; + regs[REG_PS] = rtcb->xcp.saved_ps; + + /* Get a local copy of the sigdeliver function pointer. we do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + up_irq_restore(regs[REG_PS]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming\n"); + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of execution. */ + + board_autoled_off(LED_SIGNAL); + xtensa_context_restore(regs); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c new file mode 100644 index 00000000000..388238d8de3 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_stackframe.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_stackframe.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - adj_stack_ptr: Adjusted initial stack pointer after the frame has + * been removed from the stack. This will still be the initial value + * of the stack pointer when the task is started. + * + * Inputs: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) +{ + uintptr_t topaddr; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + /* Save the adjusted stack values in the struct tcb_s */ + + topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; + tcb->adj_stack_ptr = (FAR void *)topaddr; + tcb->adj_stack_size -= frame_size; + + /* Reset the initial stack pointer (A1) */ + + tcb->xcp.regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; + + /* And return the pointer to the allocated region */ + + return (FAR void *)(topaddr + sizeof(uint32_t)); +} diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c new file mode 100644 index 00000000000..b4b3baa0fbf --- /dev/null +++ b/arch/xtensa/src/common/xtensa_testset.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_testset.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "xtensa.h" + +#ifdef CONFIG_SPINLOCK + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_compareset + * + * Description: + * Wrapper for the Xtensa compare-and-set instruction. This function will + * atomically compare *addr to compare, and if it's the same, will set + * *addr to set. It will return the old value of *addr. + * + * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i + * instruction may return the *bitwise inverse* of the old mem if the + * mem wasn't written. This doesn't seem to happen on the ESP32, though. + * (Would show up directly if it did because the magic wouldn't match.) + * + ****************************************************************************/ + +static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr, + uint32_t compare, + uint32_t set) +{ + __asm__ __volatile__ + ( + "WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */ + "ISYNC\n" /* Wait sync */ + "S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the + * same as comparel. Otherwise, no write-access */ + : "=r"(set) : "r"(addr), "r"(compare), "0"(set) + ); + + return set; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logoic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * was previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +spinlock_t up_testset(volatile FAR spinlock_t *lock) +{ + spinlock_t prev; + + /* Perform the 32-bit compare and set operation */ + + prev = xtensa_compareset((FAR volatile uint32_t *)lock, + SP_UNLOCKED, SP_LOCKED); + + /* xtensa_compareset() should return either SP_UNLOCKED if the spinlock + * was locked or SP_LOCKED or possibly ~SP_UNLOCKED if the spinlock was + * not locked: + * + * "In the RE-2013.0 release and after, there is a slight change in the + * semantics of the S32C1I instruction. Nothing is changed about the + * operation on memory. In rare cases the resulting value in register + * at can be different in this and later releases. The rule still holds + * that memory has been written if and only if the register result + * equals SCOMPARE1. + * + * "The difference is that in some cases where memory has not been + * written, the instruction returns ~SCOMPARE1 instead of the current + * value of memory. Although this change can, in principle, affect + * the operation of code, scanning all internal Cadence code produced + * no examples where this change would change the operation of the + * code." + * + * In any case, the return value of SP_UNLOCKED can be trusted and will + * always mean that the the spinlock was set. + */ + + return (prev == SP_UNLOCKED) ? SP_UNLOCKED : SP_LOCKED; +} diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h new file mode 100644 index 00000000000..0a4429633be --- /dev/null +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_timer.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * Copyright (c) 2003-2015 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + *******************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H + +#ifdef __ASSEMBLER__ +# include +#endif + +#include +#include +#include + +/* Select timer to use for periodic tick, and determine its interrupt number + * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, + * in which case its validity is checked (it must exist in this core and must + * not be on a high priority interrupt - an error will be reported in invalid). + * Otherwise select the first low or medium priority interrupt timer available. + */ + +#if XCHAL_NUM_TIMERS == 0 + +# error "This Xtensa configuration is unsupported, it has no timers." + +#else + +#ifndef XT_TIMER_INDEX +# if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 3 +# endif +# endif +# if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 2 +# endif +# endif +# if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 1 +# endif +# endif +# if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 0 +# endif +# endif +#endif +#ifndef XT_TIMER_INDEX +# error "There is no suitable timer in this Xtensa configuration." +#endif + +#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) +#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) +#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) +#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) + +#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED +# error "The timer selected by XT_TIMER_INDEX does not exist in this core." +#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL +# error "The timer interrupt cannot be high priority (use medium or low)." +#endif + +#endif /* XCHAL_NUM_TIMERS */ + +/* Set processor clock frequency, used to determine clock divisor for timer + * tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being + * used. If using a supported board via the board-independent API defined in + * xtbsp.h, this may be left undefined and frequency and tick divisor will + * be computed and cached during run-time initialization. + * + * NOTE ON SIMULATOR: + * Under the Xtensa instruction set simulator, the frequency can only be + * estimated because it depends on the speed of the host and the version of + * the simulator. Also because it runs much slower than hardware, it is not + * possible to achieve real-time performance for most applications under the + * simulator. A frequency too low does not allow enough time between timer + * interrupts, starving threads. To obtain a more convenient but non-real- + * time tick duration on the simulator, compile with xt-xcc option + * "-DXT_SIMULATOR". Adjust this frequency to taste (it's not real-time + * anyway!). + */ + +#if defined(XT_SIMULATOR) && !defined(BOARD_CLOCK_FREQUENCY) +# define BOARD_CLOCK_FREQUENCY +#endif + +#if !defined(BOARD_CLOCK_FREQUENCY) && !defined(XT_BOARD) +# warning "BOARD_CLOCK_FREQUENCY must be defined for the target platform." +#endif + +/* Default number of timer "ticks" per second (default 100 for 10ms tick). + * RTOS may define this in its own way (if applicable) in xtensa_rtos.h. + * User may redefine this to an optimal value for the application, either by + * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option + * "-DXT_TICK_PER_SEC=" where is a suitable number. + */ + +#ifndef XT_TICK_PER_SEC +# define XT_TICK_PER_SEC (1000000 / CONFIG_USEC_PER_TICK) +#endif + +/* Derivation of clock divisor for timer tick and interrupt (one per tick). */ + +#ifdef BOARD_CLOCK_FREQUENCY +# define XT_TICK_DIVISOR (BOARD_CLOCK_FREQUENCY / XT_TICK_PER_SEC) +#endif + +#ifndef __ASSEMBLER__ +extern unsigned _xt_tick_divisor; +void _xt_tick_divisor_init(void); +#endif + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H */ diff --git a/arch/xtensa/src/common/xtensa_udelay.c b/arch/xtensa/src/common/xtensa_udelay.c new file mode 100644 index 00000000000..09d16d5d4de --- /dev/null +++ b/arch/xtensa/src/common/xtensa_udelay.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_udelay.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay inline for the requested number of microseconds. NOTE: Because + * of all of the setup, several microseconds will be lost before the actual + * timing looop begins. Thus, the delay will always be a few microseconds + * longer than requested. + * + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_udelay(useconds_t microseconds) +{ + volatile int i; + + /* We'll do this a little at a time because we expect that the + * CONFIG_BOARD_LOOPSPERUSEC is very inaccurate during to truncation in + * the divisions of its calculation. We'll use the largest values that + * we can in order to prevent significant error buildup in the loops. + */ + + while (microseconds > 1000) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) + { + } + microseconds -= 1000; + } + + while (microseconds > 100) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) + { + } + microseconds -= 100; + } + + while (microseconds > 10) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) + { + } + microseconds -= 10; + } + + while (microseconds > 0) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) + { + } + microseconds--; + } +} diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c new file mode 100644 index 00000000000..e7a37ba4104 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_unblocktask.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_unblocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list + * but has been prepped to execute. Move the TCB to the + * ready-to-run list, restore its context, and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is + * in one of the waiting tasks lists. It must be moved to + * the ready-to-run list and, if it is the highest priority + * ready to run task, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + struct tcb_s *rtcb = this_task(); + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && + (tcb->task_state <= LAST_BLOCKED_STATE)); + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Add the task in the correct location in the prioritized + * ready-to-run task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* We are not in an interrupt handler. Copy the user C context + * into the TCB of the task that was previously active. if + * up_saveusercontext returns a non-zero value, then this is really the + * previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the new task that is ready to + * run (probably tcb). This is the new rtcb at the head of the + * ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c new file mode 100644 index 00000000000..0b5db031e91 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_usestack.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from task_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The + * initial value of the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + size_t top_of_stack; + size_t size_of_stack; + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* XTENSA uses a push-down stack: the stack grows toward loweraddresses in + * memory. The stack pointer register, points to the lowest, valid work + * address (the "top" of the stack). Items on the stack are referenced + * as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The XTENSA stack must be aligned at word (4 byte) or double word (8 byte) + * boundaries. If necessary top_of_stack must be rounded down to the + * next boundary + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + return OK; +} diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig new file mode 100644 index 00000000000..5263d6c5b70 --- /dev/null +++ b/arch/xtensa/src/esp32/Kconfig @@ -0,0 +1,20 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32 + +config ESP32_BT_RESERVE_DRAM + int "Reserved BT DRAM" + default 0 + +config ESP32_TRACEMEM_RESERVE_DRAM + int "Reserved trace memory DRAM" + default 0 + +config ESP32_ULP_COPROC_RESERVE_MEM + int "Reserved ULP co-processor DRAM" + default 0 + +endif # ARCH_CHIP_ESP32 diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs new file mode 100644 index 00000000000..1270f0c0cc1 --- /dev/null +++ b/arch/xtensa/src/esp32/Make.defs @@ -0,0 +1,87 @@ +############################################################################ +# arch/xtensa/src/lx6/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# The start-up, "head", file. May be either a .S or a .c file. + +HEAD_ASRC = +HEAD_CSRC = esp32_start.c + +# Common XTENSA files (arch/xtensa/src/common) + +CMN_ASRCS = xtensa_context.S xtensa_intvectors.S +CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c +CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c +CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c xtensa_lowputs.c +CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c +CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasepending.c +CMN_CSRCS += xtensa_releasestack.c xtensa_reprioritizertr.c +CMN_CSRCS += xtensa_schedsigaction.c xtensa_sigdeliver.c xtensa_stackframe.c +CMN_CSRCS += xtensa_udelay.c xtensa_unblocktask.c xtensa_usestack.c + +# Configuration-dependent common XTENSA files + +ifeq ($(CONFIG_DEBUG_ALERT),y) + CMN_CSRCS += xtensa_dumpstate.c +endif + +ifeq ($(CONFIG_SPINLOCK),y) + CMN_CSRCS += xtensa_testset.c +endif + +# Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism +# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to +# up_netinitialize() in xtensa_initialize.c. Then this stub would not be +# needed. + +ifneq ($(CONFIG_LX6_ETHERNET),y) +ifeq ($(CONFIG_NET),y) + CMN_CSRCS += xtensa_etherstub.c +endif +endif + +# Required ESP32 files (arch/xtensa/src/lx6) + +CHIP_ASRCS = +CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c +CHIP_CSRCS += esp32_region.c esp32_start.c esp32_timerisr.c + +# Configuration-dependent ESP32 files + +ifeq ($(CONFIG_SMP),y) +CHIP_ASRCS = esp32_cpuindex.S +#CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c +CMN_CSRCS += esp32_cpustart.c +endif diff --git a/arch/xtensa/src/esp32/chip/esp32_dport.h b/arch/xtensa/src/esp32/chip/esp32_dport.h new file mode 100644 index 00000000000..0dcf98b6262 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_dport.h @@ -0,0 +1,3854 @@ +/**************************************************************************** + * arch/xtensa/src/common/esp32_dport.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) +/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_BOOT_REMAP (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_M (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_V 0x1 +#define DPORT_PRO_BOOT_REMAP_S 0 + +#define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) +/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_BOOT_REMAP (BIT(0)) +#define DPORT_APP_BOOT_REMAP_M (BIT(0)) +#define DPORT_APP_BOOT_REMAP_V 0x1 +#define DPORT_APP_BOOT_REMAP_S 0 + +#define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) +/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_ACCESS_CHECK_APP (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_M (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_V 0x1 +#define DPORT_ACCESS_CHECK_APP_S 8 +/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_ACCESS_CHECK_PRO (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_V 0x1 +#define DPORT_ACCESS_CHECK_PRO_S 0 + +#define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) +/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) +#define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_S 0 + +#define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) +/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) +#define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_S 0 + +#define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) +/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) +#define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_S 0 + +#define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) +/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) +#define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_S 0 + +#define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) +/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERI_CLK_EN 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) +#define DPORT_PERI_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_S 0 + +#define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) +/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERI_RST_EN 0xFFFFFFFF +#define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) +#define DPORT_PERI_RST_EN_V 0xFFFFFFFF +#define DPORT_PERI_RST_EN_S 0 + +#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) +/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_BB_CFG 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) +#define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_S 0 + +#define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) +/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) +#define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_S 0 + +#define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) +/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APPCPU_RESETTING (BIT(0)) +#define DPORT_APPCPU_RESETTING_M (BIT(0)) +#define DPORT_APPCPU_RESETTING_V 0x1 +#define DPORT_APPCPU_RESETTING_S 0 + +#define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) +/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APPCPU_CLKGATE_EN (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_V 0x1 +#define DPORT_APPCPU_CLKGATE_EN_S 0 + +#define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) +/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APPCPU_RUNSTALL (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_M (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_V 0x1 +#define DPORT_APPCPU_RUNSTALL_S 0 + +#define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) +/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) +#define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_S 0 + +#define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) +/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_FAST_CLK_RTC_SEL (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_V 0x1 +#define DPORT_FAST_CLK_RTC_SEL_S 3 +/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LOWSPEED_CLK_SEL (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_V 0x1 +#define DPORT_LOWSPEED_CLK_SEL_S 2 +/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_CPUPERIOD_SEL 0x00000003 +#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) +#define DPORT_CPUPERIOD_SEL_V 0x3 +#define DPORT_CPUPERIOD_SEL_S 0 + +#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) +/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM_HL (BIT(16)) +#define DPORT_PRO_DRAM_HL_M (BIT(16)) +#define DPORT_PRO_DRAM_HL_V 0x1 +#define DPORT_PRO_DRAM_HL_S 16 +/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_REQ (BIT(15)) +#define DPORT_SLAVE_REQ_M (BIT(15)) +#define DPORT_SLAVE_REQ_V 0x1 +#define DPORT_SLAVE_REQ_S 15 +/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_SPI_REQ (BIT(14)) +#define DPORT_AHB_SPI_REQ_M (BIT(14)) +#define DPORT_AHB_SPI_REQ_V 0x1 +#define DPORT_AHB_SPI_REQ_S 14 +/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_REQ (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_M (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_V 0x1 +#define DPORT_PRO_SLAVE_REQ_S 13 +/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_AHB_SPI_REQ (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_V 0x1 +#define DPORT_PRO_AHB_SPI_REQ_S 12 +/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM_SPLIT (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_V 0x1 +#define DPORT_PRO_DRAM_SPLIT_S 11 +/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_PRO_SINGLE_IRAM_ENA_S 10 +/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_3_EN_S 9 +/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_2_EN_S 8 +/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_1_EN_S 7 +/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_0_EN_S 6 +/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_DONE_S 5 +/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_ENA_S 4 +/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_ENABLE (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_V 0x1 +#define DPORT_PRO_CACHE_ENABLE_S 3 +/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MODE (BIT(2)) +#define DPORT_PRO_CACHE_MODE_M (BIT(2)) +#define DPORT_PRO_CACHE_MODE_V 0x1 +#define DPORT_PRO_CACHE_MODE_S 2 + +#define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) +/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 +/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_PD (BIT(12)) +#define DPORT_PRO_CMMU_PD_M (BIT(12)) +#define DPORT_PRO_CMMU_PD_V 0x1 +#define DPORT_PRO_CMMU_PD_S 12 +/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_V 0x1 +#define DPORT_PRO_CMMU_FORCE_ON_S 11 +/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_DROM0_S 4 +/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_DRAM1_S 3 +/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IROM0_S 2 +/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM1_S 1 +/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM0_S 0 + +#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) +/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM_HL (BIT(14)) +#define DPORT_APP_DRAM_HL_M (BIT(14)) +#define DPORT_APP_DRAM_HL_V 0x1 +#define DPORT_APP_DRAM_HL_S 14 +/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_REQ (BIT(13)) +#define DPORT_APP_SLAVE_REQ_M (BIT(13)) +#define DPORT_APP_SLAVE_REQ_V 0x1 +#define DPORT_APP_SLAVE_REQ_S 13 +/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_AHB_SPI_REQ (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_V 0x1 +#define DPORT_APP_AHB_SPI_REQ_S 12 +/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM_SPLIT (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_M (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_V 0x1 +#define DPORT_APP_DRAM_SPLIT_S 11 +/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_APP_SINGLE_IRAM_ENA_S 10 +/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_3_EN_S 9 +/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_2_EN_S 8 +/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_1_EN_S 7 +/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_0_EN_S 6 +/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_APP_CACHE_FLUSH_DONE_S 5 +/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_APP_CACHE_FLUSH_ENA_S 4 +/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_ENABLE (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_M (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_V 0x1 +#define DPORT_APP_CACHE_ENABLE_S 3 +/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MODE (BIT(2)) +#define DPORT_APP_CACHE_MODE_M (BIT(2)) +#define DPORT_APP_CACHE_MODE_V 0x1 +#define DPORT_APP_CACHE_MODE_S 2 + +#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) +/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_CLR_S 13 +/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CMMU_PD (BIT(12)) +#define DPORT_APP_CMMU_PD_M (BIT(12)) +#define DPORT_APP_CMMU_PD_V 0x1 +#define DPORT_APP_CMMU_PD_S 12 +/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CMMU_FORCE_ON (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_V 0x1 +#define DPORT_APP_CMMU_FORCE_ON_S 11 +/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/* Description: */ +#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_DROM0_S 4 +/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_DRAM1_S 3 +/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IROM0_S 2 +/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM1_S 1 +/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM0_S 0 + +#define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) +/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) +/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) +/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) +/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) +/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_TRACEMEM_MUX_MODE 0x00000003 +#define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) +#define DPORT_TRACEMEM_MUX_MODE_V 0x3 +#define DPORT_TRACEMEM_MUX_MODE_S 0 + +#define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) +/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_TRACEMEM_ENA (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_V 0x1 +#define DPORT_PRO_TRACEMEM_ENA_S 0 + +#define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) +/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_TRACEMEM_ENA (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_V 0x1 +#define DPORT_APP_TRACEMEM_ENA_S 0 + +#define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) +/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_CACHE_MUX_MODE 0x00000003 +#define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) +#define DPORT_CACHE_MUX_MODE_V 0x3 +#define DPORT_CACHE_MUX_MODE_S 0 + +#define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) +/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_IMMU_PAGE_MODE 0x00000003 +#define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) +#define DPORT_IMMU_PAGE_MODE_V 0x3 +#define DPORT_IMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 + +#define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) +/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_DMMU_PAGE_MODE 0x00000003 +#define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) +#define DPORT_DMMU_PAGE_MODE_V 0x3 +#define DPORT_DMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 + +#define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) +/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_MPU_ENA (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_V 0x1 +#define DPORT_APP_ROM_MPU_ENA_S 2 +/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_MPU_ENA (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_V 0x1 +#define DPORT_PRO_ROM_MPU_ENA_S 1 +/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_V 0x1 +#define DPORT_SHARE_ROM_MPU_ENA_S 0 + +#define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) +/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_LSLP_MEM_PD_MASK (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_V 0x1 +#define DPORT_LSLP_MEM_PD_MASK_S 0 + +#define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) +/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_PD 0x0000003F +#define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) +#define DPORT_SHARE_ROM_PD_V 0x3F +#define DPORT_SHARE_ROM_PD_S 2 +/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_APP_ROM_PD (BIT(1)) +#define DPORT_APP_ROM_PD_M (BIT(1)) +#define DPORT_APP_ROM_PD_V 0x1 +#define DPORT_APP_ROM_PD_S 1 +/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_PD (BIT(0)) +#define DPORT_PRO_ROM_PD_M (BIT(0)) +#define DPORT_PRO_ROM_PD_V 0x1 +#define DPORT_PRO_ROM_PD_S 0 + +#define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) +/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_FO 0x0000003F +#define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) +#define DPORT_SHARE_ROM_FO_V 0x3F +#define DPORT_SHARE_ROM_FO_S 2 +/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_APP_ROM_FO (BIT(1)) +#define DPORT_APP_ROM_FO_M (BIT(1)) +#define DPORT_APP_ROM_FO_V 0x1 +#define DPORT_APP_ROM_FO_S 1 +/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_PRO_ROM_FO (BIT(0)) +#define DPORT_PRO_ROM_FO_M (BIT(0)) +#define DPORT_PRO_ROM_FO_V 0x1 +#define DPORT_PRO_ROM_FO_S 0 + +#define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) +/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_SRAM_PD_0 0xFFFFFFFF +#define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) +#define DPORT_SRAM_PD_0_V 0xFFFFFFFF +#define DPORT_SRAM_PD_0_S 0 + +#define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) +/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_SRAM_PD_1 (BIT(0)) +#define DPORT_SRAM_PD_1_M (BIT(0)) +#define DPORT_SRAM_PD_1_V 0x1 +#define DPORT_SRAM_PD_1_S 0 + +#define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) +/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/* Description: */ +#define DPORT_SRAM_FO_0 0xFFFFFFFF +#define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) +#define DPORT_SRAM_FO_0_V 0xFFFFFFFF +#define DPORT_SRAM_FO_0_S 0 + +#define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) +/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_SRAM_FO_1 (BIT(0)) +#define DPORT_SRAM_FO_1_M (BIT(0)) +#define DPORT_SRAM_FO_1_V 0x1 +#define DPORT_SRAM_FO_1_S 0 + +#define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) +/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ +/* Description: */ +#define DPORT_MAC_DUMP_MODE 0x00000003 +#define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) +#define DPORT_MAC_DUMP_MODE_V 0x3 +#define DPORT_MAC_DUMP_MODE_S 5 +/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_AHB (BIT(4)) +#define DPORT_MASK_AHB_M (BIT(4)) +#define DPORT_MASK_AHB_V 0x1 +#define DPORT_MASK_AHB_S 4 +/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_APP_DRAM (BIT(3)) +#define DPORT_MASK_APP_DRAM_M (BIT(3)) +#define DPORT_MASK_APP_DRAM_V 0x1 +#define DPORT_MASK_APP_DRAM_S 3 +/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_PRO_DRAM (BIT(2)) +#define DPORT_MASK_PRO_DRAM_M (BIT(2)) +#define DPORT_MASK_PRO_DRAM_V 0x1 +#define DPORT_MASK_PRO_DRAM_S 2 +/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_APP_IRAM (BIT(1)) +#define DPORT_MASK_APP_IRAM_M (BIT(1)) +#define DPORT_MASK_APP_IRAM_V 0x1 +#define DPORT_MASK_APP_IRAM_S 1 +/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_PRO_IRAM (BIT(0)) +#define DPORT_MASK_PRO_IRAM_M (BIT(0)) +#define DPORT_MASK_PRO_IRAM_V 0x1 +#define DPORT_MASK_PRO_IRAM_S 0 + +#define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) +/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_TAG_PD (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_V 0x1 +#define DPORT_APP_CACHE_TAG_PD_S 9 +/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 +/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_TAG_PD (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_V 0x1 +#define DPORT_PRO_CACHE_TAG_PD_S 1 +/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 + +#define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) +/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 +#define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) +#define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 +#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 +/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_APPDPORT_S 10 +/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_PRODPORT_S 9 +/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_V 0x1 +#define DPORT_AHB_LITE_MASK_SDIO_S 8 +/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_APP (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_V 0x1 +#define DPORT_AHB_LITE_MASK_APP_S 4 +/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_PRO (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_V 0x1 +#define DPORT_AHB_LITE_MASK_PRO_S 0 + +#define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) +/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) +#define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_S 0 + +#define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) +/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF +#define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) +#define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF +#define DPORT_AHB_ACCESS_GRANT_1_S 0 + +#define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) +/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/* Description: */ +#define DPORT_LINK_DEVICE_SEL 0x000000FF +#define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) +#define DPORT_LINK_DEVICE_SEL_V 0xFF +#define DPORT_LINK_DEVICE_SEL_S 8 +/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/* Description: */ +#define DPORT_PERI_IO_SWAP 0x000000FF +#define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) +#define DPORT_PERI_IO_SWAP_V 0xFF +#define DPORT_PERI_IO_SWAP_S 0 + +#define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) +/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ +/* Description: */ +#define DPORT_PERIP_CLK_EN 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) +#define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_S 0 + +#define DPORT_PWM3_CLK_EN (BIT(26)) +#define DPORT_PWM2_CLK_EN (BIT(25)) +#define DPORT_UART_MEM_CLK_EN (BIT(24)) +#define DPORT_UART2_CLK_EN (BIT(23)) +#define DPORT_SPI_DMA_CLK_EN (BIT(22)) +#define DPORT_I2S1_CLK_EN (BIT(21)) +#define DPORT_PWM1_CLK_EN (BIT(20)) +#define DPORT_CAN_CLK_EN (BIT(19)) +#define DPORT_I2C_EXT1_CLK_EN (BIT(18)) +#define DPORT_PWM0_CLK_EN (BIT(17)) +#define DPORT_SPI_CLK_EN (BIT(16)) +#define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) +#define DPORT_EFUSE_CLK_EN (BIT(14)) +#define DPORT_TIMERGROUP_CLK_EN (BIT(13)) +#define DPORT_UHCI1_CLK_EN (BIT(12)) +#define DPORT_LEDC_CLK_EN (BIT(11)) +#define DPORT_PCNT_CLK_EN (BIT(10)) +#define DPORT_RMT_CLK_EN (BIT(9)) +#define DPORT_UHCI0_CLK_EN (BIT(8)) +#define DPORT_I2C_EXT0_CLK_EN (BIT(7)) +#define DPORT_SPI_CLK_EN_2 (BIT(6)) +#define DPORT_UART1_CLK_EN (BIT(5)) +#define DPORT_I2S0_CLK_EN (BIT(4)) +#define DPORT_WDG_CLK_EN (BIT(3)) +#define DPORT_UART_CLK_EN (BIT(2)) +#define DPORT_SPI_CLK_EN_1 (BIT(1)) +#define DPORT_TIMERS_CLK_EN (BIT(0)) +#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) +/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERIP_RST 0xFFFFFFFF +#define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) +#define DPORT_PERIP_RST_V 0xFFFFFFFF +#define DPORT_PERIP_RST_S 0 +#define DPORT_PWM3_RST (BIT(26)) +#define DPORT_PWM2_RST (BIT(25)) +#define DPORT_UART_MEM_RST (BIT(24)) +#define DPORT_UART2_RST (BIT(23)) +#define DPORT_SPI_DMA_RST (BIT(22)) +#define DPORT_I2S1_RST (BIT(21)) +#define DPORT_PWM1_RST (BIT(20)) +#define DPORT_CAN_RST (BIT(19)) +#define DPORT_I2C_EXT1_RST (BIT(18)) +#define DPORT_PWM0_RST (BIT(17)) +#define DPORT_SPI_RST (BIT(16)) +#define DPORT_TIMERGROUP1_RST (BIT(15)) +#define DPORT_EFUSE_RST (BIT(14)) +#define DPORT_TIMERGROUP_RST (BIT(13)) +#define DPORT_UHCI1_RST (BIT(12)) +#define DPORT_LEDC_RST (BIT(11)) +#define DPORT_PCNT_RST (BIT(10)) +#define DPORT_RMT_RST (BIT(9)) +#define DPORT_UHCI0_RST (BIT(8)) +#define DPORT_I2C_EXT0_RST (BIT(7)) +#define DPORT_SPI_RST_2 (BIT(6)) +#define DPORT_UART1_RST (BIT(5)) +#define DPORT_I2S0_RST (BIT(4)) +#define DPORT_WDG_RST (BIT(3)) +#define DPORT_UART_RST (BIT(2)) +#define DPORT_SPI_RST_1 (BIT(1)) +#define DPORT_TIMERS_RST (BIT(0)) +#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) +/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_V 0x1 +#define DPORT_SPI_DECRYPT_ENABLE_S 12 +/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 +#define DPORT_SPI_ENCRYPT_ENABLE_S 8 +/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_V 0x1 +#define DPORT_SLAVE_SPI_MASK_APP_S 4 +/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 +#define DPORT_SLAVE_SPI_MASK_PRO_S 0 + +#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) +/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/* Description: */ +#define DPORT_WIFI_CLK_EN 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) +#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_S 0 + +#define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) +/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_RST 0xFFFFFFFF +#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) +#define DPORT_WIFI_RST_V 0xFFFFFFFF +#define DPORT_WIFI_RST_S 0 + +#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) +/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_BTEXTWAKEUP_REQ (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_V 0x1 +#define DPORT_BTEXTWAKEUP_REQ_S 12 +/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF +#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) +#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF +#define DPORT_BT_LPCK_DIV_NUM_S 0 + +#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) +/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_V 0x1 +#define DPORT_LPCLK_SEL_XTAL32K_S 27 +/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_XTAL (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_V 0x1 +#define DPORT_LPCLK_SEL_XTAL_S 26 +/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_8M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_V 0x1 +#define DPORT_LPCLK_SEL_8M_S 25 +/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 +#define DPORT_LPCLK_SEL_RTC_SLOW_S 24 +/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_A 0x00000FFF +#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) +#define DPORT_BT_LPCK_DIV_A_V 0xFFF +#define DPORT_BT_LPCK_DIV_A_S 12 +/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_B 0x00000FFF +#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) +#define DPORT_BT_LPCK_DIV_B_V 0xFFF +#define DPORT_BT_LPCK_DIV_B_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) +/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_0_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) +/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_1_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) +/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_2_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) +/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_3_S 0 + +#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) +/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) +#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_S 0 + +#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) +/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) +#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_S 0 + +#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) +/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) +#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_S 0 + +#define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) +/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) +#define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_S 0 + +#define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) +/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) +#define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_S 0 + +#define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) +/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) +#define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_S 0 + +#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) +/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MAC_INTR_MAP 0x0000001F +#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) +#define DPORT_PRO_MAC_INTR_MAP_V 0x1F +#define DPORT_PRO_MAC_INTR_MAP_S 0 + +#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) +/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MAC_NMI_MAP 0x0000001F +#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) +#define DPORT_PRO_MAC_NMI_MAP_V 0x1F +#define DPORT_PRO_MAC_NMI_MAP_S 0 + +#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) +/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) +#define DPORT_PRO_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) +/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F +#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) +#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F +#define DPORT_PRO_BT_MAC_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) +/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) +#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BT_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) +/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F +#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) +#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F +#define DPORT_PRO_BT_BB_NMI_MAP_S 0 + +#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) +/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) +#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBT_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) +/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) +#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBLE_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) +/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) +#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBT_NMI_MAP_S 0 + +#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) +/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) +#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBLE_NMI_MAP_S 0 + +#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) +/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) +#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC0_INTR_MAP_S 0 + +#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) +/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) +#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC1_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) +/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) +#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI0_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) +/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) +#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI1_INTR_MAP_S 0 + +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) +/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) +/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) +/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) +/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) +/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) +/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) +/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) +/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) +/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) +/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) +/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) +/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) +/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) +#define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_0_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) +/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) +#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_1_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) +/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) +#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_2_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) +/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) +#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_3_MAP_S 0 + +#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) +/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2S0_INT_MAP 0x0000001F +#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) +#define DPORT_PRO_I2S0_INT_MAP_V 0x1F +#define DPORT_PRO_I2S0_INT_MAP_S 0 + +#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) +/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2S1_INT_MAP 0x0000001F +#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) +#define DPORT_PRO_I2S1_INT_MAP_V 0x1F +#define DPORT_PRO_I2S1_INT_MAP_S 0 + +#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) +/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART_INTR_MAP 0x0000001F +#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) +#define DPORT_PRO_UART_INTR_MAP_V 0x1F +#define DPORT_PRO_UART_INTR_MAP_S 0 + +#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) +/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART1_INTR_MAP 0x0000001F +#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) +#define DPORT_PRO_UART1_INTR_MAP_V 0x1F +#define DPORT_PRO_UART1_INTR_MAP_S 0 + +#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) +/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART2_INTR_MAP 0x0000001F +#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) +#define DPORT_PRO_UART2_INTR_MAP_V 0x1F +#define DPORT_PRO_UART2_INTR_MAP_S 0 + +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) +/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) +/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_EMAC_INT_MAP 0x0000001F +#define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) +#define DPORT_PRO_EMAC_INT_MAP_V 0x1F +#define DPORT_PRO_EMAC_INT_MAP_S 0 + +#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) +/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) +#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM0_INTR_MAP_S 0 + +#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) +/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) +#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM1_INTR_MAP_S 0 + +#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) +/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) +#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM2_INTR_MAP_S 0 + +#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) +/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) +#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM3_INTR_MAP_S 0 + +#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) +/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_LEDC_INT_MAP 0x0000001F +#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) +#define DPORT_PRO_LEDC_INT_MAP_V 0x1F +#define DPORT_PRO_LEDC_INT_MAP_S 0 + +#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) +/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F +#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) +#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F +#define DPORT_PRO_EFUSE_INT_MAP_S 0 + +#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) +/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CAN_INT_MAP 0x0000001F +#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) +#define DPORT_PRO_CAN_INT_MAP_V 0x1F +#define DPORT_PRO_CAN_INT_MAP_S 0 + +#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) +/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) +#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) +/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RMT_INTR_MAP 0x0000001F +#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) +#define DPORT_PRO_RMT_INTR_MAP_V 0x1F +#define DPORT_PRO_RMT_INTR_MAP_S 0 + +#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) +/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F +#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) +#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F +#define DPORT_PRO_PCNT_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) +/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) +/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) +/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RSA_INTR_MAP 0x0000001F +#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) +#define DPORT_PRO_RSA_INTR_MAP_V 0x1F +#define DPORT_PRO_RSA_INTR_MAP_S 0 + +#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) +/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) +/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) +/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) +/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_WDG_INT_MAP 0x0000001F +#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) +#define DPORT_PRO_WDG_INT_MAP_V 0x1F +#define DPORT_PRO_WDG_INT_MAP_S 0 + +#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) +/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) +#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT1_MAP_S 0 + +#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) +/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) +#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT2_MAP_S 0 + +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) +/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) +/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) +/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) +/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) +/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) +/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) +/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) +/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) +/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) +#define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MMU_IA_INT_MAP_S 0 + +#define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) +/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) +#define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MPU_IA_INT_MAP_S 0 + +#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) +/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) +#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_PRO_CACHE_IA_INT_MAP_S 0 + +#define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) +/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MAC_INTR_MAP 0x0000001F +#define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) +#define DPORT_APP_MAC_INTR_MAP_V 0x1F +#define DPORT_APP_MAC_INTR_MAP_S 0 + +#define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) +/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MAC_NMI_MAP 0x0000001F +#define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) +#define DPORT_APP_MAC_NMI_MAP_V 0x1F +#define DPORT_APP_MAC_NMI_MAP_S 0 + +#define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) +/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BB_INT_MAP 0x0000001F +#define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) +#define DPORT_APP_BB_INT_MAP_V 0x1F +#define DPORT_APP_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) +/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F +#define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) +#define DPORT_APP_BT_MAC_INT_MAP_V 0x1F +#define DPORT_APP_BT_MAC_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) +/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_BB_INT_MAP 0x0000001F +#define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) +#define DPORT_APP_BT_BB_INT_MAP_V 0x1F +#define DPORT_APP_BT_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) +/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F +#define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) +#define DPORT_APP_BT_BB_NMI_MAP_V 0x1F +#define DPORT_APP_BT_BB_NMI_MAP_S 0 + +#define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) +/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) +#define DPORT_APP_RWBT_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBT_IRQ_MAP_S 0 + +#define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) +/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) +#define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBLE_IRQ_MAP_S 0 + +#define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) +/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBT_NMI_MAP 0x0000001F +#define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) +#define DPORT_APP_RWBT_NMI_MAP_V 0x1F +#define DPORT_APP_RWBT_NMI_MAP_S 0 + +#define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) +/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F +#define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) +#define DPORT_APP_RWBLE_NMI_MAP_V 0x1F +#define DPORT_APP_RWBLE_NMI_MAP_S 0 + +#define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) +/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SLC0_INTR_MAP 0x0000001F +#define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) +#define DPORT_APP_SLC0_INTR_MAP_V 0x1F +#define DPORT_APP_SLC0_INTR_MAP_S 0 + +#define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) +/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SLC1_INTR_MAP 0x0000001F +#define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) +#define DPORT_APP_SLC1_INTR_MAP_V 0x1F +#define DPORT_APP_SLC1_INTR_MAP_S 0 + +#define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) +/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) +#define DPORT_APP_UHCI0_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI0_INTR_MAP_S 0 + +#define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) +/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) +#define DPORT_APP_UHCI1_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI1_INTR_MAP_S 0 + +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) +/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) +/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) +/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) +/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) +/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) +/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) +/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) +/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) +/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) +/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) +/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) +/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) +/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) +/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) +/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) +#define DPORT_APP_SPI_INTR_0_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_0_MAP_S 0 + +#define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) +/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) +#define DPORT_APP_SPI_INTR_1_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_1_MAP_S 0 + +#define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) +/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) +#define DPORT_APP_SPI_INTR_2_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_2_MAP_S 0 + +#define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) +/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) +#define DPORT_APP_SPI_INTR_3_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_3_MAP_S 0 + +#define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) +/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2S0_INT_MAP 0x0000001F +#define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) +#define DPORT_APP_I2S0_INT_MAP_V 0x1F +#define DPORT_APP_I2S0_INT_MAP_S 0 + +#define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) +/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2S1_INT_MAP 0x0000001F +#define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) +#define DPORT_APP_I2S1_INT_MAP_V 0x1F +#define DPORT_APP_I2S1_INT_MAP_S 0 + +#define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) +/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART_INTR_MAP 0x0000001F +#define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) +#define DPORT_APP_UART_INTR_MAP_V 0x1F +#define DPORT_APP_UART_INTR_MAP_S 0 + +#define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) +/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART1_INTR_MAP 0x0000001F +#define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) +#define DPORT_APP_UART1_INTR_MAP_V 0x1F +#define DPORT_APP_UART1_INTR_MAP_S 0 + +#define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) +/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART2_INTR_MAP 0x0000001F +#define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) +#define DPORT_APP_UART2_INTR_MAP_V 0x1F +#define DPORT_APP_UART2_INTR_MAP_S 0 + +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) +/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) +/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_EMAC_INT_MAP 0x0000001F +#define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) +#define DPORT_APP_EMAC_INT_MAP_V 0x1F +#define DPORT_APP_EMAC_INT_MAP_S 0 + +#define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) +/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM0_INTR_MAP 0x0000001F +#define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) +#define DPORT_APP_PWM0_INTR_MAP_V 0x1F +#define DPORT_APP_PWM0_INTR_MAP_S 0 + +#define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) +/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM1_INTR_MAP 0x0000001F +#define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) +#define DPORT_APP_PWM1_INTR_MAP_V 0x1F +#define DPORT_APP_PWM1_INTR_MAP_S 0 + +#define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) +/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM2_INTR_MAP 0x0000001F +#define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) +#define DPORT_APP_PWM2_INTR_MAP_V 0x1F +#define DPORT_APP_PWM2_INTR_MAP_S 0 + +#define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) +/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM3_INTR_MAP 0x0000001F +#define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) +#define DPORT_APP_PWM3_INTR_MAP_V 0x1F +#define DPORT_APP_PWM3_INTR_MAP_S 0 + +#define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) +/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_LEDC_INT_MAP 0x0000001F +#define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) +#define DPORT_APP_LEDC_INT_MAP_V 0x1F +#define DPORT_APP_LEDC_INT_MAP_S 0 + +#define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) +/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_EFUSE_INT_MAP 0x0000001F +#define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) +#define DPORT_APP_EFUSE_INT_MAP_V 0x1F +#define DPORT_APP_EFUSE_INT_MAP_S 0 + +#define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) +/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CAN_INT_MAP 0x0000001F +#define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) +#define DPORT_APP_CAN_INT_MAP_V 0x1F +#define DPORT_APP_CAN_INT_MAP_S 0 + +#define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) +/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) +#define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_APP_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) +/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RMT_INTR_MAP 0x0000001F +#define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) +#define DPORT_APP_RMT_INTR_MAP_V 0x1F +#define DPORT_APP_RMT_INTR_MAP_S 0 + +#define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) +/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PCNT_INTR_MAP 0x0000001F +#define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) +#define DPORT_APP_PCNT_INTR_MAP_V 0x1F +#define DPORT_APP_PCNT_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) +/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) +/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) +/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RSA_INTR_MAP 0x0000001F +#define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) +#define DPORT_APP_RSA_INTR_MAP_V 0x1F +#define DPORT_APP_RSA_INTR_MAP_S 0 + +#define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) +/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) +#define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) +/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) +#define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) +/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) +#define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) +/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_WDG_INT_MAP 0x0000001F +#define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) +#define DPORT_APP_WDG_INT_MAP_V 0x1F +#define DPORT_APP_WDG_INT_MAP_S 0 + +#define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) +/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TIMER_INT1_MAP 0x0000001F +#define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) +#define DPORT_APP_TIMER_INT1_MAP_V 0x1F +#define DPORT_APP_TIMER_INT1_MAP_S 0 + +#define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) +/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TIMER_INT2_MAP 0x0000001F +#define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) +#define DPORT_APP_TIMER_INT2_MAP_V 0x1F +#define DPORT_APP_TIMER_INT2_MAP_S 0 + +#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) +/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) +/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) +/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) +/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) +/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) +/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) +/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) +/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) +/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) +#define DPORT_APP_MMU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MMU_IA_INT_MAP_S 0 + +#define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) +/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) +#define DPORT_APP_MPU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MPU_IA_INT_MAP_S 0 + +#define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) +/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) +#define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_APP_CACHE_IA_INT_MAP_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) +/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) +/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) +/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) +/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) +/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) +/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) +/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) +/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) +/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) +/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) +/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) +#define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) +/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) +/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) +/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) +/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) +/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) +/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) +/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) +/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) +/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) +/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) +/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) +/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) +/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) +/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) +/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) +/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) +/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) +/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) +/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) +/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) +/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) +/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) +/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) +/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) +/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) +/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) +/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) +#define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) +/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) +/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) +/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) +/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) +/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) +/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) +/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) +/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) +/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) +/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 +/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_IA 0x00000FFF +#define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) +#define DPORT_INTERNAL_SRAM_IA_V 0xFFF +#define DPORT_INTERNAL_SRAM_IA_S 14 +/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) +#define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_AD_S 10 +/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_IA 0x0000000F +#define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) +#define DPORT_SHARE_ROM_IA_V 0xF +#define DPORT_SHARE_ROM_IA_S 6 +/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_MPU_AD 0x00000003 +#define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) +#define DPORT_SHARE_ROM_MPU_AD_V 0x3 +#define DPORT_SHARE_ROM_MPU_AD_S 4 +/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_IA (BIT(3)) +#define DPORT_APP_ROM_IA_M (BIT(3)) +#define DPORT_APP_ROM_IA_V 0x1 +#define DPORT_APP_ROM_IA_S 3 +/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_MPU_AD (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_M (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_V 0x1 +#define DPORT_APP_ROM_MPU_AD_S 2 +/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_IA (BIT(1)) +#define DPORT_PRO_ROM_IA_M (BIT(1)) +#define DPORT_PRO_ROM_IA_V 0x1 +#define DPORT_PRO_ROM_IA_S 1 +/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_MPU_AD (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_V 0x1 +#define DPORT_PRO_ROM_MPU_AD_S 0 + +#define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) +/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHBLITE_IA (BIT(10)) +#define DPORT_AHBLITE_IA_M (BIT(10)) +#define DPORT_AHBLITE_IA_V 0x1 +#define DPORT_AHBLITE_IA_S 10 +/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_V 0x1 +#define DPORT_AHBLITE_ACCESS_DENY_S 9 +/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_DENY (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_M (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_V 0x1 +#define DPORT_AHB_ACCESS_DENY_S 8 +/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PIDGEN_IA 0x00000003 +#define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) +#define DPORT_PIDGEN_IA_V 0x3 +#define DPORT_PIDGEN_IA_S 6 +/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_ARB_IA 0x00000003 +#define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) +#define DPORT_ARB_IA_V 0x3 +#define DPORT_ARB_IA_S 4 +/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) +#define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 + +#define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) +/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_RX_END (BIT(23)) +#define DPORT_PRO_RX_END_M (BIT(23)) +#define DPORT_PRO_RX_END_V 0x1 +#define DPORT_PRO_RX_END_S 23 +/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_V 0x1 +#define DPORT_PRO_SLAVE_WDATA_V_S 22 +/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_WR (BIT(21)) +#define DPORT_PRO_SLAVE_WR_M (BIT(21)) +#define DPORT_PRO_SLAVE_WR_V 0x1 +#define DPORT_PRO_SLAVE_WR_S 21 +/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_TX_END (BIT(20)) +#define DPORT_PRO_TX_END_M (BIT(20)) +#define DPORT_PRO_TX_END_V 0x1 +#define DPORT_PRO_TX_END_S 20 +/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_V 0x1 +#define DPORT_PRO_WR_BAK_TO_READ_S 19 +/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_STATE 0x00000FFF +#define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) +#define DPORT_PRO_CACHE_STATE_V 0xFFF +#define DPORT_PRO_CACHE_STATE_S 7 +/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IA 0x0000003F +#define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) +#define DPORT_PRO_CACHE_IA_V 0x3F +#define DPORT_PRO_CACHE_IA_S 1 +/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MMU_IA (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) +/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) +#define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) +/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF +#define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) +#define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_PRO_CACHE_VADDR_S 0 + +#define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) +/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/* Description: */ +#define DPORT_PRO_MMU_RDATA 0x000001FF +#define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) +#define DPORT_PRO_MMU_RDATA_V 0x1FF +#define DPORT_PRO_MMU_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) +/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) +#define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) +/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) +#define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DROM0ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) +/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) +#define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) +/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) +#define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM1ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) +/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) +#define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IROM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) +/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) +#define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) +/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_RX_END (BIT(23)) +#define DPORT_APP_RX_END_M (BIT(23)) +#define DPORT_APP_RX_END_V 0x1 +#define DPORT_APP_RX_END_S 23 +/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_WDATA_V (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_V 0x1 +#define DPORT_APP_SLAVE_WDATA_V_S 22 +/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_WR (BIT(21)) +#define DPORT_APP_SLAVE_WR_M (BIT(21)) +#define DPORT_APP_SLAVE_WR_V 0x1 +#define DPORT_APP_SLAVE_WR_S 21 +/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_TX_END (BIT(20)) +#define DPORT_APP_TX_END_M (BIT(20)) +#define DPORT_APP_TX_END_V 0x1 +#define DPORT_APP_TX_END_S 20 +/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_WR_BAK_TO_READ (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_V 0x1 +#define DPORT_APP_WR_BAK_TO_READ_S 19 +/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_STATE 0x00000FFF +#define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) +#define DPORT_APP_CACHE_STATE_V 0xFFF +#define DPORT_APP_CACHE_STATE_S 7 +/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IA 0x0000003F +#define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) +#define DPORT_APP_CACHE_IA_V 0x3F +#define DPORT_APP_CACHE_IA_S 1 +/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MMU_IA (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) +/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) +#define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) +/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_VADDR 0x07FFFFFF +#define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) +#define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_APP_CACHE_VADDR_S 0 + +#define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) +/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/* Description: */ +#define DPORT_APP_MMU_RDATA 0x000001FF +#define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) +#define DPORT_APP_MMU_RDATA_V 0x1FF +#define DPORT_APP_MMU_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) +/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) +#define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DRAM1ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) +/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) +#define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DROM0ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) +/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) +#define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) +/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) +#define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM1ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) +/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) +#define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IROM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) +/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) +#define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_APP_OPSDRAMADDR_IA_S 0 + +#define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) +/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_DISABLE_S 4 +/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_ENABLE_S 0 + +#define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) +/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORDING (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_M (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_V 0x1 +#define DPORT_PRO_CPU_RECORDING_S 0 + +#define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) +/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PID 0x00000007 +#define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) +#define DPORT_RECORD_PRO_PID_V 0x7 +#define DPORT_RECORD_PRO_PID_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) +/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) +#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) +/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) +#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) +/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) +#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) +/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) +#define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) +/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) +/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) +/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 + +#define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) +/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_DISABLE_S 4 +/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_ENABLE_S 0 + +#define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) +/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORDING (BIT(0)) +#define DPORT_APP_CPU_RECORDING_M (BIT(0)) +#define DPORT_APP_CPU_RECORDING_V 0x1 +#define DPORT_APP_CPU_RECORDING_S 0 + +#define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) +/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PID 0x00000007 +#define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) +#define DPORT_RECORD_APP_PID_V 0x7 +#define DPORT_RECORD_APP_PID_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) +/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) +#define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) +/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) +#define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) +/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) +#define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) +/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) +#define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) +/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) +/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) +/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 + +#define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) +/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_RSA_PD (BIT(0)) +#define DPORT_RSA_PD_M (BIT(0)) +#define DPORT_RSA_PD_V 0x1 +#define DPORT_RSA_PD_S 0 + +#define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) +/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE0 0x00000003 +#define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) +#define DPORT_ROM_MPU_TABLE0_V 0x3 +#define DPORT_ROM_MPU_TABLE0_S 0 + +#define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) +/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE1 0x00000003 +#define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) +#define DPORT_ROM_MPU_TABLE1_V 0x3 +#define DPORT_ROM_MPU_TABLE1_S 0 + +#define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) +/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE2 0x00000003 +#define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) +#define DPORT_ROM_MPU_TABLE2_V 0x3 +#define DPORT_ROM_MPU_TABLE2_S 0 + +#define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) +/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE3 0x00000003 +#define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) +#define DPORT_ROM_MPU_TABLE3_V 0x3 +#define DPORT_ROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) +/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE0 0x00000003 +#define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) +#define DPORT_SHROM_MPU_TABLE0_V 0x3 +#define DPORT_SHROM_MPU_TABLE0_S 0 + +#define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) +/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE1 0x00000003 +#define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) +#define DPORT_SHROM_MPU_TABLE1_V 0x3 +#define DPORT_SHROM_MPU_TABLE1_S 0 + +#define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) +/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE2 0x00000003 +#define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) +#define DPORT_SHROM_MPU_TABLE2_V 0x3 +#define DPORT_SHROM_MPU_TABLE2_S 0 + +#define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) +/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE3 0x00000003 +#define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) +#define DPORT_SHROM_MPU_TABLE3_V 0x3 +#define DPORT_SHROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) +/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE4 0x00000003 +#define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) +#define DPORT_SHROM_MPU_TABLE4_V 0x3 +#define DPORT_SHROM_MPU_TABLE4_S 0 + +#define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) +/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE5 0x00000003 +#define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) +#define DPORT_SHROM_MPU_TABLE5_V 0x3 +#define DPORT_SHROM_MPU_TABLE5_S 0 + +#define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) +/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE6 0x00000003 +#define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) +#define DPORT_SHROM_MPU_TABLE6_V 0x3 +#define DPORT_SHROM_MPU_TABLE6_S 0 + +#define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) +/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE7 0x00000003 +#define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) +#define DPORT_SHROM_MPU_TABLE7_V 0x3 +#define DPORT_SHROM_MPU_TABLE7_S 0 + +#define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) +/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE8 0x00000003 +#define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) +#define DPORT_SHROM_MPU_TABLE8_V 0x3 +#define DPORT_SHROM_MPU_TABLE8_S 0 + +#define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) +/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE9 0x00000003 +#define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) +#define DPORT_SHROM_MPU_TABLE9_V 0x3 +#define DPORT_SHROM_MPU_TABLE9_S 0 + +#define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) +/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE10 0x00000003 +#define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) +#define DPORT_SHROM_MPU_TABLE10_V 0x3 +#define DPORT_SHROM_MPU_TABLE10_S 0 + +#define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) +/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE11 0x00000003 +#define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) +#define DPORT_SHROM_MPU_TABLE11_V 0x3 +#define DPORT_SHROM_MPU_TABLE11_S 0 + +#define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) +/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE12 0x00000003 +#define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) +#define DPORT_SHROM_MPU_TABLE12_V 0x3 +#define DPORT_SHROM_MPU_TABLE12_S 0 + +#define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) +/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE13 0x00000003 +#define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) +#define DPORT_SHROM_MPU_TABLE13_V 0x3 +#define DPORT_SHROM_MPU_TABLE13_S 0 + +#define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) +/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE14 0x00000003 +#define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) +#define DPORT_SHROM_MPU_TABLE14_V 0x3 +#define DPORT_SHROM_MPU_TABLE14_S 0 + +#define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) +/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE15 0x00000003 +#define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) +#define DPORT_SHROM_MPU_TABLE15_V 0x3 +#define DPORT_SHROM_MPU_TABLE15_S 0 + +#define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) +/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE16 0x00000003 +#define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) +#define DPORT_SHROM_MPU_TABLE16_V 0x3 +#define DPORT_SHROM_MPU_TABLE16_S 0 + +#define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) +/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE17 0x00000003 +#define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) +#define DPORT_SHROM_MPU_TABLE17_V 0x3 +#define DPORT_SHROM_MPU_TABLE17_S 0 + +#define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) +/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE18 0x00000003 +#define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) +#define DPORT_SHROM_MPU_TABLE18_V 0x3 +#define DPORT_SHROM_MPU_TABLE18_S 0 + +#define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) +/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE19 0x00000003 +#define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) +#define DPORT_SHROM_MPU_TABLE19_V 0x3 +#define DPORT_SHROM_MPU_TABLE19_S 0 + +#define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) +/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE20 0x00000003 +#define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) +#define DPORT_SHROM_MPU_TABLE20_V 0x3 +#define DPORT_SHROM_MPU_TABLE20_S 0 + +#define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) +/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE21 0x00000003 +#define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) +#define DPORT_SHROM_MPU_TABLE21_V 0x3 +#define DPORT_SHROM_MPU_TABLE21_S 0 + +#define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) +/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE22 0x00000003 +#define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) +#define DPORT_SHROM_MPU_TABLE22_V 0x3 +#define DPORT_SHROM_MPU_TABLE22_S 0 + +#define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) +/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE23 0x00000003 +#define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) +#define DPORT_SHROM_MPU_TABLE23_V 0x3 +#define DPORT_SHROM_MPU_TABLE23_S 0 + +#define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) +/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE0 0x0000007F +#define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) +#define DPORT_IMMU_TABLE0_V 0x7F +#define DPORT_IMMU_TABLE0_S 0 + +#define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) +/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE1 0x0000007F +#define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) +#define DPORT_IMMU_TABLE1_V 0x7F +#define DPORT_IMMU_TABLE1_S 0 + +#define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) +/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE2 0x0000007F +#define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) +#define DPORT_IMMU_TABLE2_V 0x7F +#define DPORT_IMMU_TABLE2_S 0 + +#define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) +/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE3 0x0000007F +#define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) +#define DPORT_IMMU_TABLE3_V 0x7F +#define DPORT_IMMU_TABLE3_S 0 + +#define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) +/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE4 0x0000007F +#define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) +#define DPORT_IMMU_TABLE4_V 0x7F +#define DPORT_IMMU_TABLE4_S 0 + +#define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) +/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE5 0x0000007F +#define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) +#define DPORT_IMMU_TABLE5_V 0x7F +#define DPORT_IMMU_TABLE5_S 0 + +#define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) +/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE6 0x0000007F +#define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) +#define DPORT_IMMU_TABLE6_V 0x7F +#define DPORT_IMMU_TABLE6_S 0 + +#define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) +/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE7 0x0000007F +#define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) +#define DPORT_IMMU_TABLE7_V 0x7F +#define DPORT_IMMU_TABLE7_S 0 + +#define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) +/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE8 0x0000007F +#define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) +#define DPORT_IMMU_TABLE8_V 0x7F +#define DPORT_IMMU_TABLE8_S 0 + +#define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) +/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE9 0x0000007F +#define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) +#define DPORT_IMMU_TABLE9_V 0x7F +#define DPORT_IMMU_TABLE9_S 0 + +#define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) +/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE10 0x0000007F +#define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) +#define DPORT_IMMU_TABLE10_V 0x7F +#define DPORT_IMMU_TABLE10_S 0 + +#define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) +/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE11 0x0000007F +#define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) +#define DPORT_IMMU_TABLE11_V 0x7F +#define DPORT_IMMU_TABLE11_S 0 + +#define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) +/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE12 0x0000007F +#define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) +#define DPORT_IMMU_TABLE12_V 0x7F +#define DPORT_IMMU_TABLE12_S 0 + +#define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) +/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE13 0x0000007F +#define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) +#define DPORT_IMMU_TABLE13_V 0x7F +#define DPORT_IMMU_TABLE13_S 0 + +#define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) +/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE14 0x0000007F +#define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) +#define DPORT_IMMU_TABLE14_V 0x7F +#define DPORT_IMMU_TABLE14_S 0 + +#define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) +/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE15 0x0000007F +#define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) +#define DPORT_IMMU_TABLE15_V 0x7F +#define DPORT_IMMU_TABLE15_S 0 + +#define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) +/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE0 0x0000007F +#define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) +#define DPORT_DMMU_TABLE0_V 0x7F +#define DPORT_DMMU_TABLE0_S 0 + +#define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) +/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE1 0x0000007F +#define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) +#define DPORT_DMMU_TABLE1_V 0x7F +#define DPORT_DMMU_TABLE1_S 0 + +#define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) +/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE2 0x0000007F +#define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) +#define DPORT_DMMU_TABLE2_V 0x7F +#define DPORT_DMMU_TABLE2_S 0 + +#define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) +/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE3 0x0000007F +#define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) +#define DPORT_DMMU_TABLE3_V 0x7F +#define DPORT_DMMU_TABLE3_S 0 + +#define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) +/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE4 0x0000007F +#define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) +#define DPORT_DMMU_TABLE4_V 0x7F +#define DPORT_DMMU_TABLE4_S 0 + +#define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) +/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE5 0x0000007F +#define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) +#define DPORT_DMMU_TABLE5_V 0x7F +#define DPORT_DMMU_TABLE5_S 0 + +#define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) +/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE6 0x0000007F +#define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) +#define DPORT_DMMU_TABLE6_V 0x7F +#define DPORT_DMMU_TABLE6_S 0 + +#define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) +/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE7 0x0000007F +#define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) +#define DPORT_DMMU_TABLE7_V 0x7F +#define DPORT_DMMU_TABLE7_S 0 + +#define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) +/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE8 0x0000007F +#define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) +#define DPORT_DMMU_TABLE8_V 0x7F +#define DPORT_DMMU_TABLE8_S 0 + +#define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) +/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE9 0x0000007F +#define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) +#define DPORT_DMMU_TABLE9_V 0x7F +#define DPORT_DMMU_TABLE9_S 0 + +#define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) +/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE10 0x0000007F +#define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) +#define DPORT_DMMU_TABLE10_V 0x7F +#define DPORT_DMMU_TABLE10_S 0 + +#define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) +/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE11 0x0000007F +#define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) +#define DPORT_DMMU_TABLE11_V 0x7F +#define DPORT_DMMU_TABLE11_S 0 + +#define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) +/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE12 0x0000007F +#define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) +#define DPORT_DMMU_TABLE12_V 0x7F +#define DPORT_DMMU_TABLE12_S 0 + +#define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) +/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE13 0x0000007F +#define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) +#define DPORT_DMMU_TABLE13_V 0x7F +#define DPORT_DMMU_TABLE13_S 0 + +#define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) +/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE14 0x0000007F +#define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) +#define DPORT_DMMU_TABLE14_V 0x7F +#define DPORT_DMMU_TABLE14_S 0 + +#define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) +/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE15 0x0000007F +#define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) +#define DPORT_DMMU_TABLE15_V 0x7F +#define DPORT_DMMU_TABLE15_S 0 + +#define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) +/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) +/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_PRO_INTRUSION_RECORD 0x0000000F +#define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) +#define DPORT_PRO_INTRUSION_RECORD_V 0xF +#define DPORT_PRO_INTRUSION_RECORD_S 0 + +#define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) +/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) +/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_APP_INTRUSION_RECORD 0x0000000F +#define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) +#define DPORT_APP_INTRUSION_RECORD_V 0xF +#define DPORT_APP_INTRUSION_RECORD_S 0 + +#define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) +/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PD_S 3 +/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PU_S 2 +/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AGC_MEM_FORCE_PD (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_V 0x1 +#define DPORT_AGC_MEM_FORCE_PD_S 1 +/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_AGC_MEM_FORCE_PU (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_V 0x1 +#define DPORT_AGC_MEM_FORCE_PU_S 0 + +#define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) +/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/* Description: */ +#define DPORT_MMU_IA_INT_EN 0x00FFFFFF +#define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) +#define DPORT_MMU_IA_INT_EN_V 0xFFFFFF +#define DPORT_MMU_IA_INT_EN_S 0 + +#define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) +/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ +/* Description: */ +#define DPORT_MPU_IA_INT_EN 0x0001FFFF +#define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) +#define DPORT_MPU_IA_INT_EN_V 0x1FFFF +#define DPORT_MPU_IA_INT_EN_S 0 + +#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) +/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/* Description: */ +#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF +#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) +#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF +#define DPORT_CACHE_IA_INT_EN_S 0 + +#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) +/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SW_BOOTLOADER_SEL (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_V 0x1 +#define DPORT_SW_BOOTLOADER_SEL_S 0 + +#define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) +/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) +#define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI3_DMA_CHAN_SEL_S 4 +/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) +#define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI2_DMA_CHAN_SEL_S 2 +/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) +#define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI1_DMA_CHAN_SEL_S 0 + +#define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) +/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 +#define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) +#define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 +#define DPORT_PRO_OUT_VECBASE_SEL_S 0 + +#define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) +/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/* Description: */ +#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) +#define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_S 0 + +#define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) +/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_APP_OUT_VECBASE_SEL 0x00000003 +#define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) +#define DPORT_APP_OUT_VECBASE_SEL_V 0x3 +#define DPORT_APP_OUT_VECBASE_SEL_S 0 + +#define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) +/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/* Description: */ +#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) +#define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_APP_OUT_VECBASE_REG_S 0 + +#define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) +/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ +/* Description: */ +#define DPORT_DATE 0x0FFFFFFF +#define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) +#define DPORT_DATE_V 0xFFFFFFF +#define DPORT_DATE_S 0 +#define DPORT_DPORT_DATE_VERSION 0x1605190 + +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H */ diff --git a/arch/xtensa/src/esp32/chip/esp32_rtccntl.h b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h new file mode 100644 index 00000000000..12f5ba07a91 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h @@ -0,0 +1,2004 @@ +/**************************************************************************** + * arch/xtensa/src/common/esp32_rtccnt.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: BIAS_CORE force power up*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 +/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: BIAS_CORE force power down*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 +/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: BIAS_CORE follow CK8M*/ +#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 +/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: BIAS_I2C force power up*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: BIAS_I2C force power down*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 +/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: BIAS_I2C follow CK8M*/ +#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 +/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: BIAS_SLEEP force no sleep*/ +#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 +/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP force sleep*/ +#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 +/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP follow CK8M*/ +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: To indicate the register is updated*/ +#define RTC_CNTL_TIME_VALID (BIT(30)) +#define RTC_CNTL_TIME_VALID_M (BIT(30)) +#define RTC_CNTL_TIME_VALID_V 0x1 +#define RTC_CNTL_TIME_VALID_S 30 + +#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIME_LO 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) +#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_S 0 + +#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIME_HI 0x0000FFFF +#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) +#define RTC_CNTL_TIME_HI_V 0xFFFF +#define RTC_CNTL_TIME_HI_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: sleep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: sleep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: ULP-coprocessor force wake up*/ +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 +/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: touch controller force wake up*/ +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: PLL_I2C power up otherwise power down*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x000007FF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FF +#define RTC_CNTL_WAKEUP_ENA_S 11 +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch interrupt*/ +#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable RTC time valid interrupt*/ +#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt raw*/ +#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 +/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INT_ST_S 6 +/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_ST (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_V 0x1 +#define RTC_CNTL_SAR_INT_ST_S 5 +/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INT_CLR_S 6 +/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_CLR (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_V 0x1 +#define RTC_CNTL_SAR_INT_CLR_S 5 +/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Clear RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable control XTAL by external pads*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0000000F +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0xF +#define RTC_CNTL_REJECT_CAUSE_S 28 +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 +/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: enable SDIO reject*/ +#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 +#define RTC_CNTL_SDIO_REJECT_EN_S 25 +/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: enable GPIO reject*/ +#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 +#define RTC_CNTL_GPIO_REJECT_EN_S 24 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: CPU period sel*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 +#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: RST_BIAS_I2C*/ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ +/*description: DBG_ATTEN*/ +#define RTC_CNTL_DBG_ATTEN 0x00000003 +#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) +#define RTC_CNTL_DBG_ATTEN_V 0x3 +#define RTC_CNTL_DBG_ATTEN_S 24 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: RTC_REG force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(31)) +#define RTC_CNTL_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 31 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_FORCE_PD (BIT(30)) +#define RTC_CNTL_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 +/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: N/A*/ +#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 +#define RTC_CNTL_SCK_DCAP_FORCE_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_V 0x1 +#define RTC_CNTL_PWC_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_V 0x1 +#define RTC_CNTL_PWC_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: enable power down digital core in sleep*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: digital core force no ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: enable RTC WDT*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 +#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 +/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 +#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) +/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: DTEST_RTC*/ +#define RTC_CNTL_DTEST_RTC 0x00000003 +#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) +#define RTC_CNTL_DTEST_RTC_V 0x3 +#define RTC_CNTL_DTEST_RTC_S 30 +/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ENT_RTC*/ +#define RTC_CNTL_ENT_RTC (BIT(29)) +#define RTC_CNTL_ENT_RTC_M (BIT(29)) +#define RTC_CNTL_ENT_RTC_V 0x1 +#define RTC_CNTL_ENT_RTC_S 29 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) +#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_S 0 + +#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) +/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32N_HOLD_FORCE_S 17 +/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32P_HOLD_FORCE_S 16 +/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 +/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 +/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 +/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 +/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 +/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 +/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 +/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 +/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 +/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 +/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 +/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 +/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 +/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 +/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 +/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: brown out detect*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ +/*description: brown out threshold*/ +#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 +#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) +#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 +#define RTC_CNTL_DBROWN_OUT_THRES_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) +#define RTC_MEM_CRC_FINISH (BIT(31)) +#define RTC_MEM_CRC_FINISH_M (BIT(31)) +#define RTC_MEM_CRC_FINISH_V 0x1 +#define RTC_MEM_CRC_FINISH_S (31) +#define RTC_MEM_CRC_LEN (0x7ff) +#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) +#define RTC_MEM_CRC_LEN_V (0x7ff) +#define RTC_MEM_CRC_LEN_S (20) +#define RTC_MEM_CRC_ADDR (0x7ff) +#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) +#define RTC_MEM_CRC_ADDR_V (0x7ff) +#define RTC_MEM_CRC_ADDR_S (9) +#define RTC_MEM_CRC_START (BIT(8)) +#define RTC_MEM_CRC_START_M (BIT(8)) +#define RTC_MEM_CRC_START_V 0x1 +#define RTC_MEM_CRC_START_S (8) +#define RTC_MEM_PID_CONF (0xff) +#define RTC_MEM_PID_CONF_M (0xff) +#define RTC_MEM_PID_CONF_V (0xff) +#define RTC_MEM_PID_CONF_S (0) + +#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 + +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H */ diff --git a/arch/xtensa/src/esp32/chip/esp32_soc.h b/arch/xtensa/src/esp32/chip/esp32_soc.h new file mode 100644 index 00000000000..20405c067db --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_soc.h @@ -0,0 +1,356 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip/esp32_soc.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Bits */ + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 + +#define PRO_CPU_NUM (0) +#define APP_CPU_NUM (1) + +/* Registers Operation */ + +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#define BIT(nr) (1UL << (nr)) + +/* Write value to register */ + +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +/* Read value from register */ + +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +/* Get bit or get bits from register */ + +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +/* Set bit or set bits to register */ + +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +/* Clear bit or clear bits of register */ + +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +/* Set bits of register controlled by mask */ + +#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) + +/* Get field from register, used when _f is not left shifted by _f##_S */ + +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f)) + +/* Set field to register, used when _f is not left shifted by _f##_S */ + +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) + +/* Set field value from a variable, used when _f is not left shifted by _f##_S */ + +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +/* Get field value from a variable, used when _f is left shifted by _f##_S */ + +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +/* Set field value to a variable, used when _f is not left shifted by _f##_S */ + +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +/* Set field value to a variable, used when _f is left shifted by _f##_S */ + +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +/* Generate a value from a field value, used when _f is not left shifted by _f##_S */ + +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +/* Generate a value from a field value, used when _f is left shifted by _f##_S */ + +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +/* Read value from register */ + +#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +/* Write value to register */ + +#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +/* Clear bits of register controlled by mask */ + +#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +/* Set bits of register controlled by mask */ + +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) */ + +/* Get bits of register controlled by mask */ + +#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) + +/* Get bits of register controlled by highest bit and lowest bit */ + +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +/* Set bits of register controlled by mask and shift */ + +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +/* Get field of register */ + +#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) + +/* Periheral Clock */ + +#define APB_CLK_FREQ_ROM 26*1000000 +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ 80*1000000 /* Unit: Hz */ +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) /* 80MHz divided by 16 */ +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */ + +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SARADC_BASE 0x3ff48800 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define DR_REG_PWM2_BASE 0x3ff6F000 +#define DR_REG_PWM3_BASE 0x3ff70000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE + +/* Interrupt hardware source table + * This table is decided by hardware, don't touch this. + */ + +#define ETS_WIFI_MAC_INTR_SOURCE 0 /* Interrupt of WiFi MAC, level */ +#define ETS_WIFI_MAC_NMI_SOURCE 1 /* Interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI */ +#define ETS_WIFI_BB_INTR_SOURCE 2 /* Interrupt of WiFi BB, level, we can do some calibartion */ +#define ETS_BT_MAC_INTR_SOURCE 3 /* will be cancelled */ +#define ETS_BT_BB_INTR_SOURCE 4 /* Interrupt of BT BB, level */ +#define ETS_BT_BB_NMI_SOURCE 5 /* Interrupt of BT BB, NMI, use if BB have bug to fix in NMI */ +#define ETS_RWBT_INTR_SOURCE 6 /* Interrupt of RWBT, level */ +#define ETS_RWBLE_INTR_SOURCE 7 /* Interrupt of RWBLE, level */ +#define ETS_RWBT_NMI_SOURCE 8 /* Interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI */ +#define ETS_RWBLE_NMI_SOURCE 9 /* Interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI */ +#define ETS_SLC0_INTR_SOURCE 10 /* Interrupt of SLC0, level */ +#define ETS_SLC1_INTR_SOURCE 11 /* Interrupt of SLC1, level */ +#define ETS_UHCI0_INTR_SOURCE 12 /* Interrupt of UHCI0, level */ +#define ETS_UHCI1_INTR_SOURCE 13 /* Interrupt of UHCI1, level */ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14 /* Interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission */ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15 /* Interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission */ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 /* Interrupt of TIMER_GROUP0, WATCHDOG, level */ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 /* Interrupt of TIMER_GROUP0, LACT, level */ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18 /* Interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission */ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19 /* Interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission */ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 /* Interrupt of TIMER_GROUP1, WATCHDOG, level */ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 /* Interrupt of TIMER_GROUP1, LACT, level */ +#define ETS_GPIO_INTR_SOURCE 22 /* Interrupt of GPIO, level */ +#define ETS_GPIO_NMI_SOURCE 23 /* Interrupt of GPIO, NMI */ +#define ETS_FROM_CPU_INTR0_SOURCE 24 /* Interrupt0 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR1_SOURCE 25 /* Interrupt1 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR2_SOURCE 26 /* Interrupt2 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR3_SOURCE 27 /* Interrupt3 generated from a CPU, level */ +#define ETS_SPI0_INTR_SOURCE 28 /* Interrupt of SPI0, level, SPI0 is for Cache Access, do not use this */ +#define ETS_SPI1_INTR_SOURCE 29 /* Interrupt of SPI1, level, SPI1 is for flash read/write, do not use this */ +#define ETS_SPI2_INTR_SOURCE 30 /* Interrupt of SPI2, level */ +#define ETS_SPI3_INTR_SOURCE 31 /* Interrupt of SPI3, level */ +#define ETS_I2S0_INTR_SOURCE 32 /* Interrupt of I2S0, level */ +#define ETS_I2S1_INTR_SOURCE 33 /* Interrupt of I2S1, level */ +#define ETS_UART0_INTR_SOURCE 34 /* Interrupt of UART0, level */ +#define ETS_UART1_INTR_SOURCE 35 /* Interrupt of UART1, level */ +#define ETS_UART2_INTR_SOURCE 36 /* Interrupt of UART2, level */ +#define ETS_SDIO_HOST_INTR_SOURCE 37 /* Interrupt of SD/SDIO/MMC HOST, level */ +#define ETS_ETH_MAC_INTR_SOURCE 38 /* Interrupt of ethernet mac, level */ +#define ETS_PWM0_INTR_SOURCE 39 /* Interrupt of PWM0, level, Reserved */ +#define ETS_PWM1_INTR_SOURCE 40 /* Interrupt of PWM1, level, Reserved */ +#define ETS_PWM2_INTR_SOURCE 41 /* Interrupt of PWM2, level */ +#define ETS_PWM3_INTR_SOURCE 42 /* Interruot of PWM3, level */ +#define ETS_LEDC_INTR_SOURCE 43 /* Interrupt of LED PWM, level */ +#define ETS_EFUSE_INTR_SOURCE 44 /* Interrupt of efuse, level, not likely to use */ +#define ETS_CAN_INTR_SOURCE 45 /* Interrupt of can, level */ +#define ETS_RTC_CORE_INTR_SOURCE 46 /* Interrupt of rtc core, level, include rtc watchdog */ +#define ETS_RMT_INTR_SOURCE 47 /* Interrupt of remote controller, level */ +#define ETS_PCNT_INTR_SOURCE 48 /* Interrupt of pluse count, level */ +#define ETS_I2C_EXT0_INTR_SOURCE 49 /* Interrupt of I2C controller1, level */ +#define ETS_I2C_EXT1_INTR_SOURCE 50 /* Interrupt of I2C controller0, level */ +#define ETS_RSA_INTR_SOURCE 51 /* Interrupt of RSA accelerator, level */ +#define ETS_SPI1_DMA_INTR_SOURCE 52 /* Interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this */ +#define ETS_SPI2_DMA_INTR_SOURCE 53 /* Interrupt of SPI2 DMA, level */ +#define ETS_SPI3_DMA_INTR_SOURCE 54 /* Interrupt of SPI3 DMA, level */ +#define ETS_WDT_INTR_SOURCE 55 /* will be cancelled */ +#define ETS_TIMER1_INTR_SOURCE 56 /* will be cancelled */ +#define ETS_TIMER2_INTR_SOURCE 57 /* will be cancelled */ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58 /* Interrupt of TIMER_GROUP0, TIMER0, EDGE */ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59 /* Interrupt of TIMER_GROUP0, TIMER1, EDGE */ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60 /* Interrupt of TIMER_GROUP0, WATCH DOG, EDGE */ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62 /* Interrupt of TIMER_GROUP1, TIMER0, EDGE */ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63 /* Interrupt of TIMER_GROUP1, TIMER1, EDGE */ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64 /* Interrupt of TIMER_GROUP1, WATCHDOG, EDGE */ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ +#define ETS_MMU_IA_INTR_SOURCE 66 /* Interrupt of MMU Invalid Access, LEVEL */ +#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */ +#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */ + +/* Interrupt cpu using table */ +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host VHCI Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level BT Controller + * 6 1 timer RTOS Tick RTOS Tick + * 7 1 software Reserved Reserved + * 8 1 extern level BLE Controller + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer Internal Timer + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + *************************************************************************************************************/ + +/* CPU0 Interrupt number reserved, not touch this. */ + +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */ + +/* CPU0 Intrrupt number used in ROM, should be cancelled in SDK */ + +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 + +/* Other interrupt numbers should be managed by the user */ + +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H */ diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h new file mode 100644 index 00000000000..8b3530cc26b --- /dev/null +++ b/arch/xtensa/src/esp32/chip_macros.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/* Macro to get the current core ID. Only uses the reg given as an argument. + * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO + * processor and 0xabab on the APP CPU. We distinguish between the two by + * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + */ + + .macro getcoreid reg + rsr.prid \reg + bbci \reg, 1, 1f + movi \reg, 1 + j 2f +1: + movi \reg, 0 +2: + .endm + +#endif /* __ASSEMBLY */ +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H */ diff --git a/arch/xtensa/src/esp32/esp32_allocateheap.c b/arch/xtensa/src/esp32/esp32_allocateheap.c new file mode 100644 index 00000000000..4e613adc6d0 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_allocateheap.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_allocateheap.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} + +/**************************************************************************** + * Name: xtensa_add_region + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void xtensa_add_region(void) +{ +} +#endif diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.h b/arch/xtensa/src/esp32/esp32_clockconfig.h new file mode 100644 index 00000000000..a552f9b33d2 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_clockconfig.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_clockconfig.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_clockconfig + * + * Description: + * Called to initialize the ESP32. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32_clockconfig(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpuindex.S b/arch/xtensa/src/esp32/esp32_cpuindex.S new file mode 100644 index 00000000000..0059f256e26 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuindex.S @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/exp32_cpuindex.S + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + .file "xtensa_cpumacros.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip_macros.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * If TLS is enabled, then the RTOS can get this information from the TLS + * info structure. Otherwise, the MCU-specific logic must provide some + * mechanism to provide the CPU index. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + + .text + .align 4 + .global up_cpu_index + .type up_cpu_index, @function + +up_cpu_index: + getcoreid a2 + ret + .size up_cpu_index, . - up_cpu_index diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c new file mode 100644 index 00000000000..038a2851c2a --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -0,0 +1,219 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpustart.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" +#include "esp32_region.h" + +#ifdef CONFIG_SMP + +#warning REVISIT Need ets_set_appcpu_boot_addr() prototype +void ets_set_appcpu_boot_addr(uint32_t); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_appcpu_started; +static sem_t g_appcpu_interlock; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_registerdump + ****************************************************************************/ + +#if 0 /* Was useful in solving some startup problems */ +static inline void xtensa_registerdump(FAR struct tcb_s *tcb) +{ + _info("CPU%d:\n", up_cpu_index()); + + /* Dump the startup registers */ + /* To be provided */ +} +#else +# define xtensa_registerdump(tcb) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_start_handler + * + * Description: + * This is the handler for SGI1. This handler simply returns from the + * interrupt, restoring the state of the new task at the head of the ready + * to run list. + * + * Input Parameters: + * Standard interrupt handling + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int xtensa_start_handler(int irq, FAR void *context) +{ + FAR struct tcb_s *tcb; + + sinfo("CPU%d Started\n", up_cpu_index()); + + /* Handle interlock*/ + + g_appcpu_started = true; + sem_post(&g_appcpu_interlock); + + /* Reset scheduler parameters */ + + tcb = this_task(); + sched_resume_scheduler(tcb); + + /* Move CPU0 exception vectors to IRAM */ + + asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); + + /* Make page 0 access raise an exception */ + + esp32_region_protection(); + + /* Dump registers so that we can see what is going to happen on return */ + + xtensa_registerdump(tcb); + + /* Then switch contexts. This instantiates the exception context of the + * tcb at the head of the assigned task list. In this case, this should + * be the CPUs NULL task. + */ + + xtensa_context_restore(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_start + * + * Description: + * In an SMP configution, only one CPU is initially active (CPU 0). System + * initialization occurs on that single thread. At the completion of the + * initialization of the OS, just before beginning normal multitasking, + * the additional CPUs would be started by calling this function. + * + * Each CPU is provided the entry point to is IDLE task when started. A + * TCB for each CPU's IDLE task has been initialized and placed in the + * CPU's g_assignedtasks[cpu] list. Not stack has been alloced or + * initialized. + * + * The OS initialization logic calls this function repeatedly until each + * CPU has been started, 1 through (CONFIG_SMP_NCPUS-1). + * + * Input Parameters: + * cpu - The index of the CPU being started. This will be a numeric + * value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU + * 0 is already active) + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_start(int cpu) +{ + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + if (!g_appcpu_started) + { + uint32_t regval; + int ret; + + /* Start CPU1 */ + + sinfo("Starting CPU%d\n", cpu); + sem_init(&g_appcpu_interlock, 0, 0) + + regval = getreg32(DPORT_APPCPU_CTRL_B_REG); + regval |= DPORT_APPCPU_CLKGATE_EN; + putreg32(regval, DPORT_APPCPU_CTRL_B_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_C_REG); + regval ~= DPORT_APPCPU_RUNSTALL; + putreg32(regval, DPORT_APPCPU_CTRL_C_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_A_REG); + regval |= DPORT_APPCPU_RESETTING; + putreg32(regval, DPORT_APPCPU_CTRL_A_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_A_REG); + regval &= ~DPORT_APPCPU_RESETTING; + putreg32(regval, DPORT_APPCPU_CTRL_A_REG); + + /* Set the CPU1 start address */ + + ets_set_appcpu_boot_addr((uint32_t)xtensa_start_handler); + + /* And way for the initial task to run on CPU1 */ + + while (!app_cpu_started) + { + ret = sem_wait(&g_appcpu_interlock); + if (ret < 0) + { + DEBUGASSERT(errno == EINTR); + } + } + + sem_destroy(&g_appcpu_interlock); + } +} + +#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c new file mode 100644 index 00000000000..5490e614e36 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_intdecode.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip/esp32_dport.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_int_decode + * + * Description: + * Determine the peripheral that geneated the interrupt and dispatch + * handling to the registered interrupt handler via xtensa_irq_dispatch(). + * + * Input Parameters: + * regs - Saves processor state on the stack + * + * Returned Value: + * Normally the same vale as regs is returned. But, in the event of an + * interrupt level context switch, the returned value will, instead point + * to the saved processor state in the TCB of the newly started task. + * + ****************************************************************************/ + +uint32_t *xtensa_int_decode(uint32_t *regs) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t mask; + int regndx; + int bit; + int baseirq; + +#ifdef CONFIG_SMP + int cpu; + + /* Select PRO or APP interrupt status registers */ + + cpu = up_cpu_index(); + if (cpu == 0) + { + regaddr = DPORT_PRO_INTR_STATUS_0_REG; + } + else +#endif + { + regaddr = DPORT_APP_INTR_STATUS_0_REG; + } + + /* Process each pending interrupt in each of the three interrupt status + * registers. + */ + + for (regndx = 0, baseirq = XTENSA_IRQ_SREG0; + regndx < 3; + regndx++, baseirq += 32, regaddr += sizeof(uint32_t)) + { + /* Fetch the next register status register */ + + regval = getreg32(regaddr); + + /* Decode and dispatch each pending bit in the interrupt status + * register. + */ + + for (bit = 0; regval != 0 && bit < 32; bit++) + { + /* Check if this interrupt is pending */ + + mask = (1 << bit); + if ((regval & mask) != 0) + { + /* Yes.. Dispatch the interrupt. Note that regs may be + * altered in the case of an interrupt level context switch. + */ + + regs = xtensa_irq_dispatch(baseirq + bit, regs); + + /* Clear this bit in the sampled status register so that + * perhaps we can exit this loop sooner. + */ + + regval &= ~mask; + } + } + } + + return regs; +} diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c new file mode 100644 index 00000000000..2fa02c8e931 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_irq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_irq_dump + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void esp32_irq_dump(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} +#else +# define esp32_irq_dump(msg, irq) +#endif + +/**************************************************************************** + * Name: esp32_nmi + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +static int esp32_nmi(int irq, FAR void *context) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_irq_initialize + ****************************************************************************/ + +void xtensa_irq_initialize(void) +{ + /* Disable all interrupts */ +#warning Missing logic + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Colorize the interrupt stack for debug purposes */ + +#warning Missing logic +#endif + + /* Set all interrupts (and exceptions) to the default priority */ +#warning Missing logic + + /* Attach all other processor exceptions (except reset and sys tick) */ +#warning Missing logic + + esp32_irq_dump("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ +#warning Missing logic + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32/esp32_region.c b/arch/xtensa/src/esp32/esp32_region.c new file mode 100644 index 00000000000..1e64aa7e32f --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_region.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_region.c + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from code originally provided Espressif Systems: + * + * C opyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_protected_pages[] = +{ + 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000 +}; + +#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_write_dtlb and xtensa_write_itlb + * + * Description: + * Functions to set page attributes for Region Protection option in the + * CPU. See Xtensa ISA Reference manual for explanation of arguments + * (section 4.6.3.2). + * + ****************************************************************************/ + +static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "wdtlb %1, %0\n" + "dsync\n" + : : "r" (vpn), "r" (attr) + ); +} + +static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "witlb %1, %0\n" + "isync\n" + : : "r" (vpn), "r" (attr) + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32_region_protection(void) +{ + int i; + + for (i = 0; i < NPROTECTED_PAGES; ++i) + { + xtensa_write_dtlb(g_protected_pages[i], 0xf); + xtensa_write_itlb(g_protected_pages[i], 0xf); + } + + xtensa_write_dtlb(0x20000000, 0); + xtensa_write_itlb(0x20000000, 0); +} diff --git a/arch/xtensa/src/esp32/esp32_region.h b/arch/xtensa/src/esp32/esp32_region.h new file mode 100644 index 00000000000..6a39afad09d --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_region.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_region.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32_region_protection(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c new file mode 100644 index 00000000000..3d1ca5c9b98 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/xtensa/src/common/esp32_start.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Basic initialize sequence derives from logic originally provided by + * Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "xtensa_attr.h" +#include "chip/esp32_dport.h" +#include "chip/esp32_rtccntl.h" +#include "esp32_clockconfig.h" +#include "esp32_region.h" +#include "esp32_start.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * We arrive here after the bootloader finished loading the program from + * flash. The hardware is mostly uninitialized, and the app CPU is in + * reset. We do have a stack, so we can do the initialization in C. + * + * The app CPU will remain in reset unless CONFIG_SMP is selected and + * up_cpu_start() is called later in the bring-up sequeuence. + * + ****************************************************************************/ + +void IRAM_ATTR __start(void) +{ + uint32_t regval; + + /* Kill the watchdog timer */ + + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); + regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN; + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + + regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */ + regval &= ~(1 << 14); + putreg32(regval, 0x6001f048); + + /* Make page 0 access raise an exception */ + + esp32_region_protection(); + + /* Move CPU0 exception vectors to IRAM */ + + asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); + + /* Set .bss to zero */ + + memset(&_sbss, 0, (&_ebss - &_sbss) * sizeof(_sbss)); + +#warning Missing logic: Initialize .data + +#warning REVISIT heap. Do what with non-heterogeneous memory? +#warning REVISIT belongs in up_allocateheap() +#if 0 + /* Initialize heap allocator */ + + heap_alloc_caps_init(); +#endif + + /* Make sure that the APP_CPU is disabled for now */ + + regval = getreg32(DPORT_APPCPU_CTRL_B_REG); + regval &= ~DPORT_APPCPU_CLKGATE_EN; + putreg32(regval, DPORT_APPCPU_CTRL_B_REG); + + /* Set CPU frequency configured in board.h */ + + esp32_clockconfig(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + xtensa_earlyserialinit(); +#endif + + /* Initialize onboard resources */ + + esp32_board_initialize(); + +#warning These belong elsewhere +#if 0 + ets_setup_syscalls(); + esp_ipc_init(); + spi_flash_init(); +#endif + + /* Bring up NuttX */ + + os_start(); +} diff --git a/arch/xtensa/src/esp32/esp32_start.h b/arch/xtensa/src/esp32/esp32_start.h new file mode 100644 index 00000000000..d836f40147f --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_start.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_start.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_START_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_board_initialize + * + * Description: + * All ESP32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_board_initialize(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_START_H */ diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c new file mode 100644 index 00000000000..982b3bfa3c7 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -0,0 +1,222 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_timerisr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "clock/clock.h" +#include "xtensa_timer.h" +#include "xtensa.h" + +/**************************************************************************** + * Private data + ****************************************************************************/ + +static uint32_t g_tick_divisor; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xtensa_getcount, xtensa_getcompare, xtensa_setcompare, and + * xtensa_enable_timer + * + * Description: + * Lower level operations on Xtensa special registers. + * + ****************************************************************************/ + +/* Return the current value of the cyle count register */ + +static inline uint32_t xtensa_getcount(void) +{ + uint32_t count; + + __asm__ __volatile__ + ( + "rsr %0, CCOUNT" : "=r"(count) + ); + + return count; +} + +/* Return the old value of the compare register */ + +static inline uint32_t xtensa_getcompare(void) +{ + uint32_t compare; + + __asm__ __volatile__ + ( + "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) + ); + + return compare; +} + +/* Set the value of the compare register */ + +static inline void xtensa_setcompare(uint32_t compare) +{ + __asm__ __volatile__ + ( + "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) + ); +} + +/* Enable the timer interrupt. NOTE: This is non-atomic but safe in this + * context because this occurs early in the initialization sequence. + */ + +static inline void xtensa_enable_timer(void) +{ + __asm__ __volatile__ + ( + "movi a3, %0\n" + "rsr a2, INTENABLE\n" + "or a2, a2, a3\n" + "wsr a2, INTENABLE\n" + : : "I"(XT_TIMER_INTEN) : "a2", "a3" + ); +} + +/**************************************************************************** + * Function: esp32_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + * Xtensa timers work by comparing a cycle counter with a preset value. + * Once the match occurs an interrupt is generated, and the handler has to + * set a new cycle count into the comparator. To avoid clock drift due to + * interrupt latency, the new cycle count is computed from the old, not the + * time the interrupt was serviced. However if a timer interrupt is ever + * serviced more than one tick late, it is necessary to process multiple + * ticks until the new cycle count is in the future, otherwise the next + * timer interrupt would not occur until after the cycle counter had + * wrapped (2^32 cycles later). + * + ****************************************************************************/ + +static int esp32_timerisr(int irq, uint32_t *regs) +{ + uint32_t divisor; + uint32_t compare; + uint32_t diff; + + divisor = g_tick_divisor; + do + { + /* Increment the compare register for the next tick */ + + compare = xtensa_getcompare(); + xtensa_setcompare(compare + divisor); + + /* Process one timer tick */ + + sched_process_timer(); + + /* Check if we are falling behind and need to process multiple timer + * interrupts. + */ + + diff = xtensa_getcount() - compare; + } + while (diff < divisor); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xtensa_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void xtensa_timer_initialize(void) +{ + uint64_t divisor; + uint32_t count; + + /* Configured the timer0 as the system timer. + * + * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec + * = BOARD_CLOCK_FREQUENCY / (ticks_per_usec * 1000000) + * = (1000000 * BOARD_CLOCK_FREQUENCY) / ticks_per_usec + * + * A long long calculation is used to preserve accuracy in all cases. + */ + + divisor = (1000000ull * (uint64_t)BOARD_CLOCK_FREQUENCY) / CONFIG_USEC_PER_TICK; + DEBUGASSERT(divisor <= UINT32_MAX) + g_tick_divisor = divisor; + + /* Set up periodic timer */ + + count = xtensa_getcount(); + xtensa_setcompare(count + divisor); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); + + /* Enable the timer interrupt at the device level */ + + xtensa_enable_timer(); + + /* And enable the timer interrupt */ + + up_enable_irq(XTENSA_IRQ_TIMER0); +} diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig new file mode 100644 index 00000000000..073954b7d6b --- /dev/null +++ b/arch/xtensa/src/lx6/Kconfig @@ -0,0 +1,31 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_LX6 + +choice + prompt "LX6 implementation" + default ARCH_CHIP_ESP32 + +config ARCH_CHIP_ESP32 + bool "Expressif ESP32" + ---help--- + The ESP32 is a dual-core system with two Harvard Architecture Xtensa + LX6 CPUs. All embedded memory, external memory and peripherals are + located on the data bus and/or the instruction bus of these CPUs. + With some minor exceptions the address mapping of two CPUs is + symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded + memory via DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + +endchoice # LX6 implementation + +source arch/xtensa/src/esp32/Kconfig + +endif # ARCH_CHIP_LX6 diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs new file mode 100644 index 00000000000..b18659fe551 --- /dev/null +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -0,0 +1,36 @@ +############################################################################ +# arch/xtensa/src/lx6/Toolchain.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +CROSSDEV = xtensa-esp32-elf- diff --git a/configs/Board.mk b/configs/Board.mk index a04da664270..11f0ed4dc23 100644 --- a/configs/Board.mk +++ b/configs/Board.mk @@ -124,12 +124,18 @@ endif depend: .depend +ifneq ($(BOARD_CONTEXT),y) +context: +endif + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) + $(EXTRA_CLEAN) distclean: clean $(call DELFILE, Make.dep) $(call DELFILE, .depend) + $(EXTRA_DISTCLEAN) -include Make.dep diff --git a/configs/Kconfig b/configs/Kconfig index 65f6a690d98..0c5135513a4 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -170,14 +170,16 @@ config ARCH_BOARD_EKKLM3S9B96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. -config ARCH_BOARD_EZ80F910200KITG - bool "ZiLOG ez80f910200kitg development kit" - depends on ARCH_CHIP_EZ80F91 - select ARCH_HAVE_LEDS +config ARCH_BOARD_ESP32CORE + bool "Expressif ESP32 Core board V2" + depends on ARCH_CHIP_ESP32 ---help--- - ez80Acclaim! Microcontroller. This port use the ZiLOG ez80f910200kitg - development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line - tools. The development environment is Cygwin under WinXP. + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory + and peripherals are located on the data bus and/or the instruction + bus of these CPUs. With some minor exceptions, the address mapping + of two CPUs is symmetric, meaning they use the same addresses to + access the same memory. config ARCH_BOARD_EZ80F910200ZCO bool "ZiLOG ez80f910200zco development kit" @@ -1392,6 +1394,7 @@ config ARCH_BOARD default "efm32-g8xx-stk" if ARCH_BOARD_EFM32G8XXSTK default "efm32gg-stk3700" if ARCH_BOARD_EFM32GG_STK3700 default "ekk-lm3s9b96" if ARCH_BOARD_EKKLM3S9B96 + default "esp32-core" if ARCH_BOARD_ESP32CORE default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 @@ -1591,6 +1594,9 @@ endif if ARCH_BOARD_EKKLM3S9B96 source "configs/ekk-lm3s9b96/Kconfig" endif +if ARCH_BOARD_ESP32CORE +source "configs/esp32-core/Kconfig" +endif if ARCH_BOARD_EZ80F910200KITG source "configs/ez80f910200kitg/Kconfig" endif diff --git a/configs/Makefile b/configs/Makefile index 9a04b131bb6..68a5fad87fe 100644 --- a/configs/Makefile +++ b/configs/Makefile @@ -57,6 +57,11 @@ endif DUMMY_KCONFIG = $(TOPDIR)$(DELIM)configs$(DELIM)dummy$(DELIM)Kconfig +# The board configuration should be installed in the arch/ directory + +BOARD_DIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board +BOARD_INSTALLED = $(if $(wildcard $(BOARD_DIR)$(DELIM)Makefile),y,) + # Basic CONFIG_ASRCS = @@ -106,6 +111,9 @@ $(DUMMY_KCONFIG): $(BOARD_KCONFIG) dirlinks: $(DUMMY_KCONFIG) context: $(DUMMY_KCONFIG) +ifeq ($(BOARD_INSTALLED),y) + $(Q) $(MAKE) -C $(BOARD_DIR) TOPDIR="$(TOPDIR)" context +endif clean_context: $(call DELFILE, $(DUMMY_KCONFIG)) diff --git a/configs/README.txt b/configs/README.txt index c9b84676b2a..c95087f42a7 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -246,6 +246,14 @@ configs/ekk-lm3s9b96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. +configs/esp-core + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + nd peripherals are located on the data bus and/or the instruction bus of + bus of these CPUs. With some minor exceptions, the address mapping of two + CPUs is symmetric, meaning they use the same addresses to access the same + memory. + configs/ez80f0910200kitg ez80Acclaim! Microcontroller. This port use the Zilog ez80f0910200kitg development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line diff --git a/configs/arduino-mega2560/src/Makefile b/configs/arduino-mega2560/src/Makefile index 1f7743da6f5..7e5911999ee 100644 --- a/configs/arduino-mega2560/src/Makefile +++ b/configs/arduino-mega2560/src/Makefile @@ -87,6 +87,8 @@ libboard$(LIBEXT): $(OBJS) depend: .depend +context: + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig new file mode 100644 index 00000000000..719b83d1a5c --- /dev/null +++ b/configs/esp32-core/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32CORE + +endif # ARCH_BOARD_ESP32CORE diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt new file mode 100644 index 00000000000..50fd2d273d3 --- /dev/null +++ b/configs/esp32-core/README.txt @@ -0,0 +1,156 @@ +README for the Expressif ESP32 Core board (V2) +============================================== + + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + peripherals are located on the data bus and/or the instruction bus of + these CPUs. With some minor exceptions, the address mapping of two CPUs + is symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded memory via + DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + +Contents +======== + + o STATUS + o ESP32 Features + o ESP32 Toolchain + o Serial Console + o Buttons and LEDs + o Configurations + +STATUS +====== + + The basic port is underway. No testing has yet been performed. + +ESP32 Features +============== + + * Address Space + - Symmetric address mapping + - 4 GB (32-bit) address space for both data bus and instruction bus + - 1296 KB embedded memory address space + - 19704 KB external memory address space + - 512 KB peripheral address space + - Some embedded and external memory regions can be accessed by either + data bus or instruction bus + - 328 KB DMA address space + * Embedded Memory + - 448 KB Internal ROM + - 520 KB Internal SRAM + - 8 KB RTC FAST Memory + - 8 KB RTC SLOW Memory + * External Memory + Off-chip SPI memory can be mapped into the available address space as + external memory. Parts of the embedded memory can be used as transparent + cache for this external memory. + - Supports up to 16 MB off-Chip SPI Flash. + - Supports up to 8 MB off-Chip SPI SRAM. + * Peripherals + - 41 peripherals + * DMA + - 13 modules are capable of DMA operation + +ESP32 Toolchain +=============== + + You must use the custom Xtensa toolchain in order to build the ESP32 Core + BSP. The steps to build toolchain with crosstool-NG on Linux are as + follows: + + git clone -b xtensa-1.22.x https://github.com/espressif/crosstool-NG.git + cd crosstool-NG + ./bootstrap && ./configure --prefix=$PWD && make install + ./ct-ng xtensa-esp32-elf + ./ct-ng build + chmod -R u+w builds/xtensa-esp32-elf + + These steps are given in setup guide in ESP-IDF repository: + https://github.com/espressif/esp-idf/blob/master/docs/linux-setup.rst#alternative-step-1-compile-the-toolchain-from-source-using-crosstool-ng + + NOTE: The xtensa-esp32-elf configuration is only available in the + xtensa-1.22.x branch. + +Serial Console +============== + + To be provided + +Buttons and LEDs +================ + + Buttons + ------- + There are two buttons labeled Boot and EN. The EN button is not available + to software. It pulls the chip enable line that doubles as a reset line. + + The BOOT button is connected to IO0. On reset it is used as a strapping + pin to determine whether the chip boots normally or into the serial + bootloader. After reset, however, the BOOT button can be used for software + input. + + LEDs + ---- + There are several on-board LEDs for that indicate the presence of power + and USB activity. None of these are available for use by sofware. + +Configurations +============== + + Common Configuration Information + -------------------------------- + Each ESP32 core configuration is maintained in sub-directories and + can be selected as follow: + + cd tools + ./configure.sh esp32-core/ + cd - + make oldconfig + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and + perform edits as necessary so that TOOLCHAIN_BIN is the correct path to + the directory than holds your toolchain binaries. + + If this is a Windows native build, then configure.bat should be used + instead of configure.sh: + + configure.bat esp32-core\ + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, + nuttx. + + make oldconfig + make + + The that is provided above as an argument to the + tools/configure.sh must be is one of the directories listed below. + +NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on [To be provided]. + + Configuration sub-directories + ----------------------------- + + nsh: + + Configures the NuttShell (nsh) located at apps/examples/nsh. + + NOTES: diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h new file mode 100644 index 00000000000..94dcebef320 --- /dev/null +++ b/configs/esp32-core/include/board.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * configs/esp32-core/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H +#define __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking ****************************************************************/ + +#define BOARD_CLOCK_FREQUENCY 80000000 + +#endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs new file mode 100644 index 00000000000..f8901d0f8bc --- /dev/null +++ b/configs/esp32-core/nsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/esp32-core/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs + +LDSCRIPT1 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_out.ld +LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_common.ld +LDSCRIPT3 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_rom.ld +LDSCRIPT4 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_peripherals.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -MMD -MP +ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +LDFLAGS += -nostartfiles -nodefaultlibs +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig new file mode 100644 index 00000000000..f78400225ad --- /dev/null +++ b/configs/esp32-core/nsh/defconfig @@ -0,0 +1,758 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +# CONFIG_DEBUG_NOOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +CONFIG_ARCH_XTENSA=y +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_FAMILY_LX6=y +CONFIG_XTENSA_NCOPROCESSORS=1 +# CONFIG_XTENSA_USE_SWPRI is not set +CONFIG_XTENSA_CALL0_ABI=y +# CONFIG_XTENSA_USE_OVLY is not set +CONFIG_ESP32_BT_RESERVE_DRAM=0 +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_MULTICPU=y +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_ESP32CORE=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="esp32-core" + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +# CONFIG_SERIAL_CONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +# CONFIG_MCU_SERIAL is not set +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/esp32-core/nsh/setenv.sh b/configs/esp32-core/nsh/setenv.sh new file mode 100644 index 00000000000..3c57c18b554 --- /dev/null +++ b/configs/esp32-core/nsh/setenv.sh @@ -0,0 +1,57 @@ +#!/bin/bash +# configs/esp32-core/nsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the path to the location where I installed the Expressif crosstools-NG +# toolchaing +export TOOLCHAIN_BIN="/home/patacongo/projects/nuttx/crosstool-NG/builds/xtensa-esp32-elf/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/esp32-core/scripts/.gitignore b/configs/esp32-core/scripts/.gitignore new file mode 100644 index 00000000000..155d3f50341 --- /dev/null +++ b/configs/esp32-core/scripts/.gitignore @@ -0,0 +1,2 @@ +/esp32_out.ld + diff --git a/configs/esp32-core/scripts/esp32.template b/configs/esp32-core/scripts/esp32.template new file mode 100644 index 00000000000..9fbe0f1ccc2 --- /dev/null +++ b/configs/esp32-core/scripts/esp32.template @@ -0,0 +1,62 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32.template + * ESP32 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * esp32.common.ld contains output sections to link compiler output + * into these memory blocks. + * + * NOTE: That this is not the actual linker script but rather a "template" + * for the elf32_out.ld script. This template script is passed through + * the C preprocessor to include selected configuration options. + * + ****************************************************************************/ + +#include + +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this + * uses subtracted from the length of the various regions. The 'data access + * port' dram/drom regions map to the same iram/irom regions but are + * connected to the data port of the CPU and eg allow bytewise access. + */ + + /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 + + /* Even though the segment name is iram, it is actually mapped to flash */ + + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 + + /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. + * Enabling Bluetooth & Trace Memory features in menuconfig will decrease + * the amount of RAM available. + */ + + dram0_0_seg (RW) : org = 0x3ffb0000 + CONFIG_ESP32_BT_RESERVE_DRAM, + len = 0x50000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM - CONFIG_ESP32_BT_RESERVE_DRAM + + /* Flash mapped constant data */ + + drom0_0_seg (R) : org = 0x3f400010, len = 0x800000 + + /* RTC fast memory (executable). Persists over deep sleep. */ + + rtc_iram_seg(RWX) : org = 0x400c0000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + * Start of RTC slow memory is reserved for ULP co-processor code + data, + * if enabled. + */ + + rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM, + len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM +} + +/* Heap ends at top of dram0_0_seg */ + +_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld new file mode 100644 index 00000000000..da7b74d5103 --- /dev/null +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -0,0 +1,179 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32_common.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP(*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP(*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP(*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as runnning out of IRAM */ + + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *libfreertos.a:(.literal .text .literal.* .text.*) + *libphy.a:(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libpp.a:(.literal .text .literal.* .text.*) + *libhal.a:(.literal .text .literal.* .text.*) + _iram_text_end = ABSOLUTE(.); + } > iram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP(*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _ebss = ABSOLUTE(.); + } >dram0_0_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + KEEP(*(.data)) + KEEP(*(.data.*)) + KEEP(*(.gnu.linkonce.d.*)) + KEEP(*(.data1)) + KEEP(*(.sdata)) + KEEP(*(.sdata.*)) + KEEP(*(.gnu.linkonce.s.*)) + KEEP(*(.sdata2)) + KEEP(*(.sdata2.*)) + KEEP(*(.gnu.linkonce.s2.*)) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + _data_end = ABSOLUTE(.); + . = ALIGN(4); + _heap_start = ABSOLUTE(.); + } >dram0_0_seg + + .flash.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg + + .flash.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram0_2_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } > rtc_slow_seg +} diff --git a/configs/esp32-core/scripts/esp32_peripherals.ld b/configs/esp32-core/scripts/esp32_peripherals.ld new file mode 100644 index 00000000000..cabfe4aaa43 --- /dev/null +++ b/configs/esp32-core/scripts/esp32_peripherals.ld @@ -0,0 +1,24 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32_peripherals.ld + ****************************************************************************/ + +PROVIDE ( UART0 = 0x3ff40000 ); +PROVIDE ( SPI1 = 0x3ff42000 ); +PROVIDE ( SPI0 = 0x3ff43000 ); +PROVIDE ( GPIO = 0x3ff44000 ); +PROVIDE ( SIGMADELTA = 0x3ff44f00 ); +PROVIDE ( UHCI1 = 0x3ff4C000 ); +PROVIDE ( I2S0 = 0x3ff4F000 ); +PROVIDE ( UART1 = 0x3ff50000 ); +PROVIDE ( I2C0 = 0x3ff53000 ); +PROVIDE ( UHCI0 = 0x3ff54000 ); +PROVIDE ( RMT = 0x3ff56000 ); +PROVIDE ( PCNT = 0x3ff57000 ); +PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( TIMERG0 = 0x3ff5F000 ); +PROVIDE ( TIMERG1 = 0x3ff60000 ); +PROVIDE ( SPI2 = 0x3ff64000 ); +PROVIDE ( SPI3 = 0x3ff65000 ); +PROVIDE ( I2C1 = 0x3ff67000 ); +PROVIDE ( I2S1 = 0x3ff6D000 ); +PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/configs/esp32-core/scripts/esp32_rom.ld b/configs/esp32-core/scripts/esp32_rom.ld new file mode 100644 index 00000000000..b7181d88964 --- /dev/null +++ b/configs/esp32-core/scripts/esp32_rom.ld @@ -0,0 +1,1846 @@ +/* +ESP32 ROM address table +Generated for ROM with MD5sum: +ab8282ae908fe9e7a63fb2a4ac2df013 ../../rom_image/prorom.elf +*/ + +PROVIDE ( abort = 0x4000bba4 ); +PROVIDE ( abs = 0x40056340 ); +PROVIDE ( __absvdi2 = 0x4006387c ); +PROVIDE ( __absvsi2 = 0x40063868 ); +PROVIDE ( Add2SelfBigHex256 = 0x40015b7c ); +PROVIDE ( AddBigHex256 = 0x40015b28 ); +PROVIDE ( AddBigHexModP256 = 0x40015c98 ); +PROVIDE ( __adddf3 = 0x40002590 ); +PROVIDE ( AddP256 = 0x40015c74 ); +PROVIDE ( AddPdiv2_256 = 0x40015ce0 ); +PROVIDE ( __addsf3 = 0x400020e8 ); +PROVIDE ( __addvdi3 = 0x40002cbc ); +PROVIDE ( __addvsi3 = 0x40002c98 ); +PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c ); +PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 ); +PROVIDE ( aes_unwrap = 0x4005ccf0 ); +PROVIDE ( app_gpio_arg = 0x3ffe003c ); +PROVIDE ( app_gpio_handler = 0x3ffe0040 ); +PROVIDE ( __ascii_wctomb = 0x40058ef0 ); +PROVIDE ( asctime = 0x40059588 ); +PROVIDE ( asctime_r = 0x40000ec8 ); +PROVIDE ( __ashldi3 = 0x4000c818 ); +PROVIDE ( __ashrdi3 = 0x4000c830 ); +PROVIDE ( asiprintf = 0x40056d9c ); +PROVIDE ( _asiprintf_r = 0x40056d4c ); +PROVIDE ( asniprintf = 0x40056cd8 ); +PROVIDE ( _asniprintf_r = 0x40056c64 ); +PROVIDE ( asnprintf = 0x40056cd8 ); +PROVIDE ( _asnprintf_r = 0x40056c64 ); +PROVIDE ( asprintf = 0x40056d9c ); +PROVIDE ( _asprintf_r = 0x40056d4c ); +PROVIDE ( atoi = 0x400566c4 ); +PROVIDE ( _atoi_r = 0x400566d4 ); +PROVIDE ( atol = 0x400566ec ); +PROVIDE ( _atol_r = 0x400566fc ); +PROVIDE ( base64_decode = 0x4005ced8 ); +PROVIDE ( base64_encode = 0x4005cdbc ); +PROVIDE ( BasePoint_x_256 = 0x3ff97488 ); +PROVIDE ( BasePoint_y_256 = 0x3ff97468 ); +PROVIDE ( bigHexInversion256 = 0x400168f0 ); +PROVIDE ( bigHexP256 = 0x3ff973bc ); +PROVIDE ( __bswapdi2 = 0x400649c4 ); +PROVIDE ( __bswapsi2 = 0x4006499c ); +PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c ); +PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 ); +PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 ); +PROVIDE ( btdm_r_data_init = 0x4001002c ); +PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 ); +PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 ); +PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc ); +PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c ); +PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 ); +PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 ); +PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 ); +PROVIDE ( bzero = 0x4000c1f4 ); +PROVIDE ( cache_flash_mmu_set = 0x400095e0 ); +PROVIDE ( Cache_Flush = 0x40009a14 ); +PROVIDE ( Cache_Read_Disable = 0x40009ab8 ); +PROVIDE ( Cache_Read_Enable = 0x40009a84 ); +PROVIDE ( Cache_Read_Init = 0x40009950 ); +PROVIDE ( cache_sram_mmu_set = 0x400097f4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); +PROVIDE ( calloc = 0x4000bee4 ); +PROVIDE ( _calloc_r = 0x4000bbf8 ); +PROVIDE ( check_pos = 0x400068b8 ); +PROVIDE ( _cleanup = 0x40001df8 ); +PROVIDE ( _cleanup_r = 0x40001d48 ); +PROVIDE ( __clear_cache = 0x40063860 ); +PROVIDE ( close = 0x40001778 ); +PROVIDE ( _close_r = 0x4000bd3c ); +PROVIDE ( __clrsbdi2 = 0x40064a38 ); +PROVIDE ( __clrsbsi2 = 0x40064a20 ); +PROVIDE ( __clzdi2 = 0x4000ca50 ); +PROVIDE ( __clzsi2 = 0x4000c7e8 ); +PROVIDE ( __cmpdi2 = 0x40063820 ); +PROVIDE ( co_default_bdaddr = 0x3ffae704 ); +PROVIDE ( co_null_bdaddr = 0x3ffb80e0 ); +PROVIDE ( co_sca2ppm = 0x3ff971e8 ); +PROVIDE ( crc16_be = 0x4005d09c ); +PROVIDE ( crc16_le = 0x4005d05c ); +PROVIDE ( crc32_be = 0x4005d024 ); +PROVIDE ( crc32_le = 0x4005cfec ); +PROVIDE ( crc8_be = 0x4005d114 ); +PROVIDE ( crc8_le = 0x4005d0e0 ); +PROVIDE ( creat = 0x40000e8c ); +PROVIDE ( ctime = 0x400595b0 ); +PROVIDE ( ctime_r = 0x400595c4 ); +PROVIDE ( _ctype_ = 0x3ff96354 ); +PROVIDE ( __ctype_ptr__ = 0x3ff96350 ); +PROVIDE ( __ctzdi2 = 0x4000ca64 ); +PROVIDE ( __ctzsi2 = 0x4000c7f0 ); +PROVIDE ( _data_end = 0x4000d5c8 ); +PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 ); +PROVIDE ( _data_start = 0x4000d4f8 ); +PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 ); +PROVIDE ( _data_start_btdm = 0x3ffae6e0); +PROVIDE ( _data_end_btdm = 0x3ffaff10); +PROVIDE ( _sbss_btdm = 0x3ffb8000); +PROVIDE ( _ebss_btdm = 0x3ffbff70); +PROVIDE ( _daylight = 0x3ffae0a4 ); +PROVIDE ( dbg_default_handler = 0x3ff97218 ); +PROVIDE ( dbg_state = 0x3ffb8d5d ); +PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 ); +PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 ); +PROVIDE ( DebugE256SecretKey = 0x3ff973e8 ); +PROVIDE ( _DebugExceptionVector = 0x40000280 ); +PROVIDE ( debug_timer = 0x3ffe042c ); +PROVIDE ( debug_timerfn = 0x3ffe0430 ); +PROVIDE ( dh_group14_generator = 0x3ff9ac60 ); +PROVIDE ( dh_group14_prime = 0x3ff9ab60 ); +PROVIDE ( dh_group15_generator = 0x3ff9ab5f ); +PROVIDE ( dh_group15_prime = 0x3ff9a9df ); +PROVIDE ( dh_group16_generator = 0x3ff9a9de ); +PROVIDE ( dh_group16_prime = 0x3ff9a7de ); +PROVIDE ( dh_group17_generator = 0x3ff9a7dd ); +PROVIDE ( dh_group17_prime = 0x3ff9a4dd ); +PROVIDE ( dh_group18_generator = 0x3ff9a4dc ); +PROVIDE ( dh_group18_prime = 0x3ff9a0dc ); +PROVIDE ( dh_group1_generator = 0x3ff9ae03 ); +PROVIDE ( dh_group1_prime = 0x3ff9ada3 ); +PROVIDE ( dh_group2_generator = 0x3ff9ada2 ); +PROVIDE ( dh_group2_prime = 0x3ff9ad22 ); +PROVIDE ( dh_group5_generator = 0x3ff9ad21 ); +PROVIDE ( dh_group5_prime = 0x3ff9ac61 ); +PROVIDE ( div = 0x40056348 ); +PROVIDE ( __divdc3 = 0x40064460 ); +PROVIDE ( __divdf3 = 0x40002954 ); +PROVIDE ( __divdi3 = 0x4000ca84 ); +PROVIDE ( __divsc3 = 0x40064200 ); +PROVIDE ( __divsf3 = 0x4000234c ); +PROVIDE ( __divsi3 = 0x4000c7b8 ); +PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); +PROVIDE ( dummy_len_plus = 0x3ffae290 ); +PROVIDE ( __dummy_lock = 0x4000c728 ); +PROVIDE ( __dummy_lock_try = 0x4000c730 ); +PROVIDE ( ecc_env = 0x3ffb8d60 ); +PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 ); +PROVIDE ( em_buf_env = 0x3ffb8d74 ); +PROVIDE ( environ = 0x3ffae0b4 ); +PROVIDE ( __env_lock = 0x40001fd4 ); +PROVIDE ( __env_unlock = 0x40001fe0 ); +PROVIDE ( __eqdf2 = 0x400636a8 ); +PROVIDE ( __eqsf2 = 0x40063374 ); +PROVIDE ( esp_crc8 = 0x4005d144 ); +PROVIDE ( _etext = 0x4000d66c ); +PROVIDE ( ets_aes_crypt = 0x4005c9b8 ); +PROVIDE ( ets_aes_disable = 0x4005c8f8 ); +PROVIDE ( ets_aes_enable = 0x4005c8cc ); +PROVIDE ( ets_aes_set_endian = 0x4005c928 ); +PROVIDE ( ets_aes_setkey_dec = 0x4005c994 ); +PROVIDE ( ets_aes_setkey_enc = 0x4005c97c ); +PROVIDE ( ets_bigint_disable = 0x4005c4e0 ); +PROVIDE ( ets_bigint_enable = 0x4005c498 ); +PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 ); +PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 ); +PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 ); +PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c ); +PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 ); +PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc ); +PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 ); +PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 ); +PROVIDE ( ets_bigint_wait_finish = 0x4005c520 ); +PROVIDE ( ets_delay_us = 0x40008534 ); +PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 ); +PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 ); +PROVIDE ( ets_efuse_program_op = 0x40008628 ); +PROVIDE ( ets_efuse_read_op = 0x40008600 ); +PROVIDE ( ets_get_cpu_frequency = 0x4000855c ); +PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 ); +PROVIDE ( ets_get_xtal_scale = 0x4000856c ); +PROVIDE ( ets_install_putc1 = 0x40007d18 ); +PROVIDE ( ets_install_putc2 = 0x40007d38 ); +PROVIDE ( ets_install_uart_printf = 0x40007d28 ); +PROVIDE ( ets_intr_count = 0x3ffe03fc ); +PROVIDE ( ets_intr_lock = 0x400067b0 ); +PROVIDE ( ets_intr_unlock = 0x400067c4 ); +PROVIDE ( ets_isr_attach = 0x400067ec ); +PROVIDE ( ets_isr_mask = 0x400067fc ); +PROVIDE ( ets_isr_unmask = 0x40006808 ); +PROVIDE ( ets_post = 0x4000673c ); +PROVIDE ( ets_printf = 0x40007d54 ); +PROVIDE ( ets_readySet_ = 0x3ffe01f0 ); +PROVIDE ( ets_run = 0x400066bc ); +PROVIDE ( ets_secure_boot_check = 0x4005cb40 ); +PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 ); +PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc ); +PROVIDE ( ets_secure_boot_finish = 0x4005ca84 ); +PROVIDE ( ets_secure_boot_hash = 0x4005cad4 ); +PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 ); +PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 ); +PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 ); +PROVIDE ( ets_secure_boot_start = 0x4005ca34 ); +PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c ); +PROVIDE ( ets_set_idle_cb = 0x40006674 ); +PROVIDE ( ets_set_startup_callback = 0x4000688c ); +PROVIDE ( ets_set_user_start = 0x4000687c ); +PROVIDE ( ets_sha_disable = 0x4005c0a8 ); +PROVIDE ( ets_sha_enable = 0x4005c07c ); +PROVIDE ( ets_sha_finish = 0x4005c104 ); +PROVIDE ( ets_sha_init = 0x4005c0d4 ); +PROVIDE ( ets_sha_update = 0x4005c2a0 ); +PROVIDE ( ets_startup_callback = 0x3ffe0404 ); +PROVIDE ( ets_task = 0x40006688 ); +PROVIDE ( ets_timer_arm = 0x40008368 ); +PROVIDE ( ets_timer_arm_us = 0x400083ac ); +PROVIDE ( ets_timer_disarm = 0x400083ec ); +PROVIDE ( ets_timer_done = 0x40008428 ); +PROVIDE ( ets_timer_handler_isr = 0x40008454 ); +PROVIDE ( ets_timer_init = 0x400084e8 ); +PROVIDE ( ets_timer_setfn = 0x40008350 ); +PROVIDE ( ets_unpack_flash_code = 0x40007018 ); +PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c ); +PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); +PROVIDE ( ets_waiti0 = 0x400067d8 ); +PROVIDE ( exc_cause_table = 0x3ff991d0 ); +PROVIDE ( _exit_r = 0x4000bd28 ); +PROVIDE ( __extendsfdf2 = 0x40002c34 ); +PROVIDE ( fclose = 0x400020ac ); +PROVIDE ( _fclose_r = 0x40001fec ); +PROVIDE ( fflush = 0x40059394 ); +PROVIDE ( _fflush_r = 0x40059320 ); +PROVIDE ( __ffsdi2 = 0x4000ca2c ); +PROVIDE ( __ffssi2 = 0x4000c804 ); +PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 ); +PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 ); +PROVIDE ( _findenv_r = 0x40001f44 ); +PROVIDE ( fiprintf = 0x40056efc ); +PROVIDE ( _fiprintf_r = 0x40056ed8 ); +PROVIDE ( fiscanf = 0x40058884 ); +PROVIDE ( _fiscanf_r = 0x400588b4 ); +PROVIDE ( __fixdfdi = 0x40002ac4 ); +PROVIDE ( __fixdfsi = 0x40002a78 ); +PROVIDE ( __fixsfdi = 0x4000244c ); +PROVIDE ( __fixsfsi = 0x4000240c ); +PROVIDE ( __fixunsdfsi = 0x40002b30 ); +PROVIDE ( __fixunssfdi = 0x40002504 ); +PROVIDE ( __fixunssfsi = 0x400024ac ); +PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 ); +PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c ); +PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 ); +PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 ); +PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec ); +PROVIDE ( __floatdidf = 0x4000c988 ); +PROVIDE ( __floatdisf = 0x4000c8c0 ); +PROVIDE ( __floatsidf = 0x4000c944 ); +PROVIDE ( __floatsisf = 0x4000c870 ); +PROVIDE ( __floatundidf = 0x4000c978 ); +PROVIDE ( __floatundisf = 0x4000c8b0 ); +PROVIDE ( __floatunsidf = 0x4000c938 ); +PROVIDE ( __floatunsisf = 0x4000c864 ); +PROVIDE ( __fp_lock_all = 0x40001f1c ); +PROVIDE ( fprintf = 0x40056efc ); +PROVIDE ( _fprintf_r = 0x40056ed8 ); +PROVIDE ( __fp_unlock_all = 0x40001f30 ); +PROVIDE ( fputwc = 0x40058ea8 ); +PROVIDE ( __fputwc = 0x40058da0 ); +PROVIDE ( _fputwc_r = 0x40058e4c ); +PROVIDE ( free = 0x4000beb8 ); +PROVIDE ( _free_r = 0x4000bbcc ); +PROVIDE ( fscanf = 0x40058884 ); +PROVIDE ( _fscanf_r = 0x400588b4 ); +PROVIDE ( _fstat_r = 0x4000bccc ); +PROVIDE ( _fwalk = 0x4000c738 ); +PROVIDE ( _fwalk_reent = 0x4000c770 ); +PROVIDE ( __gcc_bcmp = 0x40064a70 ); +PROVIDE ( __gedf2 = 0x40063768 ); +PROVIDE ( _GeneralException = 0x40000e14 ); +PROVIDE ( __gesf2 = 0x4006340c ); +PROVIDE ( __get_current_time_locale = 0x40001834 ); +PROVIDE ( _getenv_r = 0x40001fbc ); +PROVIDE ( _getpid_r = 0x4000bcfc ); +PROVIDE ( __getreent = 0x4000be8c ); +PROVIDE ( _gettimeofday_r = 0x4000bc58 ); +PROVIDE ( __gettzinfo = 0x40001fcc ); +PROVIDE ( GetUartDevice = 0x40009598 ); +PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 ); +PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 ); +PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c ); +PROVIDE ( _global_impure_ptr = 0x3ffae0b0 ); +PROVIDE ( gmtime = 0x40059848 ); +PROVIDE ( gmtime_r = 0x40059868 ); +PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 ); +PROVIDE ( gpio_init = 0x40009c20 ); +PROVIDE ( gpio_input_get = 0x40009b88 ); +PROVIDE ( gpio_input_get_high = 0x40009b9c ); +PROVIDE ( gpio_intr_ack = 0x40009dd4 ); +PROVIDE ( gpio_intr_ack_high = 0x40009e1c ); +PROVIDE ( gpio_intr_handler_register = 0x40009e6c ); +PROVIDE ( gpio_intr_pending = 0x40009cec ); +PROVIDE ( gpio_intr_pending_high = 0x40009cf8 ); +PROVIDE ( gpio_matrix_in = 0x40009edc ); +PROVIDE ( gpio_matrix_out = 0x40009f0c ); +PROVIDE ( gpio_output_set = 0x40009b24 ); +PROVIDE ( gpio_output_set_high = 0x40009b5c ); +PROVIDE ( gpio_pad_hold = 0x4000a734 ); +PROVIDE ( gpio_pad_pulldown = 0x4000a348 ); +PROVIDE ( gpio_pad_pullup = 0x4000a22c ); +PROVIDE ( gpio_pad_select_gpio = 0x40009fdc ); +PROVIDE ( gpio_pad_set_drv = 0x4000a11c ); +PROVIDE ( gpio_pad_unhold = 0x4000a484 ); +PROVIDE ( gpio_pending_mask = 0x3ffe0038 ); +PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 ); +PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 ); +PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 ); +PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c ); +PROVIDE ( gpio_register_get = 0x40009cbc ); +PROVIDE ( gpio_register_set = 0x40009bbc ); +PROVIDE ( __gtdf2 = 0x400636dc ); +PROVIDE ( __gtsf2 = 0x400633a0 ); +PROVIDE ( gTxMsg = 0x3ffe0050 ); +PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 ); +PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 ); +PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c ); +PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 ); +PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 ); +PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c ); +PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 ); +PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 ); +PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 ); +PROVIDE ( hci_command_handler = 0x4004c928 ); +PROVIDE ( hci_env = 0x3ffb9350 ); +PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c ); +PROVIDE ( hci_evt_desc_tab = 0x3ff9751c ); +PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 ); +PROVIDE ( hci_fc_env = 0x3ffb9340 ); +PROVIDE ( hmac_md5 = 0x4005d264 ); +PROVIDE ( hmac_md5_vector = 0x4005d17c ); +PROVIDE ( hmac_sha1 = 0x40060acc ); +PROVIDE ( hmac_sha1_vector = 0x400609e4 ); +PROVIDE ( hmac_sha256 = 0x40060d58 ); +PROVIDE ( hmac_sha256_vector = 0x40060c84 ); +PROVIDE ( intr_matrix_set = 0x4000681c ); +PROVIDE ( iprintf = 0x40056978 ); +PROVIDE ( _iprintf_r = 0x40056944 ); +PROVIDE ( isalnum = 0x40000f04 ); +PROVIDE ( isalpha = 0x40000f18 ); +PROVIDE ( isascii = 0x4000c20c ); +PROVIDE ( _isatty_r = 0x40000ea0 ); +PROVIDE ( isblank = 0x40000f2c ); +PROVIDE ( iscanf = 0x40058760 ); +PROVIDE ( _iscanf_r = 0x4005879c ); +PROVIDE ( iscntrl = 0x40000f50 ); +PROVIDE ( isdigit = 0x40000f64 ); +PROVIDE ( isgraph = 0x40000f94 ); +PROVIDE ( islower = 0x40000f78 ); +PROVIDE ( isprint = 0x40000fa8 ); +PROVIDE ( ispunct = 0x40000fc0 ); +PROVIDE ( isspace = 0x40000fd4 ); +PROVIDE ( isupper = 0x40000fe8 ); +PROVIDE ( itoa = 0x400566b4 ); +PROVIDE ( __itoa = 0x40056678 ); +PROVIDE ( jd_decomp = 0x400613e8 ); +PROVIDE ( jd_prepare = 0x40060fa8 ); +PROVIDE ( ke_env = 0x3ffb93cc ); +PROVIDE ( _KernelExceptionVector = 0x40000300 ); +PROVIDE ( _kill_r = 0x4000bd10 ); +PROVIDE ( labs = 0x40056370 ); +PROVIDE ( lb_default_handler = 0x3ff982b8 ); +PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); +PROVIDE ( lb_env = 0x3ffb9424 ); +PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c ); +PROVIDE ( lb_state = 0x3ffb94e8 ); +PROVIDE ( lc_default_handler = 0x3ff98648 ); +PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 ); +PROVIDE ( lc_env = 0x3ffb94ec ); +PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 ); +PROVIDE ( lc_state = 0x3ffb9508 ); +PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a ); +PROVIDE ( ld_acl_br_types = 0x3ff98a36 ); +PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 ); +PROVIDE ( ld_acl_edr_types = 0x3ff98a22 ); +PROVIDE ( ld_env = 0x3ffb9510 ); +PROVIDE ( ldiv = 0x40056378 ); +PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c ); +PROVIDE ( ld_sched_params = 0x3ffb96c0 ); +PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); +PROVIDE ( __ledf2 = 0x40063704 ); +PROVIDE ( __lesf2 = 0x400633c0 ); +PROVIDE ( _xtensa_level2_from = 0x40000954 ); +PROVIDE ( _xtensa_level2_vector = 0x40000180 ); +PROVIDE ( _xtensa_level3_from = 0x40000a28 ); +PROVIDE ( _xtensa_level3_vector = 0x400001c0 ); +PROVIDE ( _xtensa_level4_from = 0x40000af8 ); +PROVIDE ( _xtensa_level4_vector = 0x40000200 ); +PROVIDE ( _xtensa_level5_from = 0x40000c68 ); +PROVIDE ( _xtensa_level5_vector = 0x40000240 ); +PROVIDE ( _LevelOneInterrupt = 0x40000835 ); +PROVIDE ( _link_r = 0x4000bc9c ); +PROVIDE ( llc_default_handler = 0x3ff98b3c ); +PROVIDE ( llc_default_state_tab_p_get = 0x40046058 ); +PROVIDE ( llc_env = 0x3ffb96d0 ); +PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 ); +PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 ); +PROVIDE ( llc_hci_command_handler = 0x40042360 ); +PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 ); +PROVIDE ( llc_state = 0x3ffb96f8 ); +PROVIDE ( lldesc_build_chain = 0x4000a850 ); +PROVIDE ( lldesc_num2link = 0x4000a948 ); +PROVIDE ( lldesc_set_owner = 0x4000a974 ); +PROVIDE ( lld_evt_env = 0x3ffb9704 ); +PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 ); +PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 ); +PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a ); +PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 ); +PROVIDE ( llm_default_handler = 0x3ff98d80 ); +PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 ); +PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 ); +PROVIDE ( llm_le_env = 0x3ffb976c ); +PROVIDE ( llm_local_cmds = 0x3ff98d38 ); +PROVIDE ( llm_local_data_len_values = 0x3ff98d1c ); +PROVIDE ( llm_local_le_feats = 0x3ff98d30 ); +PROVIDE ( llm_local_le_states = 0x3ff98d28 ); +PROVIDE ( llm_state = 0x3ffb985c ); +PROVIDE ( lm_default_handler = 0x3ff990e0 ); +PROVIDE ( lm_default_state_tab_p_get = 0x40054268 ); +PROVIDE ( lm_env = 0x3ffb9860 ); +PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c ); +PROVIDE ( lm_local_supp_feats = 0x3ff990ee ); +PROVIDE ( lm_n_page_tab = 0x3ff990e8 ); +PROVIDE ( lmp_desc_tab = 0x3ff96e6c ); +PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c ); +PROVIDE ( lm_state = 0x3ffb9a1c ); +PROVIDE ( __locale_charset = 0x40059540 ); +PROVIDE ( __locale_cjk_lang = 0x40059558 ); +PROVIDE ( localeconv = 0x4005957c ); +PROVIDE ( _localeconv_r = 0x40059560 ); +PROVIDE ( __locale_mb_cur_max = 0x40059548 ); +PROVIDE ( __locale_msgcharset = 0x40059550 ); +PROVIDE ( localtime = 0x400595dc ); +PROVIDE ( localtime_r = 0x400595fc ); +PROVIDE ( _lock_acquire = 0x4000be14 ); +PROVIDE ( _lock_acquire_recursive = 0x4000be28 ); +PROVIDE ( _lock_close = 0x4000bdec ); +PROVIDE ( _lock_close_recursive = 0x4000be00 ); +PROVIDE ( _lock_init = 0x4000bdc4 ); +PROVIDE ( _lock_init_recursive = 0x4000bdd8 ); +PROVIDE ( _lock_release = 0x4000be64 ); +PROVIDE ( _lock_release_recursive = 0x4000be78 ); +PROVIDE ( _lock_try_acquire = 0x4000be3c ); +PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 ); +PROVIDE ( longjmp = 0x400562cc ); +PROVIDE ( _lseek_r = 0x4000bd8c ); +PROVIDE ( __lshrdi3 = 0x4000c84c ); +PROVIDE ( __ltdf2 = 0x40063790 ); +PROVIDE ( __ltsf2 = 0x4006342c ); +PROVIDE ( malloc = 0x4000bea0 ); +PROVIDE ( _malloc_r = 0x4000bbb4 ); +PROVIDE ( maxSecretKey_256 = 0x3ff97448 ); +PROVIDE ( __mb_cur_max = 0x3ff96530 ); +PROVIDE ( MD5Final = 0x4005db1c ); +PROVIDE ( MD5Init = 0x4005da7c ); +PROVIDE ( MD5Update = 0x4005da9c ); +PROVIDE ( md5_vector = 0x4005db80 ); +PROVIDE ( memccpy = 0x4000c220 ); +PROVIDE ( memchr = 0x4000c244 ); +PROVIDE ( memcmp = 0x4000c260 ); +PROVIDE ( memcpy = 0x4000c2c8 ); +PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 ); +PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc ); +PROVIDE ( memmove = 0x4000c3c0 ); +PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 ); +PROVIDE ( memrchr = 0x4000c400 ); +PROVIDE ( memset = 0x4000c44c ); +PROVIDE ( mktime = 0x4005a5e8 ); +PROVIDE ( mmu_init = 0x400095a4 ); +PROVIDE ( __moddi3 = 0x4000cd4c ); +PROVIDE ( __modsi3 = 0x4000c7c0 ); +PROVIDE ( __month_lengths = 0x3ff9609c ); +PROVIDE ( __muldc3 = 0x40063bf4 ); +PROVIDE ( __muldf3 = 0x4006358c ); +PROVIDE ( __muldi3 = 0x4000c9fc ); +PROVIDE ( __mulsc3 = 0x40063934 ); +PROVIDE ( __mulsf3 = 0x400632c8 ); +PROVIDE ( __mulsi3 = 0x4000c7b0 ); +PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 ); +PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 ); +PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc ); +PROVIDE ( multofup = 0x4000ab8c ); +PROVIDE ( __mulvdi3 = 0x40002d78 ); +PROVIDE ( __mulvsi3 = 0x40002d60 ); +PROVIDE ( mz_adler32 = 0x4005edbc ); +PROVIDE ( mz_crc32 = 0x4005ee88 ); +PROVIDE ( mz_free = 0x4005eed4 ); +PROVIDE ( __nedf2 = 0x400636a8 ); +PROVIDE ( __negdf2 = 0x400634a0 ); +PROVIDE ( __negdi2 = 0x4000ca14 ); +PROVIDE ( __negsf2 = 0x400020c0 ); +PROVIDE ( __negvdi2 = 0x40002e98 ); +PROVIDE ( __negvsi2 = 0x40002e78 ); +PROVIDE ( __nesf2 = 0x40063374 ); +PROVIDE ( _NMIExceptionVector = 0x400002c0 ); +PROVIDE ( notEqual256 = 0x40015b04 ); +PROVIDE ( __nsau_data = 0x3ff96544 ); +PROVIDE ( one_bits = 0x3ff971f8 ); +PROVIDE ( open = 0x4000178c ); +PROVIDE ( _open_r = 0x4000bd54 ); +PROVIDE ( __paritysi2 = 0x40002f3c ); +PROVIDE ( pbkdf2_sha1 = 0x40060ba4 ); +PROVIDE ( phy_get_romfuncs = 0x40004100 ); +PROVIDE ( __popcountdi2 = 0x40002ef8 ); +PROVIDE ( __popcountsi2 = 0x40002ed0 ); +PROVIDE ( __popcount_tab = 0x3ff96544 ); +PROVIDE ( __powidf2 = 0x400638d4 ); +PROVIDE ( __powisf2 = 0x4006389c ); +PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 ); +PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c ); +PROVIDE ( printf = 0x40056978 ); +PROVIDE ( _printf_common = 0x40057338 ); +PROVIDE ( _printf_float = 0x4000befc ); +PROVIDE ( _printf_i = 0x40057404 ); +PROVIDE ( _printf_r = 0x40056944 ); +PROVIDE ( qsort = 0x40056424 ); +PROVIDE ( _raise_r = 0x4000bc70 ); +PROVIDE ( rand = 0x40001058 ); +PROVIDE ( rand_r = 0x400010d4 ); +PROVIDE ( r_btdm_option_data = 0x3ffae6e0 ); +PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 ); +PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 ); +PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 ); +PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 ); +PROVIDE ( r_bt_util_buf_init = 0x400100e4 ); +PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 ); +PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec ); +PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 ); +PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 ); +PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 ); +PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c ); +PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec ); +PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 ); +PROVIDE ( rc4_skip = 0x40060928 ); +PROVIDE ( r_co_bdaddr_compare = 0x40014324 ); +PROVIDE ( r_co_bytes_to_string = 0x400142e4 ); +PROVIDE ( r_co_list_check_size_available = 0x400142c4 ); +PROVIDE ( r_co_list_extract = 0x4001404c ); +PROVIDE ( r_co_list_extract_after = 0x40014118 ); +PROVIDE ( r_co_list_find = 0x4001419c ); +PROVIDE ( r_co_list_init = 0x40013f14 ); +PROVIDE ( r_co_list_insert_after = 0x40014254 ); +PROVIDE ( r_co_list_insert_before = 0x40014200 ); +PROVIDE ( r_co_list_merge = 0x400141bc ); +PROVIDE ( r_co_list_pool_init = 0x40013f30 ); +PROVIDE ( r_co_list_pop_front = 0x40014028 ); +PROVIDE ( r_co_list_push_back = 0x40013fb8 ); +PROVIDE ( r_co_list_push_front = 0x40013ff4 ); +PROVIDE ( r_co_list_size = 0x400142ac ); +PROVIDE ( r_co_nb_good_channels = 0x40014360 ); +PROVIDE ( r_co_slot_to_duration = 0x40014348 ); +PROVIDE ( RcvMsg = 0x4000954c ); +PROVIDE ( r_dbg_init = 0x40014394 ); +PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 ); +PROVIDE ( r_dbg_swdiag_init = 0x40014470 ); +PROVIDE ( r_dbg_swdiag_read = 0x400144a4 ); +PROVIDE ( r_dbg_swdiag_write = 0x400144d0 ); +PROVIDE ( r_E1 = 0x400108e8 ); +PROVIDE ( r_E21 = 0x40010968 ); +PROVIDE ( r_E22 = 0x400109b4 ); +PROVIDE ( r_E3 = 0x40010a58 ); +PROVIDE ( r_ea_alarm_clear = 0x40015ab4 ); +PROVIDE ( r_ea_alarm_set = 0x40015a10 ); +PROVIDE ( read = 0x400017dc ); +PROVIDE ( _read_r = 0x4000bda8 ); +PROVIDE ( r_ea_elt_cancel = 0x400150d0 ); +PROVIDE ( r_ea_elt_create = 0x40015264 ); +PROVIDE ( r_ea_elt_insert = 0x400152a8 ); +PROVIDE ( r_ea_elt_remove = 0x400154f0 ); +PROVIDE ( r_ea_finetimer_isr = 0x400155d4 ); +PROVIDE ( r_ea_init = 0x40015228 ); +PROVIDE ( r_ea_interval_create = 0x4001555c ); +PROVIDE ( r_ea_interval_delete = 0x400155a8 ); +PROVIDE ( r_ea_interval_duration_req = 0x4001597c ); +PROVIDE ( r_ea_interval_insert = 0x4001557c ); +PROVIDE ( r_ea_interval_remove = 0x40015590 ); +PROVIDE ( realloc = 0x4000becc ); +PROVIDE ( _realloc_r = 0x4000bbe0 ); +PROVIDE ( r_ea_offset_req = 0x40015748 ); +PROVIDE ( r_ea_sleep_check = 0x40015928 ); +PROVIDE ( r_ea_sw_isr = 0x40015724 ); +PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 ); +PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 ); +PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 ); +PROVIDE ( r_ecc_generate_key256 = 0x40016e00 ); +PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 ); +PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 ); +PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 ); +PROVIDE ( r_ecc_init = 0x40016dbc ); +PROVIDE ( RecvBuff = 0x3ffe009c ); +PROVIDE ( recv_packet = 0x40009424 ); +PROVIDE ( r_em_buf_init = 0x4001729c ); +PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 ); +PROVIDE ( r_em_buf_rx_free = 0x400173c4 ); +PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 ); +PROVIDE ( r_em_buf_tx_free = 0x4001741c ); +PROVIDE ( _rename_r = 0x4000bc28 ); +PROVIDE ( _ResetHandler = 0x40000450 ); +PROVIDE ( _ResetVector = 0x40000400 ); +PROVIDE ( r_F1_256 = 0x400133e4 ); +PROVIDE ( r_F2_256 = 0x40013568 ); +PROVIDE ( r_F3_256 = 0x40013664 ); +PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c ); +PROVIDE ( r_G_256 = 0x40013470 ); +PROVIDE ( r_H3 = 0x40013760 ); +PROVIDE ( r_H4 = 0x40013830 ); +PROVIDE ( r_h4tl_init = 0x40017878 ); +PROVIDE ( r_h4tl_start = 0x40017924 ); +PROVIDE ( r_h4tl_stop = 0x40017934 ); +PROVIDE ( r_h4tl_write = 0x400178d0 ); +PROVIDE ( r_H5 = 0x400138dc ); +PROVIDE ( r_hashConcat = 0x40013a38 ); +PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c ); +PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 ); +PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 ); +PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac ); +PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c ); +PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 ); +PROVIDE ( r_hci_cmd_received = 0x400192f8 ); +PROVIDE ( r_hci_evt_filter_add = 0x40018a64 ); +PROVIDE ( r_hci_evt_mask_set = 0x400189e4 ); +PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 ); +PROVIDE ( r_hci_fc_acl_en = 0x400179d8 ); +PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c ); +PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 ); +PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 ); +PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c ); +PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 ); +PROVIDE ( r_hci_fc_init = 0x40017974 ); +PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 ); +PROVIDE ( r_hci_fc_sync_en = 0x40017a30 ); +PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 ); +PROVIDE ( r_hci_init = 0x40018538 ); +PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 ); +PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 ); +PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 ); +PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 ); +PROVIDE ( r_hci_reset = 0x4001856c ); +PROVIDE ( r_hci_send_2_host = 0x400185bc ); +PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 ); +PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 ); +PROVIDE ( r_hci_tl_init = 0x40019290 ); +PROVIDE ( r_hci_tl_send = 0x40019228 ); +PROVIDE ( r_hci_util_pack = 0x40019874 ); +PROVIDE ( r_hci_util_unpack = 0x40019998 ); +PROVIDE ( r_hci_voice_settings_get = 0x40018bdc ); +PROVIDE ( r_hci_voice_settings_set = 0x40018be8 ); +PROVIDE ( r_HMAC = 0x40013968 ); +PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 ); +PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 ); +PROVIDE ( r_ip_funcs = 0x3ffae710 ); +PROVIDE ( r_ip_funcs_p = 0x3ffae70c ); +PROVIDE ( r_ke_check_malloc = 0x40019de0 ); +PROVIDE ( r_ke_event_callback_set = 0x40019ba8 ); +PROVIDE ( r_ke_event_clear = 0x40019c2c ); +PROVIDE ( r_ke_event_flush = 0x40019ccc ); +PROVIDE ( r_ke_event_get = 0x40019c78 ); +PROVIDE ( r_ke_event_get_all = 0x40019cc0 ); +PROVIDE ( r_ke_event_init = 0x40019b90 ); +PROVIDE ( r_ke_event_schedule = 0x40019cdc ); +PROVIDE ( r_ke_event_set = 0x40019be0 ); +PROVIDE ( r_ke_flush = 0x4001a374 ); +PROVIDE ( r_ke_free = 0x4001a014 ); +PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 ); +PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 ); +PROVIDE ( r_ke_init = 0x4001a318 ); +PROVIDE ( r_ke_is_free = 0x4001a184 ); +PROVIDE ( r_ke_malloc = 0x40019eb4 ); +PROVIDE ( r_ke_mem_init = 0x40019d3c ); +PROVIDE ( r_ke_mem_is_empty = 0x40019d8c ); +PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 ); +PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 ); +PROVIDE ( r_ke_msg_discard = 0x4001a850 ); +PROVIDE ( r_ke_msg_forward = 0x4001a290 ); +PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac ); +PROVIDE ( r_ke_msg_free = 0x4001a2cc ); +PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 ); +PROVIDE ( r_ke_msg_save = 0x4001a858 ); +PROVIDE ( r_ke_msg_send = 0x4001a234 ); +PROVIDE ( r_ke_msg_send_basic = 0x4001a26c ); +PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec ); +PROVIDE ( r_ke_queue_extract = 0x40055fd0 ); +PROVIDE ( r_ke_queue_insert = 0x40056020 ); +PROVIDE ( r_ke_sleep_check = 0x4001a3d8 ); +PROVIDE ( r_ke_state_get = 0x4001a7d8 ); +PROVIDE ( r_ke_state_set = 0x4001a6fc ); +PROVIDE ( r_ke_stats_get = 0x4001a3f0 ); +PROVIDE ( r_ke_task_check = 0x4001a8a4 ); +PROVIDE ( r_ke_task_create = 0x4001a674 ); +PROVIDE ( r_ke_task_delete = 0x4001a6c0 ); +PROVIDE ( r_ke_task_init = 0x4001a650 ); +PROVIDE ( r_ke_task_msg_flush = 0x4001a860 ); +PROVIDE ( r_ke_timer_active = 0x4001ac08 ); +PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 ); +PROVIDE ( r_ke_timer_clear = 0x4001ab90 ); +PROVIDE ( r_ke_timer_init = 0x4001aa9c ); +PROVIDE ( r_ke_timer_set = 0x4001aac0 ); +PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 ); +PROVIDE ( r_KPrimC = 0x40010ad4 ); +PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 ); +PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 ); +PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 ); +PROVIDE ( r_lb_init = 0x4001acd4 ); +PROVIDE ( r_lb_mst_key = 0x4001afc0 ); +PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 ); +PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 ); +PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 ); +PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c ); +PROVIDE ( r_lb_reset = 0x4001ad38 ); +PROVIDE ( r_lb_send_lmp = 0x4001adbc ); +PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c ); +PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 ); +PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 ); +PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 ); +PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c ); +PROVIDE ( r_lc_afh_set = 0x4001cc74 ); +PROVIDE ( r_lc_afh_start = 0x4001d240 ); +PROVIDE ( r_lc_auth_cmp = 0x4001cd54 ); +PROVIDE ( r_lc_calc_link_key = 0x4001ce7c ); +PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 ); +PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc ); +PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac ); +PROVIDE ( r_lc_chk_to = 0x4001d2a8 ); +PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 ); +PROVIDE ( r_lc_comb_key_svr = 0x4001d30c ); +PROVIDE ( r_lc_con_cmp = 0x4001d44c ); +PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc ); +PROVIDE ( r_lc_conn_seq_done = 0x40021334 ); +PROVIDE ( r_lc_detach = 0x4002037c ); +PROVIDE ( r_lc_dhkey = 0x4001d564 ); +PROVIDE ( r_lc_enc_cmp = 0x4001d8bc ); +PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 ); +PROVIDE ( r_lc_end_chk_colli = 0x4001d858 ); +PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 ); +PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 ); +PROVIDE ( r_lc_epr_change_lk = 0x4001db38 ); +PROVIDE ( r_lc_epr_cmp = 0x4001da88 ); +PROVIDE ( r_lc_epr_resp = 0x4001e0b4 ); +PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 ); +PROVIDE ( r_lc_ext_feat = 0x40020d6c ); +PROVIDE ( r_lc_feat = 0x40020984 ); +PROVIDE ( r_lc_hl_connect = 0x400209e8 ); +PROVIDE ( r_lc_init = 0x4001c948 ); +PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 ); +PROVIDE ( r_lc_initiator_epr = 0x4001e064 ); +PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 ); +PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 ); +PROVIDE ( r_lc_key_exch_end = 0x4001e140 ); +PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 ); +PROVIDE ( r_lc_local_switch = 0x4001e22c ); +PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 ); +PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 ); +PROVIDE ( r_lc_loc_auth = 0x40020ecc ); +PROVIDE ( r_lc_locepr_lkref = 0x4001d648 ); +PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 ); +PROVIDE ( r_lc_loc_sniff = 0x40020a6c ); +PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 ); +PROVIDE ( r_lc_mst_key = 0x4001e7c0 ); +PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 ); +PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 ); +PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 ); +PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 ); +PROVIDE ( r_lc_packet_type = 0x40021038 ); +PROVIDE ( r_lc_pair = 0x40020ddc ); +PROVIDE ( r_lc_pairing_cont = 0x4001eafc ); +PROVIDE ( r_lc_passkey_comm = 0x4001ed20 ); +PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 ); +PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec ); +PROVIDE ( r_lc_ptt = 0x4001ee2c ); +PROVIDE ( r_lc_ptt_cmp = 0x4001eeec ); +PROVIDE ( r_lc_qos_setup = 0x4001ef50 ); +PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 ); +PROVIDE ( r_lc_release = 0x4001f8a8 ); +PROVIDE ( r_lc_rem_enc = 0x4001f124 ); +PROVIDE ( r_lc_rem_name_cont = 0x4001f290 ); +PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 ); +PROVIDE ( r_lc_rem_sniff = 0x40020ca4 ); +PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 ); +PROVIDE ( r_lc_rem_switch = 0x4001f070 ); +PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 ); +PROVIDE ( r_lc_rem_unsniff = 0x400207a0 ); +PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c ); +PROVIDE ( r_lc_reset = 0x4001c99c ); +PROVIDE ( r_lc_resp_auth = 0x4001f518 ); +PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 ); +PROVIDE ( r_lc_resp_num_comp = 0x40020074 ); +PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 ); +PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c ); +PROVIDE ( r_lc_resp_pair = 0x400208a4 ); +PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 ); +PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c ); +PROVIDE ( r_lc_restart_enc = 0x4001f8ec ); +PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 ); +PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 ); +PROVIDE ( r_lc_restore_to = 0x4001f9e0 ); +PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 ); +PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 ); +PROVIDE ( r_lc_rsw_done = 0x4001db94 ); +PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 ); +PROVIDE ( r_lc_sco_detach = 0x40021e40 ); +PROVIDE ( r_lc_sco_host_accept = 0x40022118 ); +PROVIDE ( r_lc_sco_host_reject = 0x400222b8 ); +PROVIDE ( r_lc_sco_host_request = 0x40021f4c ); +PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c ); +PROVIDE ( r_lc_sco_init = 0x40021dc8 ); +PROVIDE ( r_lc_sco_peer_accept = 0x40022780 ); +PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 ); +PROVIDE ( r_lc_sco_peer_reject = 0x40022824 ); +PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c ); +PROVIDE ( r_lc_sco_peer_request = 0x4002240c ); +PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec ); +PROVIDE ( r_lc_sco_release = 0x40021eec ); +PROVIDE ( r_lc_sco_reset = 0x40021dfc ); +PROVIDE ( r_lc_sco_timeout = 0x40022bd4 ); +PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec ); +PROVIDE ( r_lc_semi_key_cmp = 0x40020294 ); +PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c ); +PROVIDE ( r_lc_send_enc_mode = 0x40020220 ); +PROVIDE ( r_lc_send_lmp = 0x4001c1a8 ); +PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c ); +PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 ); +PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 ); +PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 ); +PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c ); +PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 ); +PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 ); +PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 ); +PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 ); +PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 ); +PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 ); +PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 ); +PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec ); +PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 ); +PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 ); +PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c ); +PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c ); +PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 ); +PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec ); +PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c ); +PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 ); +PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 ); +PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 ); +PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 ); +PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 ); +PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c ); +PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 ); +PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 ); +PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 ); +PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 ); +PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 ); +PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 ); +PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 ); +PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 ); +PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 ); +PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc ); +PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 ); +PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 ); +PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 ); +PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc ); +PROVIDE ( r_lc_sniff_init = 0x40022cac ); +PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 ); +PROVIDE ( r_lc_sniff_reset = 0x40022cc8 ); +PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 ); +PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc ); +PROVIDE ( r_lc_sp_end = 0x400213a8 ); +PROVIDE ( r_lc_sp_fail = 0x40020470 ); +PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc ); +PROVIDE ( r_lc_ssr_nego = 0x4002125c ); +PROVIDE ( r_lc_start = 0x4001ca28 ); +PROVIDE ( r_lc_start_enc = 0x4001fb28 ); +PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c ); +PROVIDE ( r_lc_start_key_exch = 0x4001fe10 ); +PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 ); +PROVIDE ( r_lc_start_oob = 0x4001fffc ); +PROVIDE ( r_lc_start_passkey = 0x4001feac ); +PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 ); +PROVIDE ( r_lc_stop_afh_report = 0x40020184 ); +PROVIDE ( r_lc_stop_enc = 0x40020110 ); +PROVIDE ( r_lc_switch_cmp = 0x40020448 ); +PROVIDE ( r_lc_unit_key_svr = 0x400206d8 ); +PROVIDE ( r_lc_unsniff = 0x40020c50 ); +PROVIDE ( r_lc_unsniff_cmp = 0x40020810 ); +PROVIDE ( r_lc_unsniff_cont = 0x40020750 ); +PROVIDE ( r_lc_upd_to = 0x4002065c ); +PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 ); +PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac ); +PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 ); +PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c ); +PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 ); +PROVIDE ( r_lc_version = 0x40020a30 ); +PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); +PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); +PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); +PROVIDE ( r_ld_acl_afh_set = 0x40036b60 ); +PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 ); +PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 ); +PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 ); +PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 ); +PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 ); +PROVIDE ( r_ld_acl_clk_set = 0x40036950 ); +PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 ); +PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 ); +PROVIDE ( r_ld_acl_data_flush = 0x400357bc ); +PROVIDE ( r_ld_acl_data_tx = 0x4003544c ); +PROVIDE ( r_ld_acl_edr_set = 0x4003678c ); +PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 ); +PROVIDE ( r_ld_acl_flow_off = 0x40035400 ); +PROVIDE ( r_ld_acl_flow_on = 0x4003541c ); +PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c ); +PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 ); +PROVIDE ( r_ld_acl_init = 0x40034d08 ); +PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 ); +PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 ); +PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 ); +PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 ); +PROVIDE ( r_ld_acl_reset = 0x40034d24 ); +PROVIDE ( r_ld_acl_role_get = 0x40036b30 ); +PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 ); +PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 ); +PROVIDE ( r_ld_acl_rx_enc = 0x40036344 ); +PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 ); +PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 ); +PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c ); +PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 ); +PROVIDE ( r_ld_acl_sniff = 0x4003617c ); +PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 ); +PROVIDE ( r_ld_acl_ssr_set = 0x40036274 ); +PROVIDE ( r_ld_acl_start = 0x40034ddc ); +PROVIDE ( r_ld_acl_stop = 0x4003532c ); +PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 ); +PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c ); +PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 ); +PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 ); +PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 ); +PROVIDE ( r_ld_acl_unsniff = 0x400361e0 ); +PROVIDE ( r_ld_active_check = 0x4003cac4 ); +PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec ); +PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c ); +PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 ); +PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc ); +PROVIDE ( r_ld_bcst_acl_start = 0x4003882c ); +PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c ); +PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c ); +PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 ); +PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 ); +PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 ); +PROVIDE ( r_ld_channel_assess = 0x4003c184 ); +PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 ); +PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 ); +PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 ); +PROVIDE ( r_ld_csb_rx_init = 0x40039690 ); +PROVIDE ( r_ld_csb_rx_reset = 0x4003969c ); +PROVIDE ( r_ld_csb_rx_start = 0x4003972c ); +PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 ); +PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc ); +PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c ); +PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 ); +PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 ); +PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 ); +PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 ); +PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 ); +PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 ); +PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c ); +PROVIDE ( r_ld_fm_init = 0x4003a760 ); +PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 ); +PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 ); +PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 ); +PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 ); +PROVIDE ( r_ld_fm_reset = 0x4003a794 ); +PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 ); +PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 ); +PROVIDE ( r_ld_init = 0x4003c294 ); +PROVIDE ( r_ld_inq_init = 0x4003b15c ); +PROVIDE ( r_ld_inq_reset = 0x4003b168 ); +PROVIDE ( r_ld_inq_start = 0x4003b1f0 ); +PROVIDE ( r_ld_inq_stop = 0x4003b4f0 ); +PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 ); +PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 ); +PROVIDE ( r_ld_iscan_init = 0x4003b9f0 ); +PROVIDE ( r_ld_iscan_reset = 0x4003ba14 ); +PROVIDE ( r_ld_iscan_restart = 0x4003ba44 ); +PROVIDE ( r_ld_iscan_start = 0x4003bb28 ); +PROVIDE ( r_ld_iscan_stop = 0x4003bf1c ); +PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 ); +PROVIDE ( r_ld_page_init = 0x4003d808 ); +PROVIDE ( r_ld_page_reset = 0x4003d814 ); +PROVIDE ( r_ld_page_start = 0x4003d848 ); +PROVIDE ( r_ld_page_stop = 0x4003da54 ); +PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 ); +PROVIDE ( r_ld_pca_init = 0x4003deb4 ); +PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac ); +PROVIDE ( r_ld_pca_local_config = 0x4003df6c ); +PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 ); +PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 ); +PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 ); +PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 ); +PROVIDE ( r_ld_pca_reset = 0x4003df0c ); +PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 ); +PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 ); +PROVIDE ( r_ld_pscan_init = 0x4003f474 ); +PROVIDE ( r_ld_pscan_reset = 0x4003f498 ); +PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 ); +PROVIDE ( r_ld_pscan_start = 0x4003f514 ); +PROVIDE ( r_ld_pscan_stop = 0x4003f618 ); +PROVIDE ( r_ld_read_clock = 0x4003c9e4 ); +PROVIDE ( r_ld_reset = 0x4003c714 ); +PROVIDE ( r_ld_sched_acl_add = 0x4003f978 ); +PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c ); +PROVIDE ( r_ld_sched_compute = 0x4003f6f8 ); +PROVIDE ( r_ld_sched_init = 0x4003f7ac ); +PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 ); +PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 ); +PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 ); +PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 ); +PROVIDE ( r_ld_sched_page_add = 0x4003f910 ); +PROVIDE ( r_ld_sched_page_remove = 0x4003f938 ); +PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 ); +PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 ); +PROVIDE ( r_ld_sched_reset = 0x4003f7d4 ); +PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c ); +PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c ); +PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 ); +PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c ); +PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 ); +PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 ); +PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 ); +PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 ); +PROVIDE ( r_ld_sco_start = 0x40037110 ); +PROVIDE ( r_ld_sco_stop = 0x40037c40 ); +PROVIDE ( r_ld_sco_update = 0x40037a74 ); +PROVIDE ( r_ld_sscan_activated = 0x4004031c ); +PROVIDE ( r_ld_sscan_init = 0x400402f0 ); +PROVIDE ( r_ld_sscan_reset = 0x400402fc ); +PROVIDE ( r_ld_sscan_start = 0x40040384 ); +PROVIDE ( r_ld_strain_init = 0x400409f4 ); +PROVIDE ( r_ld_strain_reset = 0x40040a00 ); +PROVIDE ( r_ld_strain_start = 0x40040a8c ); +PROVIDE ( r_ld_strain_stop = 0x40040df0 ); +PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac ); +PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c ); +PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 ); +PROVIDE ( r_ld_util_bch_create = 0x40040fcc ); +PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 ); +PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 ); +PROVIDE ( r_ld_util_stp_pk = 0x400413f4 ); +PROVIDE ( r_ld_util_stp_unpk = 0x40041324 ); +PROVIDE ( r_ld_version_get = 0x4003ca6c ); +PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 ); +PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 ); +PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c ); +PROVIDE ( r_llc_ch_assess_local = 0x40041494 ); +PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 ); +PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 ); +PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac ); +PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 ); +PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c ); +PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 ); +PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c ); +PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 ); +PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 ); +PROVIDE ( r_llc_con_update_finished = 0x4004518c ); +PROVIDE ( r_llc_con_update_ind = 0x40045038 ); +PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 ); +PROVIDE ( r_llc_end_evt_defer = 0x40046330 ); +PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c ); +PROVIDE ( r_llc_init = 0x40044778 ); +PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 ); +PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 ); +PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc ); +PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 ); +PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 ); +PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 ); +PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 ); +PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 ); +PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 ); +PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c ); +PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 ); +PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac ); +PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 ); +PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 ); +PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c ); +PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 ); +PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 ); +PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c ); +PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c ); +PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 ); +PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 ); +PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 ); +PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 ); +PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c ); +PROVIDE ( r_llc_lsto_con_update = 0x40045098 ); +PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 ); +PROVIDE ( r_llc_map_update_finished = 0x40045260 ); +PROVIDE ( r_llc_map_update_ind = 0x400450f0 ); +PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc ); +PROVIDE ( r_llc_pdu_defer = 0x40046528 ); +PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac ); +PROVIDE ( r_llc_reset = 0x400447b8 ); +PROVIDE ( r_llc_start = 0x400447f4 ); +PROVIDE ( r_llc_stop = 0x400449ac ); +PROVIDE ( r_llc_util_bw_mgt = 0x4004629c ); +PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 ); +PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 ); +PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 ); +PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 ); +PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 ); +PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 ); +PROVIDE ( r_llc_util_update_channel_map = 0x400461ac ); +PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 ); +PROVIDE ( r_lld_adv_start = 0x40048b38 ); +PROVIDE ( r_lld_adv_stop = 0x40048ea0 ); +PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 ); +PROVIDE ( r_lld_con_param_req = 0x40049f0c ); +PROVIDE ( r_lld_con_param_rsp = 0x40049e00 ); +PROVIDE ( r_lld_con_start = 0x400491f8 ); +PROVIDE ( r_lld_con_stop = 0x40049fdc ); +PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc ); +PROVIDE ( r_lld_con_update_ind = 0x4004a30c ); +PROVIDE ( r_lld_con_update_req = 0x40049b60 ); +PROVIDE ( r_lld_core_reset = 0x40048a9c ); +PROVIDE ( r_lld_crypt_isr = 0x4004a324 ); +PROVIDE ( r_lld_evt_adv_create = 0x400481f4 ); +PROVIDE ( r_lld_evt_canceled = 0x400485c8 ); +PROVIDE ( r_lld_evt_channel_next = 0x40046aac ); +PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc ); +PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 ); +PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c ); +PROVIDE ( r_lld_evt_drift_compute = 0x40047670 ); +PROVIDE ( r_lld_evt_elt_delete = 0x40047538 ); +PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 ); +PROVIDE ( r_lld_evt_end = 0x400483e8 ); +PROVIDE ( r_lld_evt_end_isr = 0x4004862c ); +PROVIDE ( r_lld_evt_init = 0x40046b3c ); +PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 ); +PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 ); +PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 ); +PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc ); +PROVIDE ( r_lld_evt_restart = 0x40046d50 ); +PROVIDE ( r_lld_evt_rx = 0x40048578 ); +PROVIDE ( r_lld_evt_rx_isr = 0x40048678 ); +PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 ); +PROVIDE ( r_lld_evt_schedule = 0x40047908 ); +PROVIDE ( r_lld_evt_schedule_next = 0x400477dc ); +PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 ); +PROVIDE ( r_lld_evt_slave_update = 0x40048138 ); +PROVIDE ( r_lld_evt_update_create = 0x40047cd8 ); +PROVIDE ( r_lld_get_mode = 0x40049ff8 ); +PROVIDE ( r_lld_init = 0x4004873c ); +PROVIDE ( r_lld_move_to_master = 0x400499e0 ); +PROVIDE ( r_lld_move_to_slave = 0x4004a024 ); +PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 ); +PROVIDE ( r_lld_pdu_check = 0x4004ac34 ); +PROVIDE ( r_lld_pdu_data_send = 0x4004b018 ); +PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc ); +PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 ); +PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 ); +PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 ); +PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 ); +PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 ); +PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 ); +PROVIDE ( r_lld_ral_renew_req = 0x4004a73c ); +/**************************************************************************** + * configs/elf32-core/scripts/esp32_rom.ld + ****************************************************************************/ + +PROVIDE ( r_lld_scan_start = 0x40048ee0 ); +PROVIDE ( r_lld_scan_stop = 0x40049190 ); +PROVIDE ( r_lld_test_mode_rx = 0x4004a540 ); +PROVIDE ( r_lld_test_mode_tx = 0x4004a350 ); +PROVIDE ( r_lld_test_stop = 0x4004a710 ); +PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc ); +PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c ); +PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 ); +PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 ); +PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 ); +PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 ); +PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 ); +PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 ); +PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac ); +PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 ); +PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 ); +PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 ); +PROVIDE ( r_lld_util_instant_get = 0x4004b890 ); +PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc ); +PROVIDE ( r_lld_util_priority_set = 0x4004bd10 ); +PROVIDE ( r_lld_util_priority_update = 0x4004bd78 ); +PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 ); +PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 ); +PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 ); +PROVIDE ( r_llm_ble_ready = 0x4004cc34 ); +PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 ); +PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 ); +PROVIDE ( r_llm_con_req_ind = 0x4004cc54 ); +PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 ); +PROVIDE ( r_llm_create_con = 0x4004de78 ); +PROVIDE ( r_llm_encryption_done = 0x4004dff8 ); +PROVIDE ( r_llm_encryption_start = 0x4004e128 ); +PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c ); +PROVIDE ( r_llm_init = 0x4004c9f8 ); +PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 ); +PROVIDE ( r_llm_pdu_defer = 0x4004ec48 ); +PROVIDE ( r_llm_ral_clear = 0x4004e1fc ); +PROVIDE ( r_llm_ral_dev_add = 0x4004e23c ); +PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc ); +PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 ); +PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 ); +PROVIDE ( r_llm_ral_update = 0x4004e4f8 ); +PROVIDE ( r_llm_set_adv_data = 0x4004d960 ); +PROVIDE ( r_llm_set_adv_en = 0x4004d7ec ); +PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 ); +PROVIDE ( r_llm_set_scan_en = 0x4004db64 ); +PROVIDE ( r_llm_set_scan_param = 0x4004dac8 ); +PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 ); +PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 ); +PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc ); +PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc ); +PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 ); +PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 ); +PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 ); +PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 ); +PROVIDE ( r_llm_util_bl_add = 0x4004e9ac ); +PROVIDE ( r_llm_util_bl_check = 0x4004e930 ); +PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 ); +PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 ); +PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 ); +PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 ); +PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 ); +PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 ); +PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c ); +PROVIDE ( r_llm_wl_clr = 0x4004dc54 ); +PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 ); +PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 ); +PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc ); +PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 ); +PROVIDE ( r_lm_acl_disc = 0x4004f148 ); +PROVIDE ( r_LM_AddSniff = 0x40022d20 ); +PROVIDE ( r_lm_add_sync = 0x40051358 ); +PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 ); +PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 ); +PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 ); +PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c ); +PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 ); +PROVIDE ( r_lm_check_active_sync = 0x40051334 ); +PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c ); +PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 ); +PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c ); +PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 ); +PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 ); +PROVIDE ( r_LM_ComputePacketType = 0x4002f554 ); +PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac ); +PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 ); +PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 ); +PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 ); +PROVIDE ( r_lm_dhkey_compare = 0x400132d8 ); +PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec ); +PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 ); +PROVIDE ( r_lm_f1 = 0x40012bb8 ); +PROVIDE ( r_lm_f2 = 0x40012cfc ); +PROVIDE ( r_lm_f3 = 0x40013050 ); +PROVIDE ( r_lm_g = 0x40012f90 ); +PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c ); +PROVIDE ( r_lm_get_auth_en = 0x4004f1ac ); +PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c ); +PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 ); +PROVIDE ( r_LM_GetFeature = 0x4002f924 ); +PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec ); +PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 ); +PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 ); +PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c ); +PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 ); +PROVIDE ( r_LM_GetMasterKey = 0x4001b260 ); +PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 ); +PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 ); +PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c ); +PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c ); +PROVIDE ( r_lm_get_nonce = 0x400131c4 ); +PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 ); +PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 ); +PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 ); +PROVIDE ( r_LM_GetPINType = 0x4004f1e8 ); +PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 ); +PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 ); +PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 ); +PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 ); +PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 ); +PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 ); +PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c ); +PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 ); +PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 ); +PROVIDE ( r_lm_get_synchdl = 0x4005175c ); +PROVIDE ( r_lm_get_sync_param = 0x400503b4 ); +PROVIDE ( r_lm_init = 0x4004ed34 ); +PROVIDE ( r_lm_init_sync = 0x400512d8 ); +PROVIDE ( r_lm_is_acl_con = 0x4004f47c ); +PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c ); +PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 ); +PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 ); +PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 ); +PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 ); +PROVIDE ( r_lm_look_for_sync = 0x40051774 ); +PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c ); +PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 ); +PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 ); +PROVIDE ( r_LM_MakeCof = 0x4002f84c ); +PROVIDE ( r_LM_MakeRandVec = 0x400112d8 ); +PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 ); +PROVIDE ( r_LM_MaxSlot = 0x4002f694 ); +PROVIDE ( r_lm_modif_sync = 0x40051578 ); +PROVIDE ( r_lm_n_is_zero = 0x40012170 ); +PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 ); +PROVIDE ( r_lm_oob_f1 = 0x40012e54 ); +PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 ); +PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 ); +PROVIDE ( r_lmp_pack = 0x4001135c ); +PROVIDE ( r_lmp_unpack = 0x4001149c ); +PROVIDE ( r_lm_read_features = 0x4004f0d8 ); +PROVIDE ( r_LM_RemoveSniff = 0x40023124 ); +PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 ); +PROVIDE ( r_lm_remove_sync = 0x400517c8 ); +PROVIDE ( r_lm_reset_sync = 0x40051304 ); +PROVIDE ( r_lm_role_switch_finished = 0x4004f028 ); +PROVIDE ( r_lm_role_switch_start = 0x4004efe0 ); +PROVIDE ( r_lm_sco_nego_end = 0x40051828 ); +PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 ); +PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 ); +PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc ); +PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 ); +PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 ); +PROVIDE ( r_lm_sp_n_one = 0x400123a4 ); +PROVIDE ( r_lm_sp_p192_add = 0x40012828 ); +PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c ); +PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c ); +PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 ); +PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 ); +PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 ); +PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 ); +PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 ); +PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 ); +PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 ); +PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 ); +PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 ); +PROVIDE ( r_modules_funcs = 0x3ffafd6c ); +PROVIDE ( r_modules_funcs_p = 0x3ffafd68 ); +PROVIDE ( r_nvds_del = 0x400544c4 ); +PROVIDE ( r_nvds_get = 0x40054488 ); +PROVIDE ( r_nvds_init = 0x40054410 ); +PROVIDE ( r_nvds_lock = 0x400544fc ); +PROVIDE ( r_nvds_put = 0x40054534 ); +PROVIDE ( rom_abs_temp = 0x400054f0 ); +PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c ); +PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac ); +PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 ); +PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 ); +PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 ); +PROVIDE ( rom_cbw2040_cfg = 0x400040b0 ); +PROVIDE ( rom_check_noise_floor = 0x40003c78 ); +PROVIDE ( rom_chip_i2c_readReg = 0x40004110 ); +PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 ); +PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c ); +PROVIDE ( rom_chip_v7_rx_init = 0x40004cec ); +PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 ); +PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 ); +PROVIDE ( rom_clk_force_on_vit = 0x40003710 ); +PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 ); +PROVIDE ( rom_dc_iq_est = 0x400055c8 ); +PROVIDE ( rom_disable_agc = 0x40002fa4 ); +PROVIDE ( rom_enable_agc = 0x40002fcc ); +PROVIDE ( rom_en_pwdet = 0x4000506c ); +PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c ); +PROVIDE ( rom_get_data_sat = 0x4000312c ); +PROVIDE ( rom_get_fm_sar_dout = 0x40005204 ); +PROVIDE ( rom_get_power_db = 0x40005fc8 ); +PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); +PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); +PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); +PROVIDE ( rom_get_sar_dout = 0x40006564 ); +PROVIDE ( rom_i2c_readReg = 0x40004148 ); +PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 ); +PROVIDE ( rom_i2c_writeReg = 0x400041a4 ); +PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc ); +PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); +PROVIDE ( rom_iq_est_disable = 0x40005590 ); +PROVIDE ( rom_iq_est_enable = 0x40005514 ); +PROVIDE ( rom_linear_to_db = 0x40005f64 ); +PROVIDE ( rom_loopback_mode_en = 0x400030f8 ); +PROVIDE ( rom_main = 0x400076c4 ); +PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 ); +PROVIDE ( rom_mhz2ieee = 0x4000404c ); +PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc ); +PROVIDE ( rom_pbus_debugmode = 0x40004458 ); +PROVIDE ( rom_pbus_force_mode = 0x40004270 ); +PROVIDE ( rom_pbus_force_test = 0x400043c0 ); +PROVIDE ( rom_pbus_rd = 0x40004414 ); +PROVIDE ( rom_pbus_rd_addr = 0x40004334 ); +PROVIDE ( rom_pbus_rd_shift = 0x40004374 ); +PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 ); +PROVIDE ( rom_pbus_set_dco = 0x40004638 ); +PROVIDE ( rom_pbus_set_rxgain = 0x40004480 ); +PROVIDE ( rom_pbus_workmode = 0x4000446c ); +PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 ); +PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c ); +PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 ); +PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 ); +PROVIDE ( rom_phy_disable_agc = 0x40002f6c ); +PROVIDE ( rom_phy_disable_cca = 0x40003000 ); +PROVIDE ( rom_phy_enable_agc = 0x40002f88 ); +PROVIDE ( rom_phy_enable_cca = 0x4000302c ); +PROVIDE ( rom_phy_freq_correct = 0x40004b44 ); +PROVIDE ( rom_phyFuns = 0x3ffae0c0 ); +PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c ); +PROVIDE ( rom_phy_get_vdd33 = 0x4000642c ); +PROVIDE ( rom_pow_usr = 0x40003044 ); +PROVIDE ( rom_read_sar_dout = 0x400051c0 ); +PROVIDE ( rom_restart_cal = 0x400046e0 ); +PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 ); +PROVIDE ( rom_rfcal_rxiq = 0x40005b4c ); +PROVIDE ( rom_rfcal_txcap = 0x40005dec ); +PROVIDE ( rom_rfpll_reset = 0x40004680 ); +PROVIDE ( rom_rfpll_set_freq = 0x400047f8 ); +PROVIDE ( rom_rtc_mem_backup = 0x40003db4 ); +PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 ); +PROVIDE ( rom_rx_gain_force = 0x4000351c ); +PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 ); +PROVIDE ( rom_rxiq_get_mis = 0x400058e4 ); +PROVIDE ( rom_rxiq_set_reg = 0x40005a00 ); +PROVIDE ( rom_set_cal_rxdc = 0x400030b8 ); +PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 ); +PROVIDE ( rom_set_channel_freq = 0x40004880 ); +PROVIDE ( rom_set_loopback_gain = 0x40003060 ); +PROVIDE ( rom_set_noise_floor = 0x40003d48 ); +PROVIDE ( rom_set_pbus_mem = 0x400031a4 ); +PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 ); +PROVIDE ( rom_set_rxclk_en = 0x40003594 ); +PROVIDE ( rom_set_txcap_reg = 0x40005d50 ); +PROVIDE ( rom_set_txclk_en = 0x40003564 ); +PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 ); +PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 ); +PROVIDE ( rom_start_tx_tone = 0x400036b4 ); +PROVIDE ( rom_start_tx_tone_step = 0x400035d0 ); +PROVIDE ( rom_stop_tx_tone = 0x40003f98 ); +PROVIDE ( _rom_store = 0x4000d66c ); +PROVIDE ( _rom_store_table = 0x4000d4f8 ); +PROVIDE ( rom_target_power_add_backoff = 0x40006268 ); +PROVIDE ( rom_tx_atten_set_interp = 0x400061cc ); +PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 ); +PROVIDE ( rom_txcal_work_mode = 0x4000510c ); +PROVIDE ( rom_txdc_cal_init = 0x40004e10 ); +PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 ); +PROVIDE ( rom_txiq_cover = 0x4000538c ); +PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc ); +PROVIDE ( rom_txiq_set_reg = 0x40005154 ); +PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c ); +PROVIDE ( rom_txtone_linear_pwr = 0x40005290 ); +PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 ); +PROVIDE ( rom_write_gain_mem = 0x4000348c ); +PROVIDE ( rom_write_rfpll_sdm = 0x40004740 ); +PROVIDE ( roundup2 = 0x4000ab7c ); +PROVIDE ( r_plf_funcs_p = 0x3ffb8360 ); +PROVIDE ( r_rf_rw_bt_init = 0x40054868 ); +PROVIDE ( r_rf_rw_init = 0x40054b0c ); +PROVIDE ( r_rf_rw_le_init = 0x400549d0 ); +PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c ); +PROVIDE ( r_rwble_init = 0x40054bf4 ); +PROVIDE ( r_rwble_isr = 0x40054e08 ); +PROVIDE ( r_rwble_reset = 0x40054ce8 ); +PROVIDE ( r_rwble_sleep_check = 0x40054d78 ); +PROVIDE ( r_rwble_version = 0x40054dac ); +PROVIDE ( r_rwbt_init = 0x40055160 ); +PROVIDE ( r_rwbt_isr = 0x40055248 ); +PROVIDE ( r_rwbt_reset = 0x400551bc ); +PROVIDE ( r_rwbt_sleep_check = 0x4005577c ); +PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 ); +PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc ); +PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc ); +PROVIDE ( r_rwbt_version = 0x4005520c ); +PROVIDE ( r_rwip_assert_err = 0x40055f88 ); +PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc ); +PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c ); +PROVIDE ( r_rwip_init = 0x4005595c ); +PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 ); +PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 ); +PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 ); +PROVIDE ( r_rwip_reset = 0x40055ab8 ); +PROVIDE ( r_rwip_schedule = 0x40055b38 ); +PROVIDE ( r_rwip_sleep = 0x40055b5c ); +PROVIDE ( r_rwip_sleep_enable = 0x40055f30 ); +PROVIDE ( r_rwip_version = 0x40055b20 ); +PROVIDE ( r_rwip_wakeup = 0x40055dc4 ); +PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c ); +PROVIDE ( r_rwip_wakeup_end = 0x40055e18 ); +PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 ); +PROVIDE ( r_SHA_256 = 0x40013a90 ); +PROVIDE ( rtc_boot_control = 0x4000821c ); +PROVIDE ( rtc_get_reset_reason = 0x400081d4 ); +PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 ); +PROVIDE ( rtc_select_apb_bridge = 0x40008288 ); +PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); +PROVIDE ( rwip_priority = 0x3ff99159 ); +PROVIDE ( rwip_rf = 0x3ffbdb28 ); +PROVIDE ( rwip_rf_p_get = 0x400558f4 ); +PROVIDE ( r_XorKey = 0x400112c0 ); +PROVIDE ( sbrk = 0x400017f4 ); +PROVIDE ( _sbrk_r = 0x4000bce4 ); +PROVIDE ( scanf = 0x40058760 ); +PROVIDE ( _scanf_chars = 0x40058384 ); +PROVIDE ( _scanf_float = 0x4000bf18 ); +PROVIDE ( _scanf_i = 0x4005845c ); +PROVIDE ( _scanf_r = 0x4005879c ); +PROVIDE ( __sccl = 0x4000c498 ); +PROVIDE ( __sclose = 0x400011b8 ); +PROVIDE ( SelectSpiFunction = 0x40061f84 ); +PROVIDE ( SelectSpiQIO = 0x40061ddc ); +PROVIDE ( SendMsg = 0x40009384 ); +PROVIDE ( send_packet = 0x40009340 ); +PROVIDE ( __seofread = 0x40001148 ); +PROVIDE ( setjmp = 0x40056268 ); +PROVIDE ( setlocale = 0x40059568 ); +PROVIDE ( _setlocale_r = 0x4005950c ); +PROVIDE ( set_rtc_memory_crc = 0x40008208 ); +PROVIDE ( SetSpiDrvs = 0x40061e78 ); +PROVIDE ( __sf_fake_stderr = 0x3ff96458 ); +PROVIDE ( __sf_fake_stdin = 0x3ff96498 ); +PROVIDE ( __sf_fake_stdout = 0x3ff96478 ); +PROVIDE ( __sflush_r = 0x400591e0 ); +PROVIDE ( __sfmoreglue = 0x40001dc8 ); +PROVIDE ( __sfp = 0x40001e90 ); +PROVIDE ( __sfp_lock_acquire = 0x40001e08 ); +PROVIDE ( __sfp_lock_release = 0x40001e14 ); +PROVIDE ( __sfputs_r = 0x40057790 ); +PROVIDE ( __sfvwrite_r = 0x4005893c ); +PROVIDE ( sha1_prf = 0x40060ae8 ); +PROVIDE ( sha1_vector = 0x40060b64 ); +PROVIDE ( sha256_prf = 0x40060d70 ); +PROVIDE ( sha256_vector = 0x40060e08 ); +PROVIDE ( sha_blk_bits = 0x3ff99290 ); +PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 ); +PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c ); +PROVIDE ( sig_matrix = 0x3ffae293 ); +PROVIDE ( __sinit = 0x40001e38 ); +PROVIDE ( __sinit_lock_acquire = 0x40001e20 ); +PROVIDE ( __sinit_lock_release = 0x40001e2c ); +PROVIDE ( sip_after_tx_complete = 0x4000b358 ); +PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c ); +PROVIDE ( sip_get_ptr = 0x4000b34c ); +PROVIDE ( sip_get_state = 0x4000ae2c ); +PROVIDE ( sip_init_attach = 0x4000ae58 ); +PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 ); +PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 ); +PROVIDE ( sip_is_active = 0x4000b3c0 ); +PROVIDE ( sip_post_init = 0x4000aed8 ); +PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc ); +PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c ); +PROVIDE ( siprintf = 0x40056c08 ); +PROVIDE ( _siprintf_r = 0x40056bbc ); +PROVIDE ( sip_send = 0x4000af54 ); +PROVIDE ( sip_to_host_chain_append = 0x4000aef8 ); +PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 ); +PROVIDE ( siscanf = 0x400587d0 ); +PROVIDE ( _siscanf_r = 0x40058830 ); +PROVIDE ( slc_add_credits = 0x4000baf4 ); +PROVIDE ( slc_enable = 0x4000b64c ); +PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 ); +PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 ); +PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc ); +PROVIDE ( slc_init_attach = 0x4000b918 ); +PROVIDE ( slc_init_credit = 0x4000badc ); +PROVIDE ( slc_reattach = 0x4000b62c ); +PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 ); +PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); +PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); +PROVIDE ( __smakebuf_r = 0x40059108 ); +PROVIDE ( sniprintf = 0x40056b4c ); +PROVIDE ( _sniprintf_r = 0x40056ae4 ); +PROVIDE ( snprintf = 0x40056b4c ); +PROVIDE ( _snprintf_r = 0x40056ae4 ); +PROVIDE ( software_reset = 0x4000824c ); +PROVIDE ( software_reset_cpu = 0x40008264 ); +PROVIDE ( specialModP256 = 0x4001600c ); +PROVIDE ( spi_cache_sram_init = 0x400626e4 ); +PROVIDE ( SPIClkConfig = 0x40062bc8 ); +PROVIDE ( SPI_Common_Command = 0x4006246c ); +PROVIDE ( spi_dummy_len_fix = 0x40061d90 ); +PROVIDE ( SPI_Encrypt_Write = 0x40062e78 ); +PROVIDE ( SPIEraseArea = 0x400631ac ); +PROVIDE ( SPIEraseBlock = 0x40062c4c ); +PROVIDE ( SPIEraseChip = 0x40062c14 ); +PROVIDE ( SPIEraseSector = 0x40062ccc ); +PROVIDE ( spi_flash_attach = 0x40062a6c ); +PROVIDE ( SPILock = 0x400628f0 ); +PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 ); +PROVIDE ( spi_modes = 0x3ff99270 ); +PROVIDE ( SPIParamCfg = 0x40063238 ); +PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); +PROVIDE ( SPIRead = 0x40062ed8 ); +PROVIDE ( SPIReadModeCnfig = 0x40062944 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status = 0x4006226c ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status_high = 0x40062448 ); +PROVIDE ( SPIUnlock = 0x400628b0 ); +PROVIDE ( SPI_user_command_read = 0x400621b0 ); +PROVIDE ( spi_w25q16 = 0x3ffae270 ); +PROVIDE ( SPIWrite = 0x40062d50 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_enable = 0x40062320 ); +PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); +PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_status = 0x400622f0 ); +PROVIDE ( sprintf = 0x40056c08 ); +PROVIDE ( _sprintf_r = 0x40056bbc ); +PROVIDE ( __sprint_r = 0x400577e4 ); +PROVIDE ( srand = 0x40001004 ); +PROVIDE ( __sread = 0x40001118 ); +PROVIDE ( __srefill_r = 0x400593d4 ); +PROVIDE ( sscanf = 0x400587d0 ); +PROVIDE ( _sscanf_r = 0x40058830 ); +PROVIDE ( __sseek = 0x40001184 ); +PROVIDE ( __ssprint_r = 0x40056ff8 ); +PROVIDE ( __ssputs_r = 0x40056f2c ); +PROVIDE ( __ssrefill_r = 0x40057fec ); +PROVIDE ( __ssvfiscanf_r = 0x4005802c ); +PROVIDE ( __ssvfscanf_r = 0x4005802c ); +PROVIDE ( __stack = 0x3ffe3f20 ); +PROVIDE ( __stack_app = 0x3ffe7e30 ); +PROVIDE ( _stack_sentry = 0x3ffe1320 ); +PROVIDE ( _stack_sentry_app = 0x3ffe5230 ); +PROVIDE ( _start = 0x40000704 ); +PROVIDE ( start_tb_console = 0x4005a980 ); +PROVIDE ( _stat_r = 0x4000bcb4 ); +PROVIDE ( _stext = 0x40000560 ); +PROVIDE ( strcasecmp = 0x400011cc ); +PROVIDE ( strcasestr = 0x40001210 ); +PROVIDE ( strcat = 0x4000c518 ); +PROVIDE ( strchr = 0x4000c53c ); +PROVIDE ( strcmp = 0x40001274 ); +PROVIDE ( strcoll = 0x40001398 ); +PROVIDE ( strcpy = 0x400013ac ); +PROVIDE ( strcspn = 0x4000c558 ); +PROVIDE ( strdup = 0x4000143c ); +PROVIDE ( _strdup_r = 0x40001450 ); +PROVIDE ( strftime = 0x40059ab4 ); +PROVIDE ( strlcat = 0x40001470 ); +PROVIDE ( strlcpy = 0x4000c584 ); +PROVIDE ( strlen = 0x400014c0 ); +PROVIDE ( strlwr = 0x40001524 ); +PROVIDE ( strncasecmp = 0x40001550 ); +PROVIDE ( strncat = 0x4000c5c4 ); +PROVIDE ( strncmp = 0x4000c5f4 ); +PROVIDE ( strncpy = 0x400015d4 ); +PROVIDE ( strndup = 0x400016b0 ); +PROVIDE ( _strndup_r = 0x400016c4 ); +PROVIDE ( strnlen = 0x4000c628 ); +PROVIDE ( strrchr = 0x40001708 ); +PROVIDE ( strsep = 0x40001734 ); +PROVIDE ( strspn = 0x4000c648 ); +PROVIDE ( strstr = 0x4000c674 ); +PROVIDE ( __strtok_r = 0x4000c6a8 ); +PROVIDE ( strtok_r = 0x4000c70c ); +PROVIDE ( strtol = 0x4005681c ); +PROVIDE ( _strtol_r = 0x40056714 ); +PROVIDE ( strtoul = 0x4005692c ); +PROVIDE ( _strtoul_r = 0x40056834 ); +PROVIDE ( strupr = 0x4000174c ); +PROVIDE ( __subdf3 = 0x400026e4 ); +PROVIDE ( __submore = 0x40058f3c ); +PROVIDE ( __subsf3 = 0x400021d0 ); +PROVIDE ( SubtractBigHex256 = 0x40015bcc ); +PROVIDE ( SubtractBigHexMod256 = 0x40015e8c ); +PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c ); +PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 ); +PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 ); +PROVIDE ( __subvdi3 = 0x40002d20 ); +PROVIDE ( __subvsi3 = 0x40002cf8 ); +PROVIDE ( _sungetc_r = 0x40057f6c ); +PROVIDE ( _svfiprintf_r = 0x40057100 ); +PROVIDE ( __svfiscanf_r = 0x40057b08 ); +PROVIDE ( _svfprintf_r = 0x40057100 ); +PROVIDE ( __svfscanf = 0x40057f04 ); +PROVIDE ( __svfscanf_r = 0x40057b08 ); +PROVIDE ( __swbuf = 0x40058cb4 ); +PROVIDE ( __swbuf_r = 0x40058bec ); +PROVIDE ( __swrite = 0x40001150 ); +PROVIDE ( __swsetup_r = 0x40058cc8 ); +PROVIDE ( sw_to_hw = 0x3ffb8d40 ); +PROVIDE ( _SyscallException = 0x400007cf ); +PROVIDE ( syscall_table_ptr_app = 0x3ffae020 ); +PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 ); +PROVIDE ( _system_r = 0x4000bc10 ); +PROVIDE ( tdefl_compress = 0x400600bc ); +PROVIDE ( tdefl_compress_buffer = 0x400607f4 ); +PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 ); +PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 ); +PROVIDE ( tdefl_get_adler32 = 0x400608d8 ); +PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 ); +PROVIDE ( tdefl_init = 0x40060810 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 ); +PROVIDE ( time = 0x40001844 ); +PROVIDE ( __time_load_locale = 0x4000183c ); +PROVIDE ( times = 0x40001808 ); +PROVIDE ( _times_r = 0x4000bc40 ); +PROVIDE ( _timezone = 0x3ffae0a0 ); +PROVIDE ( tinfl_decompress = 0x4005ef30 ); +PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 ); +PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 ); +PROVIDE ( toascii = 0x4000c720 ); +PROVIDE ( tolower = 0x40001868 ); +PROVIDE ( toupper = 0x40001884 ); +PROVIDE ( __truncdfsf2 = 0x40002b90 ); +PROVIDE ( __tzcalc_limits = 0x400018a0 ); +PROVIDE ( __tz_lock = 0x40001a04 ); +PROVIDE ( _tzname = 0x3ffae030 ); +PROVIDE ( tzset = 0x40001a1c ); +PROVIDE ( _tzset_r = 0x40001a28 ); +PROVIDE ( __tz_unlock = 0x40001a10 ); +PROVIDE ( uartAttach = 0x40008fd0 ); +PROVIDE ( uart_baudrate_detect = 0x40009034 ); +PROVIDE ( uart_buff_switch = 0x400093c0 ); +PROVIDE ( UartConnCheck = 0x40008738 ); +PROVIDE ( UartConnectProc = 0x40008a04 ); +PROVIDE ( UartDev = 0x3ffe019c ); +PROVIDE ( uart_div_modify = 0x400090cc ); +PROVIDE ( UartDwnLdProc = 0x40008ce8 ); +PROVIDE ( UartGetCmdLn = 0x40009564 ); +PROVIDE ( Uart_Init = 0x40009120 ); +PROVIDE ( UartRegReadProc = 0x40008a58 ); +PROVIDE ( UartRegWriteProc = 0x40008a14 ); +PROVIDE ( uart_rx_intr_handler = 0x40008f4c ); +PROVIDE ( uart_rx_one_char = 0x400092d0 ); +PROVIDE ( uart_rx_one_char_block = 0x400092a4 ); +PROVIDE ( uart_rx_readbuff = 0x40009394 ); +PROVIDE ( UartRxString = 0x400092fc ); +PROVIDE ( UartSetBaudProc = 0x40008aac ); +PROVIDE ( UartSpiAttachProc = 0x40008a6c ); +PROVIDE ( UartSpiReadProc = 0x40008a80 ); +PROVIDE ( uart_tx_flush = 0x40009258 ); +PROVIDE ( uart_tx_one_char = 0x40009200 ); +PROVIDE ( uart_tx_one_char2 = 0x4000922c ); +PROVIDE ( uart_tx_switch = 0x40009028 ); +PROVIDE ( uart_tx_wait_idle = 0x40009278 ); +PROVIDE ( __ucmpdi2 = 0x40063840 ); +PROVIDE ( __udivdi3 = 0x4000cff8 ); +PROVIDE ( __udivmoddi4 = 0x40064ab0 ); +PROVIDE ( __udivsi3 = 0x4000c7c8 ); +PROVIDE ( __udiv_w_sdiv = 0x40064aa8 ); +PROVIDE ( __umoddi3 = 0x4000d280 ); +PROVIDE ( __umodsi3 = 0x4000c7d0 ); +PROVIDE ( __umulsidi3 = 0x4000c7d8 ); +PROVIDE ( ungetc = 0x400590f4 ); +PROVIDE ( _ungetc_r = 0x40058fa0 ); +PROVIDE ( _unlink_r = 0x4000bc84 ); +PROVIDE ( __unorddf2 = 0x400637f4 ); +PROVIDE ( __unordsf2 = 0x40063478 ); +PROVIDE ( user_code_start = 0x3ffe0400 ); +PROVIDE ( _UserExceptionVector = 0x40000340 ); +PROVIDE ( utoa = 0x40056258 ); +PROVIDE ( __utoa = 0x400561f0 ); +PROVIDE ( vasiprintf = 0x40056eb8 ); +PROVIDE ( _vasiprintf_r = 0x40056e80 ); +PROVIDE ( vasniprintf = 0x40056e58 ); +PROVIDE ( _vasniprintf_r = 0x40056df8 ); +PROVIDE ( vasnprintf = 0x40056e58 ); +PROVIDE ( _vasnprintf_r = 0x40056df8 ); +PROVIDE ( vasprintf = 0x40056eb8 ); +PROVIDE ( _vasprintf_r = 0x40056e80 ); +PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 ); +PROVIDE ( veryBigHexP256 = 0x3ff9736c ); +PROVIDE ( vfiprintf = 0x40057ae8 ); +PROVIDE ( _vfiprintf_r = 0x40057850 ); +PROVIDE ( vfiscanf = 0x40057eb8 ); +PROVIDE ( _vfiscanf_r = 0x40057f24 ); +PROVIDE ( vfprintf = 0x40057ae8 ); +PROVIDE ( _vfprintf_r = 0x40057850 ); +PROVIDE ( vfscanf = 0x40057eb8 ); +PROVIDE ( _vfscanf_r = 0x40057f24 ); +PROVIDE ( viprintf = 0x400569b4 ); +PROVIDE ( _viprintf_r = 0x400569e4 ); +PROVIDE ( viscanf = 0x40058698 ); +PROVIDE ( _viscanf_r = 0x400586c8 ); +PROVIDE ( vprintf = 0x400569b4 ); +PROVIDE ( _vprintf_r = 0x400569e4 ); +PROVIDE ( vscanf = 0x40058698 ); +PROVIDE ( _vscanf_r = 0x400586c8 ); +PROVIDE ( vsiprintf = 0x40056ac4 ); +PROVIDE ( _vsiprintf_r = 0x40056a90 ); +PROVIDE ( vsiscanf = 0x40058740 ); +PROVIDE ( _vsiscanf_r = 0x400586f8 ); +PROVIDE ( vsniprintf = 0x40056a68 ); +PROVIDE ( _vsniprintf_r = 0x40056a14 ); +PROVIDE ( vsnprintf = 0x40056a68 ); +PROVIDE ( _vsnprintf_r = 0x40056a14 ); +PROVIDE ( vsprintf = 0x40056ac4 ); +PROVIDE ( _vsprintf_r = 0x40056a90 ); +PROVIDE ( vsscanf = 0x40058740 ); +PROVIDE ( _vsscanf_r = 0x400586f8 ); +PROVIDE ( wcrtomb = 0x40058920 ); +PROVIDE ( _wcrtomb_r = 0x400588d8 ); +PROVIDE ( __wctomb = 0x3ff96540 ); +PROVIDE ( _wctomb_r = 0x40058f14 ); +PROVIDE ( _WindowOverflow12 = 0x40000100 ); +PROVIDE ( _WindowOverflow4 = 0x40000000 ); +PROVIDE ( _WindowOverflow8 = 0x40000080 ); +PROVIDE ( _WindowUnderflow12 = 0x40000140 ); +PROVIDE ( _WindowUnderflow4 = 0x40000040 ); +PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); +PROVIDE ( write = 0x4000181c ); +PROVIDE ( _write_r = 0x4000bd70 ); +PROVIDE ( xthal_bcopy = 0x4000c098 ); +PROVIDE ( xthal_copy123 = 0x4000c124 ); +PROVIDE ( xthal_get_ccompare = 0x4000c078 ); +PROVIDE ( xthal_get_ccount = 0x4000c050 ); +PROVIDE ( xthal_get_interrupt = 0x4000c1e4 ); +PROVIDE ( xthal_get_intread = 0x4000c1e4 ); +PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); +PROVIDE ( xthal_memcpy = 0x4000c0bc ); +PROVIDE ( xthal_set_ccompare = 0x4000c058 ); +PROVIDE ( xthal_set_intclear = 0x4000c1ec ); +PROVIDE ( _xtos_alloca_handler = 0x40000010 ); +PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); +PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 ); +PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 ); +PROVIDE ( _xtos_enabled = 0x3ffe0650 ); +PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 ); +PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 ); +PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 ); +PROVIDE ( _xtos_ints_off = 0x4000bfac ); +PROVIDE ( _xtos_ints_on = 0x4000bf88 ); +PROVIDE ( _xtos_intstruct = 0x3ffe0650 ); +PROVIDE ( _xtos_l1int_handler = 0x40000814 ); +PROVIDE ( _xtos_p_none = 0x4000bfd4 ); +PROVIDE ( _xtos_restore_intlevel = 0x40000928 ); +PROVIDE ( _xtos_return_from_exc = 0x4000c034 ); +PROVIDE ( _xtos_set_exception_handler = 0x4000074c ); +PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 ); +PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 ); +PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); +PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 ); +PROVIDE ( _xtos_set_vpri = 0x40000934 ); +PROVIDE ( _xtos_syscall_handler = 0x40000790 ); +PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); +PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); +PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); diff --git a/configs/esp32-core/src/.gitignore b/configs/esp32-core/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/configs/esp32-core/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile new file mode 100644 index 00000000000..2e23d2db4b6 --- /dev/null +++ b/configs/esp32-core/src/Makefile @@ -0,0 +1,63 @@ +############################################################################ +# configs//srp32-core/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +SCRIPTDIR = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts +CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h + +ASRCS = +CSRCS = esp32_boot.c esp32_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CONFIG_CSRCS += esp32_appinit.c +endif + +SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template +SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32_out.ld + +BOARD_CONTEXT = y +EXTRA_CLEAN = +EXTRA_DISTCLEAN = $(call DELFILE, $(SCRIPTOUT)) + +.PHONY = context + +include $(TOPDIR)/configs/Board.mk + +$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) + # $(call PREPROCESS, $(SCRIPTIN), $@) + $(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@ + +context: $(SCRIPTOUT) diff --git a/configs/esp32-core/src/esp32-core.h b/configs/esp32-core/src/esp32-core.h new file mode 100644 index 00000000000..88e6f9fe79c --- /dev/null +++ b/configs/esp32-core/src/esp32-core.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * configs/esp32-core/src/esp32-core.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H +#define __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via board_app_initialize() + * + ****************************************************************************/ + +int esp32_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H */ diff --git a/configs/esp32-core/src/esp32_appinit.c b/configs/esp32-core/src/esp32_appinit.c new file mode 100644 index 00000000000..b352aa2fd26 --- /dev/null +++ b/configs/esp32-core/src/esp32_appinit.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * config/esp32-core/src/esp32_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32_core.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32_bringup(); +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/esp32-core/src/esp32_boot.c b/configs/esp32-core/src/esp32_boot.c new file mode 100644 index 00000000000..6dfe57a5ed6 --- /dev/null +++ b/configs/esp32-core/src/esp32_boot.c @@ -0,0 +1,95 @@ +/************************************************************************************ + * configs/esp32-core/src/esp32_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "esp32-core.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: esp32_board_initialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void esp32_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)esp32_bringup(); +} +#endif diff --git a/configs/esp32-core/src/esp32_bringup.c b/configs/esp32-core/src/esp32_bringup.c new file mode 100644 index 00000000000..0267217785b --- /dev/null +++ b/configs/esp32-core/src/esp32_bringup.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * config/esp32-core/src/esp32_bringup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "esp32-core.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int esp32_bringup(void) +{ + return OK; +} diff --git a/configs/skp16c26/src/Makefile b/configs/skp16c26/src/Makefile index 8b4f1312c69..a17f9134727 100644 --- a/configs/skp16c26/src/Makefile +++ b/configs/skp16c26/src/Makefile @@ -65,6 +65,8 @@ libboard$(LIBEXT): $(OBJS) depend: .depend +context: + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) diff --git a/tools/sethost.sh b/tools/sethost.sh old mode 100644 new mode 100755