diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 6e4edf93200..a6c7a6a9595 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -132,6 +132,10 @@ ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y) CHIP_CSRCS += sam_spi_slave.c endif +ifeq ($(CONFIG_SAMV7_QSPI),y) +CHIP_CSRCS += sam_qspi.c +endif + ifeq ($(CONFIG_SAMV7_TWIHS0),y) CHIP_CSRCS += sam_twihs.c else ifeq ($(CONFIG_SAMV7_TWIHS1),y) diff --git a/arch/arm/src/samv7/chip/sam_qspi.h b/arch/arm/src/samv7/chip/sam_qspi.h index 704c5e6b485..29d785704e3 100644 --- a/arch/arm/src/samv7/chip/sam_qspi.h +++ b/arch/arm/src/samv7/chip/sam_qspi.h @@ -51,7 +51,12 @@ /**************************************************************************************** * Pre-processor Definitions ****************************************************************************************/ -/* QSPI register offsets *****************************************************************/ +/* General Characteristics **************************************************************/ + +#define SAM_QSPI_MINBITS 8 /* Minimum word width */ +#define SAM_QSPI_MAXBITS 16 /* Maximum word width */ + +/* QSPI register offsets ****************************************************************/ #define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */ #define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */ @@ -73,7 +78,7 @@ #define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ /* 0xec-0xfc: Reserved */ -/* QSPI register addresses ***************************************************************/ +/* QSPI register addresses **************************************************************/ #define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */ #define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */ @@ -111,7 +116,7 @@ # define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */ #endif -/* QSPI register bit definitions *********************************************************/ +/* QSPI register bit definitions ********************************************************/ /* QSPI Control Register */ @@ -132,7 +137,7 @@ # define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_PCS_SHIFT) /* CS deasserted after each transfer */ #define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */ #define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT) -# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-8) << QSPI_MR_NBBITS_SHIFT) +# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-SAM_QSPI_MINBITS) << QSPI_MR_NBBITS_SHIFT) # define QSPI_MR_NBBITS_8BIT (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */ # define QSPI_MR_NBBITS_9BIT (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */ # define QSPI_MR_NBBITS_10BIT (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */ @@ -176,8 +181,6 @@ /* Serial Clock Register */ -#define QSPI_SCR_ - #define QSPI_SCR_CPOL (1 << 0) /* Bit 0: Clock Polarity */ #define QSPI_SCR_NCPHA (1 << 1) /* Bit 1: Clock Phase */ #define QSPI_SCR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c new file mode 100644 index 00000000000..01fb96935e8 --- /dev/null +++ b/arch/arm/src/samv7/sam_qspi.c @@ -0,0 +1,1750 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_qspi.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "sam_gpio.h" +#include "sam_xdmac.h" +#include "sam_periphclks.h" +#include "sam_qspi.h" +#include "chip/sam_pmc.h" +#include "chip/sam_xdmac.h" +#include "chip/sam_qspi.h" +#include "chip/sam_pinmap.h" + +#ifdef CONFIG_SAMV7_QSPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* When QSPI DMA is enabled, small DMA transfers will still be performed by + * polling logic. But we need a threshold value to determine what is small. + * That value is provided by CONFIG_SAMV7_QSPI_DMATHRESHOLD. + */ + +#ifndef CONFIG_SAMV7_QSPI_DMATHRESHOLD +# define CONFIG_SAMV7_QSPI_DMATHRESHOLD 4 +#endif + +#ifdef CONFIG_SAMV7_QSPI_DMA +# if defined(CONFIG_SAMV7_QSPI) && defined(CONFIG_SAMV7_DMAC0) +# define SAMV7_QSPI0_DMA true +# else +# define SAMV7_QSPI0_DMA false +# endif +#endif + +#ifndef CONFIG_SAMV7_QSPI_DMA +# undef CONFIG_SAMV7_QSPI_DMADEBUG +#endif + +/* Clocking *****************************************************************/ +/* The QSPI Baud rate clock is generated by dividing the peripheral clock by + * a value between 1 and 255 + */ + +#define SAM_QSPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ + +/* DMA timeout. The value is not critical; we just don't want the system to + * hang in the event that a DMA does not finish. This is set to + */ + +#define DMA_TIMEOUT_MS (800) +#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS) + +/* Debug *******************************************************************/ +/* Check if QSPI debug is enabled (non-standard.. no support in + * include/debug.h + */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_VERBOSE +# undef CONFIG_DEBUG_SPI +# undef CONFIG_SAMV7_QSPI_DMADEBUG +# undef CONFIG_SAMV7_QSPI_REGDEBUG +#endif + +#ifndef CONFIG_DEBUG_DMA +# undef CONFIG_SAMV7_QSPI_DMADEBUG +#endif + +#ifdef CONFIG_DEBUG_SPI +# define spidbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# define spidbg(x...) +# define spivdbg(x...) +#endif + +#define DMA_INITIAL 0 +#define DMA_AFTER_SETUP 1 +#define DMA_AFTER_START 2 +#define DMA_CALLBACK 3 +#define DMA_TIMEOUT 3 +#define DMA_END_TRANSFER 4 +#define DMA_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The state of the QSPI controller */ + +struct sam_qspidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the QSPI interface */ + + uint32_t base; /* QSPI controller register base address */ +#ifndef CONFIG_SPI_OWNBUS + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t mode; /* Mode 0,1,2,3 */ +#endif + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t intf; /* QSPI controller number (0) */ + bool initialized; /* TRUE: Controller has been initialized */ + sem_t spisem; /* Assures mutually exclusive access to QSPI */ + +#ifdef CONFIG_SAMV7_QSPI_DMA + bool candma; /* DMA is supported */ + sem_t dmawait; /* Used to wait for DMA completion */ + WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */ + int result; /* DMA result */ + DMA_HANDLE rxdma; /* QSPI RX DMA handle */ + DMA_HANDLE txdma; /* QSPI TX DMA handle */ +#endif + +#ifdef CONFIG_SAMV7_QSPI_DMA + uint8_t rxintf; /* RX hardware interface number */ + uint8_t txintf; /* TX hardware interface number */ +#endif + + /* Debug stuff */ + +#ifdef CONFIG_SAMV7_QSPI_DMADEBUG + struct sam_dmaregs_s rxdmaregs[DMA_NSAMPLES]; + struct sam_dmaregs_s txdmaregs[DMA_NSAMPLES]; +#endif + +#ifdef CONFIG_SAMV7_QSPI_REGDEBUG + bool wrlast; /* Last was a write */ + uint32_t addresslast; /* Last address */ + uint32_t valuelast; /* Last value */ + int ntimes; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +#ifdef CONFIG_SAMV7_QSPI_REGDEBUG +static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, + uint32_t value, uint32_t address); +#else +# define qspi_checkreg(priv,wr,value,address) (false) +#endif + +static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, + unsigned int offset); +static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, + unsigned int offset); + +#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE) +static void qspi_dumpregs(struct sam_qspidev_s *priv, const char *msg); +#else +# define qspi_dumpregs(priv,msg) +#endif + +static inline void qspi_flush(struct sam_qspidev_s *priv); + +/* DMA support */ + +#ifdef CONFIG_SAMV7_QSPI_DMA + +#ifdef CONFIG_SAMV7_QSPI_DMADEBUG +# define qspi_rxdma_sample(s,i) sam_dmasample((s)->rxdma, &(s)->rxdmaregs[i]) +# define qspi_txdma_sample(s,i) sam_dmasample((s)->txdma, &(s)->txdmaregs[i]) +static void qspi_dma_sampleinit(struct sam_qspidev_s *priv); +static void qspi_dma_sampledone(struct sam_qspidev_s *priv); + +#else +# define qspi_rxdma_sample(s,i) +# define qspi_txdma_sample(s,i) +# define qspi_dma_sampleinit(s) +# define qspi_dma_sampledone(s) + +#endif + +static void qspi_rxcallback(DMA_HANDLE handle, void *arg, int result); +static void qspi_txcallback(DMA_HANDLE handle, void *arg, int result); +static inline uintptr_t qspi_regaddr(struct sam_qspidev_s *priv, + unsigned int offset); +#endif + +/* QSPI master methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int qspi_lock(struct spi_dev_s *dev, bool lock); +#endif +static void qspi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected); +static uint32_t qspi_setfrequency(struct spi_dev_s *dev, uint32_t frequency); +static void qspi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); +static void qspi_setbits(struct spi_dev_s *dev, int nbits); +static uint8_t qspi_status(struct spi_dev_s *dev, enum spi_dev_e devid); +static uint16_t qspi_send(struct spi_dev_s *dev, uint16_t ch); +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, size_t nwords); +#endif +static void qspi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void qspi_sndblock(struct spi_dev_s *dev, + const void *buffer, size_t nwords); +static void qspi_recvblock(struct spi_dev_s *dev, void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI +/* QSPI0 driver operations */ + +static const struct spi_ops_s g_qspi0ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = qspi_lock, +#endif + .select = qspi_select, + .setfrequency = qspi_setfrequency, + .setmode = qspi_setmode, + .setbits = qspi_setbits, + .status = qspi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = qspi_cmddata, +#endif + .send = qspi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = qspi_exchange, +#else + .sndblock = qspi_sndblock, + .recvblock = qspi_recvblock, +#endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the QSPI0 controller */ + +static struct sam_qspidev_s g_qspi0dev = +{ + .spidev = + { + .ops = &g_qspi0ops, + }, + .base = SAM_QSPI_BASE, + .intf = 0, +#ifdef CONFIG_SAMV7_QSPI_DMA + .candma = SAMV7_QSPI_DMA, + .rxintf = XDMACH_QSPI_RX, + .txintf = XDMACH_QSPI_TX, +#endif +}; +#endif /* CONFIG_SAMV7_QSPI */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: qspi_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * value - The value to be written + * address - The address of the register to write to + * + * Returned Value: + * true: This is the first register access of this type. + * flase: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_REGDEBUG +static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, + uint32_t address) +{ + if (wr == priv->wrlast && /* Same kind of access? */ + value == priv->valuelast && /* Same value? */ + address == priv->addresslast) /* Same address? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + priv->ntimes++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (priv->ntimes > 0) + { + /* Yes... show how many times we did it */ + + lldbg("...[Repeats %d times]...\n", priv->ntimes); + } + + /* Save information about the new access */ + + priv->wrlast = wr; + priv->valuelast = value; + priv->addresslast = address; + priv->ntimes = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif + +/**************************************************************************** + * Name: qspi_getreg + * + * Description: + * Read an QSPI register + * + ****************************************************************************/ + +static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, + unsigned int offset) +{ + uint32_t address = priv->base + offset; + uint32_t value = getreg32(address); + +#ifdef CONFIG_SAMV7_QSPI_REGDEBUG + if (qspi_checkreg(priv, false, value, address)) + { + lldbg("%08x->%08x\n", address, value); + } +#endif + + return value; +} + +/**************************************************************************** + * Name: qspi_putreg + * + * Description: + * Write a value to an QSPI register + * + ****************************************************************************/ + +static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, + unsigned int offset) +{ + uint32_t address = priv->base + offset; + +#ifdef CONFIG_SAMV7_QSPI_REGDEBUG + if (qspi_checkreg(priv, true, value, address)) + { + lldbg("%08x<-%08x\n", address, value); + } +#endif + + putreg32(value, address); +} + +/**************************************************************************** + * Name: qspi_dumpregs + * + * Description: + * Dump the contents of all QSPI registers + * + * Input Parameters: + * priv - The QSPI controller to dump + * msg - Message to print before the register data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE) +static void qspi_dumpregs(struct sam_qspidev_s *priv, const char *msg) +{ + spivdbg("%s:\n", msg); + spivdbg(" MR:%08x SR:%08x IMR:%08x\n", + getreg32(priv->base + SAM_QSPI_MR_OFFSET), + getreg32(priv->base + SAM_QSPI_SR_OFFSET), + getreg32(priv->base + SAM_QSPI_IMR_OFFSET)); + spivdbg(" SCR0:%08x SCR1:%08x SCR2:%08x SCR3:%08x\n", + getreg32(priv->base + SAM_QSPI_SCR0_OFFSET), + getreg32(priv->base + SAM_QSPI_SCR1_OFFSET), + getreg32(priv->base + SAM_QSPI_SCR2_OFFSET), + getreg32(priv->base + SAM_QSPI_SCR3_OFFSET)); + spivdbg(" WPCR:%08x WPSR:%08x\n", + getreg32(priv->base + SAM_QSPI_WPCR_OFFSET), + getreg32(priv->base + SAM_QSPI_WPSR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: qspi_flush + * + * Description: + * Make sure that there are now dangling QSPI transfer in progress + * + * Input Parameters: + * priv - QSPI controller state + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void qspi_flush(struct sam_qspidev_s *priv) +{ + /* Make sure the no TX activity is in progress... waiting if necessary */ + + while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_TXEMPTY) == 0); + + /* Then make sure that there is no pending RX data .. reading as + * discarding as necessary. + */ + + while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_RDRF) != 0) + { + (void)qspi_getreg(priv, SAM_QSPI_RDR_OFFSET); + } +} + +/**************************************************************************** + * Name: qspi_dma_sampleinit + * + * Description: + * Initialize sampling of DMA registers (if CONFIG_SAMV7_QSPI_DMADEBUG) + * + * Input Parameters: + * priv - QSPI driver instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMADEBUG +static void qspi_dma_sampleinit(struct sam_qspidev_s *priv) +{ + /* Put contents of register samples into a known state */ + + memset(priv->rxdmaregs, 0xff, DMA_NSAMPLES * sizeof(struct sam_dmaregs_s)); + memset(priv->txdmaregs, 0xff, DMA_NSAMPLES * sizeof(struct sam_dmaregs_s)); + + /* Then get the initial samples */ + + sam_dmasample(priv->rxdma, &priv->rxdmaregs[DMA_INITIAL]); + sam_dmasample(priv->txdma, &priv->txdmaregs[DMA_INITIAL]); +} +#endif + +/**************************************************************************** + * Name: qspi_dma_sampledone + * + * Description: + * Dump sampled DMA registers + * + * Input Parameters: + * priv - QSPI driver instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMADEBUG +static void qspi_dma_sampledone(struct sam_qspidev_s *priv) +{ + /* Sample the final registers */ + + sam_dmasample(priv->rxdma, &priv->rxdmaregs[DMA_END_TRANSFER]); + sam_dmasample(priv->txdma, &priv->txdmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + /* Initial register values */ + + sam_dmadump(priv->txdma, &priv->txdmaregs[DMA_INITIAL], + "TX: Initial Registers"); + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_INITIAL], + "RX: Initial Registers"); + + /* Register values after DMA setup */ + + sam_dmadump(priv->txdma, &priv->txdmaregs[DMA_AFTER_SETUP], + "TX: After DMA Setup"); + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_AFTER_SETUP], + "RX: After DMA Setup"); + + /* Register values after DMA start */ + + sam_dmadump(priv->txdma, &priv->txdmaregs[DMA_AFTER_START], + "TX: After DMA Start"); + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_AFTER_START], + "RX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + * + * If the DMA timed out, then there will not be any RX DMA + * callback samples. There is probably no TX DMA callback + * samples either, but we don't know for sure. + */ + + sam_dmadump(priv->txdma, &priv->txdmaregs[DMA_CALLBACK], + "TX: At DMA callback"); + + /* Register values at the end of the DMA */ + + if (priv->result == -ETIMEDOUT) + { + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_TIMEOUT], + "RX: At DMA timeout"); + } + else + { + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_CALLBACK], + "RX: At DMA callback"); + } + + sam_dmadump(priv->txdma, &priv->txdmaregs[DMA_END_TRANSFER], + "TX: At End-of-Transfer"); + sam_dmadump(priv->rxdma, &priv->rxdmaregs[DMA_END_TRANSFER], + "RX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: qspi_dmatimeout + * + * Description: + * The watchdog timeout setup when a has expired without completion of a + * DMA. + * + * Input Parameters: + * argc - The number of arguments (should be 1) + * arg - The argument (state structure reference cast to uint32_t) + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_dmatimeout(int argc, uint32_t arg) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Sample DMA registers at the time of the timeout */ + + qspi_rxdma_sample(priv, DMA_CALLBACK); + + /* Report timeout result, perhaps overwriting any failure reports from + * the TX callback. + */ + + priv->result = -ETIMEDOUT; + + /* Then wake up the waiting thread */ + + sem_post(&priv->dmawait); +} +#endif + +/**************************************************************************** + * Name: qspi_rxcallback + * + * Description: + * This callback function is invoked at the completion of the QSPI RX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select structure + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_rxcallback(DMA_HANDLE handle, void *arg, int result) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(priv->dmadog); + + /* Sample DMA registers at the time of the callback */ + + qspi_rxdma_sample(priv, DMA_CALLBACK); + + /* Report the result of the transfer only if the TX callback has not already + * reported an error. + */ + + if (priv->result == -EBUSY) + { + /* Save the result of the transfer if no error was previously reported */ + + priv->result = result; + } + + /* Then wake up the waiting thread */ + + sem_post(&priv->dmawait); +} +#endif + +/**************************************************************************** + * Name: qspi_txcallback + * + * Description: + * This callback function is invoked at the completion of the QSPI TX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select structure + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_txcallback(DMA_HANDLE handle, void *arg, int result) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)arg; + DEBUGASSERT(priv != NULL); + + qspi_txdma_sample(priv, DMA_CALLBACK); + + /* Do nothing on the TX callback unless an error is reported. This + * callback is not really important because the QSPI exchange is not + * complete until the RX callback is received. + */ + + if (result != OK && priv->result == -EBUSY) + { + /* Save the result of the transfer if an error is reported */ + + priv->result = result; + } +} +#endif + +/**************************************************************************** + * Name: qspi_regaddr + * + * Description: + * Return the address of an QSPI register + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMA +static inline uintptr_t qspi_regaddr(struct sam_qspidev_s *priv, + unsigned int offset) +{ + return priv->base + offset; +} +#endif + +/**************************************************************************** + * Name: qspi_lock + * + * Description: + * On QSPI buses where there are multiple devices, it will be necessary to + * lock QSPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the QSPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the QSPI is properly + * configured for the device. If the QSPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock QSPI bus, false: unlock QSPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int qspi_lock(struct spi_dev_s *dev, bool lock) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + + spivdbg("lock=%d\n", lock); + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->spisem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->spisem); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: qspi_select + * + * Description: + * This function does not actually set the chip select line. Rather, it + * simply maps the device ID into a chip select number and retains that + * chip select number for later use. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The QSPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + + static void qspi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected) + { + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + + /* Are we selecting or de-selecting the device? */ + + spivdbg("selected=%d\n", selected); + if (selected) + { +#warning Missing logic + } + else + { +#warning Missing logic + } +} + +/**************************************************************************** + * Name: qspi_setfrequency + * + * Description: + * Set the QSPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The QSPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t qspi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + uint32_t actual; + uint32_t scbr; + uint32_t dlybs; + uint32_t dlybct; + uint32_t regval; + + spivdbg("frequency=%d\n", frequency); + + /* Check if the requested frequency is the same as the frequency selection */ + +#ifndef CONFIG_SPI_OWNBUS + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } +#endif + + /* Configure QSPI to a frequency as close as possible to the requested frequency. + * + * SPCK frequency = QSPI_CLK / SCBR, or SCBR = QSPI_CLK / frequency + */ + + scbr = SAM_QSPI_CLOCK / frequency; + + if (scbr < 8) + { + scbr = 8; + } + else if (scbr > 254) + { + scbr = 254; + } + + scbr = (scbr + 1) & ~1; + + /* Save the new scbr value */ + + regval = qspi_getreg(priv, SAM_QSPI_SCR_OFFSET); + regval &= ~(QSPI_SCR_SCBR_MASK | QSPI_SCR_DLYBS_MASK); + regval |= scbr << QSPI_SCR_SCBR_SHIFT; + + /* DLYBS: Delay Before SPCK. This field defines the delay from NPCS valid to the + * first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK + * transition is 1/2 the SPCK clock period. Otherwise, the following equations + * determine the delay: + * + * Delay Before SPCK = DLYBS / QSPI_CLK + * + * For a 2uS delay + * + * DLYBS = QSPI_CLK * 0.000002 = QSPI_CLK / 500000 + */ + + dlybs = SAM_QSPI_CLOCK / 500000; + regval |= dlybs << QSPI_SCR_DLYBS_SHIFT; + qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET); + + /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay + * between two consecutive transfers with the same peripheral without removing + * the chip select. The delay is always inserted after each transfer and + * before removing the chip select if needed. + * + * Delay Between Consecutive Transfers = (32 x DLYBCT) / QSPI_CLK + * + * For a 5uS delay: + * + * DLYBCT = QSPI_CLK * 0.000005 / 32 = QSPI_CLK / 200000 / 32 + */ + + dlybct = SAM_QSPI_CLOCK / 200000 / 32; + + regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); + regval &= ~QSPI_MR_DLYBCT_MASK; + regval |= dlybct << QSPI_MR_DLYBCT_SHIFT; + qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); + + /* Calculate the new actual frequency */ + + actual = SAM_QSPI_CLOCK / scbr; + spivdbg("SCR=%08x actual=%d\n", regval, actual); + + /* Save the frequency setting */ + +#ifndef CONFIG_SPI_OWNBUS + priv->frequency = frequency; + priv->actual = actual; +#endif + + spidbg("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/**************************************************************************** + * Name: qspi_setmode + * + * Description: + * Set the QSPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The QSPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void qspi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + uint32_t regval; + + spivdbg("mode=%d\n", mode); + + /* Has the mode changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != priv->mode) + { +#endif + /* Yes... Set the mode appropriately: + * + * QSPI CPOL NCPHA + * MODE + * 0 0 1 + * 1 0 0 + * 2 1 1 + * 3 1 0 + */ + + regval = qspi_getreg(priv, SAM_QSPI_SCR_OFFSET); + regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_NCPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; NCPHA=1 */ + regval |= QSPI_SCR_NCPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; NCPHA=0 */ + break; + + case SPIDEV_MODE2: /* CPOL=1; NCPHA=1 */ + regval |= (QSPI_SCR_CPOL | QSPI_SCR_NCPHA); + break; + + case SPIDEV_MODE3: /* CPOL=1; NCPHA=0 */ + regval |= QSPI_SCR_CPOL; + break; + + default: + DEBUGASSERT(FALSE); + return; + } + + qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET); + spivdbg("SCR=%08x\n", regval); + + /* Save the mode so that subsequent re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + priv->mode = mode; + } +#endif +} + +/**************************************************************************** + * Name: qspi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void qspi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + uint32_t regval; + + spivdbg("nbits=%d\n", nbits); + DEBUGASSERT(priv != NULL); + DEBUGASSERT(nbits >= SAM_QSPI_MINBITS && nbits <= SAM_QSPI_MAXBITS); + + /* Has the number of bits changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (nbits != priv->nbits) +#endif + { + /* Yes... Set number of bits appropriately */ + + regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); + regval &= ~QSPI_MR_NBBITS_MASK; + regval |= QSPI_MR_NBBITS(nbits); + qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); + + spivdbg("SCR%02x]=%08x\n", regval); + + /* Save the selection so the subsequence re-configurations will be faster */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: qspi_status + * + * Description: + * Return status information associated with the QSPI device. + * + * Input Parameters: + * dev - SPI device info + * devid - Identifies the (logical) device + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h. + * + ****************************************************************************/ + +uint8_t qspi_status(struct spi_dev_s *dev, enum spi_dev_e devid) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: qspi_send + * + * Description: + * Exchange one word on QSPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the QSPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t qspi_send(struct spi_dev_s *dev, uint16_t wd) +{ + uint8_t txbyte; + uint8_t rxbyte; + + /* qspi_exchange can do this. Note: right now, this only deals with 8-bit + * words. If the QSPI interface were configured for words of other sizes, + * this would fail. + */ + + txbyte = (uint8_t)wd; + rxbyte = (uint8_t)0; + qspi_exchange(dev, &txbyte, &rxbyte, 1); + + spivdbg("Sent %02x received %02x\n", txbyte, rxbyte); + return (uint16_t)rxbyte; +} + +/**************************************************************************** + * Name: qspi_exchange (and qspi_exchange_nodma) + * + * Description: + * Exchange a block of data from QSPI. There are two versions of this + * function: (1) One that is enabled only when CONFIG_SAMV7_QSPI_DMA=y + * that performs DMA QSPI transfers, but only when a larger block of + * data is being transferred. And (2) another version that does polled + * QSPI transfers. When CONFIG_SAMV7_QSPI_DMA=n the latter is the only + * version avaialable; when CONFIG_SAMV7_QSPI_DMA=y, this version is only + * used for short QSPI transfers and gets renamed as qspi_exchange_nodma). + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the QSPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_exchange_nodma(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#else +static void qspi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#endif +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + uint32_t data; + uint16_t *rxptr16; + uint16_t *txptr16; + uint8_t *rxptr8; + uint8_t *txptr8; + + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* Set up working pointers */ + + if (priv->nbits > 8) + { + rxptr16 = (uint16_t*)rxbuffer; + txptr16 = (uint16_t*)txbuffer; + rxptr8 = NULL; + txptr8 = NULL; + } + else + { + rxptr16 = NULL; + txptr16 = NULL; + rxptr8 = (uint8_t*)rxbuffer; + txptr8 = (uint8_t*)txbuffer; + } + + /* Make sure that any previous transfer is flushed from the hardware */ + + qspi_flush(priv); + + /* Loop, sending each word in the user-provided data buffer. + * + * Note 1: Good QSPI performance would require that we implement DMA + * transfers! + * Note 2: This loop might be made more efficient. Would logic + * like the following improve the throughput? Or would it + * just add the risk of overruns? + * + * Get word 1; + * Send word 1; Now word 1 is "in flight" + * nwords--; + * for ( ; nwords > 0; nwords--) + * { + * Get word N. + * Wait for TDRE meaning that word N-1 has moved to the shift + * register. + * Disable interrupts to keep the following atomic + * Send word N. Now both work N-1 and N are "in flight" + * Wait for RDRF meaning that word N-1 is available + * Read word N-1. + * Re-enable interrupts. + * Save word N-1. + * } + * Wait for RDRF meaning that the final word is available + * Read the final word. + * Save the final word. + */ + + for ( ; nwords > 0; nwords--) + { + /* Get the data to send (0xff if there is no data source). */ + + if (txptr8) + { + data = (uint32_t)*txptr8++; + } + else if (txptr16) + { + data = (uint32_t)*txptr16++; + } + else + { + data = 0xffff; + } + + /* Do we need to set the LASTXFER bit in the TDR value too? */ + +#ifdef CONFIG_SPI_VARSELECT + if (nwords == 1) + { + data |= QSPI_TDR_LASTXFER; + } +#endif + + /* Wait for any previous data written to the TDR to be transferred + * to the serializer. + */ + + while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_TDRE) == 0); + + /* Write the data to transmitted to the Transmit Data Register (TDR) */ + + qspi_putreg(priv, data, SAM_QSPI_TDR_OFFSET); + + /* Wait for the read data to be available in the RDR. + * TODO: Data transfer rates would be improved using the RX FIFO + * (and also DMA) + */ + + while ((qspi_getreg(priv, SAM_QSPI_SR_OFFSET) & QSPI_INT_RDRF) == 0); + + /* Read the received data from the QSPI Data Register. */ + + data = qspi_getreg(priv, SAM_QSPI_RDR_OFFSET); + if (rxptr8) + { + *rxptr8++ = (uint8_t)data; + } + else if (rxptr16) + { + *rxptr16++ = (uint16_t)data; + } + } +} + +#ifdef CONFIG_SAMV7_QSPI_DMA +static void qspi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct sam_qspidev_s *priv = (struct sam_qspidev_s *)dev; + uint32_t rxflags; + uint32_t txflags; + uint32_t txdummy; + uint32_t rxdummy; + uint32_t regaddr; + uint32_t memaddr; + uint32_t width; + size_t nbytes; + int ret; + + /* Convert the number of word to a number of bytes */ + + nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; + + /* If we cannot do DMA -OR- if this is a small QSPI transfer, then let + * qspi_exchange_nodma() do the work. + */ + + if (!priv->candma || nbytes <= CONFIG_SAMV7_QSPI_DMATHRESHOLD) + { + qspi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + priv = (struct sam_qspidev_s *)dev; + DEBUGASSERT(priv); + + /* Make sure that any previous transfer is flushed from the hardware */ + + qspi_flush(priv); + + /* Sample initial DMA registers */ + + qspi_dma_sampleinit(priv); + + /* Select the source and destination width bits */ + + if (priv->nbits > 8) + { + width = (DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_MEMWIDTH_16BITS); + } + else + { + width = (DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_MEMWIDTH_8BITS); + } + + /* Configure the DMA channels. There are four different cases: + * + * 1) A true exchange with the memory address incrementing on both + * RX and TX channels, + * 2) A read operation with the memory address incrementing only on + * the receive channel, + * 3) A write operation where the memory address increments only on + * the receive channel, and + * 4) A corner case where there the memory address does not increment + * on either channel. This case might be used in certain cases + * where you want to assure that certain number of clocks are + * provided on the QSPI bus. + */ + + /* Configure the RX DMA channel */ + + rxflags = DMACH_FLAG_FIFOCFG_LARGEST | + ((uint32_t)priv->rxintf << DMACH_FLAG_PERIPHPID_SHIFT) | + DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | + DMACH_FLAG_PERIPHCHUNKSIZE_1 | + ((uint32_t)(15) << DMACH_FLAG_MEMPID_SHIFT) | + DMACH_FLAG_MEMCHUNKSIZE_1; + + /* Set the source and destination width bits */ + + rxflags |= width; + + /* Handle the case where there is no sink buffer */ + + if (!rxbuffer) + { + /* No sink data buffer. Point to our dummy buffer and leave + * the rxflags so that no address increment is performed. + */ + + rxbuffer = (void *)&rxdummy; + } + else + { + /* A receive buffer is available. + * + * Invalidate the RX buffer memory to force re-fetching from RAM when + * the DMA completes + */ + + sam_cmcc_invalidate((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); + + /* Use normal RX memory incrementing. */ + + rxflags |= DMACH_FLAG_MEMINCREMENT; + } + + /* Configure the TX DMA channel */ + + txflags = DMACH_FLAG_FIFOCFG_LARGEST | + ((uint32_t)priv->txintf << DMACH_FLAG_PERIPHPID_SHIFT) | + DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | + DMACH_FLAG_PERIPHCHUNKSIZE_1 | + ((uint32_t)(15) << DMACH_FLAG_MEMPID_SHIFT) | + DMACH_FLAG_MEMCHUNKSIZE_1; + + /* Set the source and destination width bits */ + + txflags |= width; + + /* Handle the case where there is no source buffer */ + + if (!txbuffer) + { + /* No source data buffer. Point to our dummy buffer and leave + * the txflags so that no address increment is performed. + */ + + txdummy = 0xffffffff; + txbuffer = (const void *)&txdummy; + } + else + { + /* Source data is available. Use normal TX memory incrementing. */ + + txflags |= DMACH_FLAG_MEMINCREMENT; + } + + /* Then configure the DMA channels to make it so */ + + sam_dmaconfig(priv->rxdma, rxflags); + sam_dmaconfig(priv->txdma, txflags); + + /* Configure the RX side of the exchange transfer */ + + regaddr = qspi_regaddr(priv, SAM_QSPI_RDR_OFFSET); + memaddr = (uintptr_t)rxbuffer; + + ret = sam_dmarxsetup(priv->rxdma, regaddr, memaddr, nwords); + if (ret < 0) + { + dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret); + return; + } + + qspi_rxdma_sample(priv, DMA_AFTER_SETUP); + + /* Configure the TX side of the exchange transfer */ + + regaddr = qspi_regaddr(priv, SAM_QSPI_TDR_OFFSET); + memaddr = (uintptr_t)txbuffer; + + ret = sam_dmatxsetup(priv->txdma, regaddr, memaddr, nwords); + if (ret < 0) + { + dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret); + return; + } + + qspi_txdma_sample(priv, DMA_AFTER_SETUP); + + /* Start the DMA transfer */ + + priv->result = -EBUSY; + ret = sam_dmastart(priv->rxdma, qspi_rxcallback, (void *)priv); + if (ret < 0) + { + dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret); + return; + } + + qspi_rxdma_sample(priv, DMA_AFTER_START); + + ret = sam_dmastart(priv->txdma, qspi_txcallback, (void *)priv); + if (ret < 0) + { + dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret); + sam_dmastop(priv->rxdma); + return; + } + + qspi_txdma_sample(priv, DMA_AFTER_START); + + /* Wait for DMA completion. This is done in a loop because there may be + * false alarm semaphore counts that cause sam_wait() not fail to wait + * or to wake-up prematurely (for example due to the receipt of a signal). + * We know that the DMA has completed when the result is anything other + * that -EBUSY. + */ + + do + { + /* Start (or re-start) the watchdog timeout */ + + ret = wd_start(priv->dmadog, DMA_TIMEOUT_TICKS, + (wdentry_t)qspi_dmatimeout, 1, (uint32_t)priv); + if (ret != OK) + { + spidbg("ERROR: wd_start failed: %d\n", ret); + } + + /* Wait for the DMA complete */ + + ret = sem_wait(&priv->dmawait); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(priv->dmadog); + + /* Check if we were awakened by an error of some kind */ + + if (ret < 0) + { + /* EINTR is not a failure. That simply means that the wait + * was awakened by a signal. + */ + + int errorcode = errno; + if (errorcode != EINTR) + { + DEBUGPANIC(); + return; + } + } + + /* Not that we might be awakened before the wait is over due to + * residual counts on the semaphore. So, to handle, that case, + * we loop until something changes the DMA result to any value other + * than -EBUSY. + */ + } + while (priv->result == -EBUSY); + + /* Dump the sampled DMA registers */ + + qspi_dma_sampledone(priv); + + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer terminates + * on an error condition). + */ + + sam_dmastop(priv->rxdma); + sam_dmastop(priv->txdma); + + /* All we can do is complain if the DMA fails */ + + if (priv->result) + { + spidbg("ERROR: DMA failed with result: %d\n", priv->result); + } +} +#endif /* CONFIG_SAMV7_QSPI_DMA */ + +/*************************************************************************** + * Name: qspi_sndblock + * + * Description: + * Send a block of data on QSPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the QSPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void qspi_sndblock(struct spi_dev_s *dev, const void *buffer, + size_t nwords) +{ + /* qspi_exchange can do this. */ + + qspi_exchange(dev, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: qspi_recvblock + * + * Description: + * Revice a block of data from QSPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the QSPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void qspi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords) +{ + /* qspi_exchange can do this. */ + + qspi_exchange(dev, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_qspi_initialize + * + * Description: + * Initialize the selected QSPI port in master mode + * + * Input Parameter: + * intf - Interface number(must be zero) + * + * Returned Value: + * Valid QSPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *sam_qspi_initialize(int intf) +{ + FAR struct sam_qspidev_s *priv; + irqstate_t flags; +#ifndef CONFIG_SPI_OWNBUS + uint32_t regval; +#endif + + /* The support SAM parts have only a single QSPI port */ + + spivdbg("intf: %d\n", intf); + DEBUGASSERT(intf >= 0 && intf < SAMV7_NQSPI); + + /* Select the QSPI interface */ + +#ifdef CONFIG_SAMV7_QSPI + if (intf == 0) + { + /* Select QSPI0 */ + + priv = &g_qspi0dev; + + /* Enable clocking to the QSPI peripheral */ + + sam_qspi_enableclk(); + + /* Configure multiplexed pins as connected on the board. */ + + sam_configgpio(GPIO_QSPI_CS); + sam_configgpio(GPIO_QSPI_IO0); + sam_configgpio(GPIO_QSPI_IO1); + sam_configgpio(GPIO_QSPI_IO2); + sam_configgpio(GPIO_QSPI_IO3); + sam_configgpio(GPIO_QSPI_SCK); + } + else +#endif + { + spidbg("ERROR: QSPI%d not supported\n", intf); + return NULL; + } + +#ifdef CONFIG_SAMV7_QSPI_DMA + /* Pre-allocate DMA channels. These allocations exploit that fact that + * QSPI0 is managed by DMAC0 and QSPI1 is managed by DMAC1. Hence, + * the QSPI number (intf) is the same as the DMAC number. + */ + + if (priv->candma) + { + priv->rxdma = sam_dmachannel(0); + if (!priv->rxdma) + { + spidbg("ERROR: Failed to allocate the RX DMA channel\n"); + priv->candma = false; + } + } + + if (priv->candma) + { + priv->txdma = sam_dmachannel(0); + if (!priv->txdma) + { + spidbg("ERROR: Failed to allocate the TX DMA channel\n"); + sam_dmafree(priv->rxdma); + priv->rxdma = NULL; + priv->candma = false; + } + } +#endif + + /* Has the QSPI hardware been initialized? */ + + if (!priv->initialized) + { + /* Enable clocking to the QSPI block */ + + flags = irqsave(); +#if defined(CONFIG_SAMV7_QSPI) && defined(CONFIG_SAMV7_QSPI1_MASTER) + if (intf == 0) +#endif + /* Disable QSPI clocking */ + + qspi_putreg(priv, QSPI_CR_QSPIDIS, SAM_QSPI_CR_OFFSET); + + /* Execute a software reset of the QSPI (twice) */ + + qspi_putreg(priv, QSPI_CR_SWRST, SAM_QSPI_CR_OFFSET); + qspi_putreg(priv, QSPI_CR_SWRST, SAM_QSPI_CR_OFFSET); + irqrestore(flags); + + /* Configure the QSPI mode register */ +#warning Missing Logic + + /* And enable the QSPI */ + + qspi_putreg(priv, QSPI_CR_QSPIEN, SAM_QSPI_CR_OFFSET); + up_mdelay(20); + + /* Flush any pending transfers */ + + (void)qspi_getreg(priv, SAM_QSPI_SR_OFFSET); + (void)qspi_getreg(priv, SAM_QSPI_RDR_OFFSET); + +#ifndef CONFIG_SPI_OWNBUS + /* Initialize the QSPI semaphore that enforces mutually exclusive + * access to the QSPI registers. + */ + + sem_init(&priv->spisem, 0, 1); + priv->initialized = true; +#endif + +#ifdef CONFIG_SAMV7_QSPI_DMA + /* Initialize the QSPI semaphore that is used to wake up the waiting + * thread when the DMA transfer completes. + */ + + sem_init(&priv->dmawait, 0, 0); + + /* Create a watchdog time to catch DMA timeouts */ + + priv->dmadog = wd_create(); + DEBUGASSERT(priv->dmadog); +#endif + + qspi_dumpregs(priv, "After initialization"); + } + +#ifndef CONFIG_SPI_OWNBUS + /* Set to mode=0 and nbits=8 and impossible frequency. It is only + * critical to do this if CONFIG_SPI_OWNBUS is not defined because in + * that case, the QSPI will only be reconfigured if there is a change. + */ + + regval = qspi_getreg(priv, SAM_QSPI_SCR_OFFSET); + regval &= ~QSPI_SCR_CPOL; + regval |= QSPI_SCR_NCPHA; + qspi_putreg(priv, regval, SAM_QSPI_SCR_OFFSET); + + regval = qspi_getreg(priv, SAM_QSPI_MR_OFFSET); + regval &= ~QSPI_MR_NBBITS_MASK; + regval |= QSPI_MR_NBBITS_8BIT; + qspi_putreg(priv, regval, SAM_QSPI_MR_OFFSET); + + priv->nbits = 8; + spivdbg("SCR=%08x\n", regval); +#endif + + return &priv->spidev; +} +#endif /* CONFIG_SAMV7_QSPI */ diff --git a/arch/arm/src/samv7/sam_qspi.h b/arch/arm/src/samv7/sam_qspi.h new file mode 100644 index 00000000000..7888c5dde1b --- /dev/null +++ b/arch/arm/src/samv7/sam_qspi.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_qspi.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H +#define __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "sam_config.h" + +#ifdef CONFIG_SAMV7_QSPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_qspi_initialize + * + * Description: + * Initialize the selected QSPI port in master mode + * + * Input Parameter: + * intf - Interface number(must be zero) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *sam_qspi_initialize(int intf); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_SAMV7_QSPI */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_QSPI_H */