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tools: replace DEFINE script to Makefile variable

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In the past, predefined macros were generated by define.sh scripts
Now they are generated by concatenating environment variables

In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
This commit is contained in:
yinshengkai
2022-11-01 21:47:53 +08:00
committed by Xiang Xiao
parent cdeddcb028
commit 95d9abcf58
6 changed files with 14 additions and 12 deletions
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tools/Config.mk
+5 -4
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@@ -106,7 +106,7 @@ endif
# This define is passed as EXTRAFLAGS for kernel-mode builds. It is also passed
# during PASS1 (but not PASS2) context and depend targets.
KDEFINE ?= ${shell $(DEFINE) "$(CC)" __KERNEL__}
KDEFINE ?= ${DEFINE_PREFIX}__KERNEL__
# DELIM - Path segment delimiter character
#
@@ -577,11 +577,12 @@ $(1)_$(2):
endef
# ARCHxxx means the predefined setting(either toolchain, arch, or system specific)
export DEFINE_PREFIX := $(subst X,,${shell $(DEFINE) "$(CC)" "X"})
ARCHDEFINES += ${shell $(DEFINE) "$(CC)" __NuttX__}
# ARCHxxx means the predefined setting(either toolchain, arch, or system specific)
ARCHDEFINES += ${DEFINE_PREFIX}__NuttX__
ifeq ($(CONFIG_NDEBUG),y)
ARCHDEFINES += ${shell $(DEFINE) "$(CC)" NDEBUG}
ARCHDEFINES += ${DEFINE_PREFIX}NDEBUG
endif
# The default C/C++ search path