diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h
index 51cf921f112..08f6ebde901 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_tim.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h
@@ -719,6 +719,7 @@
 #define ATIM_CCER_CC5P            (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
 #define ATIM_CCER_CC6E            (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
 #define ATIM_CCER_CC6P            (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
+#define ATIM_CCER_CCXBASE(ch)     (ch << 2) /* Each channel uses 4-bits */
 
 /* 16-bit counter register */
 
@@ -1111,6 +1112,7 @@
 #define GTIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
 #define GTIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
 #define GTIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
+#define GTIM_CCER_CCXBASE(ch)     (ch << 2) /* Each channel uses 4-bits */
 
 /* 16-bit counter register */
 
diff --git a/arch/arm/src/stm32h7/stm32_tickless.c b/arch/arm/src/stm32h7/stm32_tickless.c
index 8679cc82117..df3083cae2e 100644
--- a/arch/arm/src/stm32h7/stm32_tickless.c
+++ b/arch/arm/src/stm32h7/stm32_tickless.c
@@ -93,13 +93,13 @@
 #endif
 
 #if CONFIG_STM32H7_TICKLESS_CHANNEL == 1
-#define DIER_CAPT_IE          ATIM_DIER_CC1IE
+#define DIER_CAPT_IE          GTIM_DIER_CC1IE
 #elif CONFIG_STM32H7_TICKLESS_CHANNEL == 2
-#define DIER_CAPT_IE          ATIM_DIER_CC2IE
+#define DIER_CAPT_IE          GTIM_DIER_CC2IE
 #elif CONFIG_STM32H7_TICKLESS_CHANNEL == 3
-#define DIER_CAPT_IE          ATIM_DIER_CC3IE
+#define DIER_CAPT_IE          GTIM_DIER_CC3IE
 #elif CONFIG_STM32H7_TICKLESS_CHANNEL == 4
-#define DIER_CAPT_IE          ATIM_DIER_CC4IE
+#define DIER_CAPT_IE          GTIM_DIER_CC4IE
 #endif
 
 /****************************************************************************
@@ -231,7 +231,8 @@ static int stm32_tickless_setchannel(uint8_t channel)
 
   /* Assume that channel is disabled and polarity is active high */
 
-  ccer_val &= ~(3 << (channel << 2));
+  ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
+                GTIM_CCER_CCXBASE(channel));
 
   /* This function is not supported on basic timers. To enable or
    * disable it, simply set its clock to valid frequency or zero.
@@ -247,11 +248,11 @@ static int stm32_tickless_setchannel(uint8_t channel)
    * disabled.
    */
 
-  ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
+  ccmr_val = (GTIM_CCMR_MODE_FRZN << GTIM_CCMR1_OC1M_SHIFT);
 
   /* Set polarity */
 
-  ccer_val |= ATIM_CCER_CC1P << (channel << 2);
+  ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
 
   /* Define its position (shift) and get register offset */
 
@@ -334,7 +335,7 @@ static void stm32_timing_handler(void)
 {
   g_tickless.overflow++;
 
-  STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF);
+  STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF);
 }
 
 /****************************************************************************
@@ -356,7 +357,7 @@ static int stm32_tickless_handler(int irq, void *context, void *arg)
 {
   int interrupt_flags = stm32_tickless_getint();
 
-  if (interrupt_flags & ATIM_SR_UIF)
+  if (interrupt_flags & GTIM_SR_UIF)
     {
       stm32_timing_handler();
     }
@@ -678,7 +679,7 @@ int up_timer_gettime(FAR struct timespec *ts)
 
   overflow = g_tickless.overflow;
   counter  = STM32_TIM_GETCOUNTER(g_tickless.tch);
-  pending  = STM32_TIM_CHECKINT(g_tickless.tch, ATIM_SR_UIF);
+  pending  = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF);
   verify   = STM32_TIM_GETCOUNTER(g_tickless.tch);
 
   /* If an interrupt was pending before we re-enabled interrupts,
@@ -687,7 +688,7 @@ int up_timer_gettime(FAR struct timespec *ts)
 
   if (pending)
     {
-      STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF);
+      STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF);
 
       /* Increment the overflow count and use the value of the
        * guaranteed to be AFTER the overflow occurred.
diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c
index 03ffa3997fc..8369b182fa5 100644
--- a/arch/arm/src/stm32h7/stm32_tim.c
+++ b/arch/arm/src/stm32h7/stm32_tim.c
@@ -939,7 +939,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
 
   /* Assume that channel is disabled and polarity is active high */
 
-  ccer_val &= ~(3 << (channel << 2));
+  ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel));
 
   /* This function is not supported on basic timers. To enable or
    * disable it, simply set its clock to valid frequency or zero.
@@ -960,13 +960,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
 
       case STM32_TIM_CH_OUTTOGGLE:
         ccmr_val  = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT);
-        ccer_val |= GTIM_CCER_CC1E << (channel << 2);
+        ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
         break;
 
       case STM32_TIM_CH_OUTPWM:
         ccmr_val  = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) +
                     GTIM_CCMR1_OC1PE;
-        ccer_val |= GTIM_CCER_CC1E << (channel << 2);
+        ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
         break;
 
       default:
@@ -977,7 +977,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
 
   if (mode & STM32_TIM_CH_POLARITY_NEG)
     {
-      ccer_val |= GTIM_CCER_CC1P << (channel << 2);
+      ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
     }
 
   /* Define its position (shift) and get register offset */