From adbacfc42ce986a06a63f0a9b7aab6ed37d48b0b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 07:07:33 -0600 Subject: [PATCH 1/4] Xtensa ESP32: Fix a duplicate in Kconfig files. Level 1 should return via RFE. --- arch/xtensa/Kconfig | 4 ++++ arch/xtensa/src/common/xtensa_context.S | 7 +++++- arch/xtensa/src/common/xtensa_int_handlers.S | 7 +++--- arch/xtensa/src/common/xtensa_user_handler.S | 6 ++--- arch/xtensa/src/lx6/Kconfig | 23 -------------------- 5 files changed, 17 insertions(+), 30 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 5c051980e68..b00d8f0d235 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -22,6 +22,10 @@ config ARCH_CHIP_ESP32 of two CPUs is symmetric, meaning they use the same addresses to access the same memory. + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + endchoice # XTENSA chip selection config ARCH_FAMILY_LX6 diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index bbe68ede204..f927f99c051 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -371,10 +371,15 @@ xtensa_context_restore: l32i a0, a2, (4 * REG_PS) /* Restore PS */ wsr a0, PS l32i a0, a2, (4 * REG_PC) /* Set up for RFE */ - rsr a0, EPC + rsr a0, EPC_1 l32i a0, a2, (4 * REG_A0) /* Restore a0 */ l32i a2, a2, (4 * REG_A2) /* Restore A2 */ + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. + */ + rfe /* And return from "exception" */ .size xtensa_context_restore, . - xtensa_context_restore diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 5b59ac8774a..a7d12e5940e 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -292,11 +292,12 @@ _xtensa_level1_handler: l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ - /* Return from interrupt. RFI restores the PS from EPS_1 and jumps to - * the address in EPC_1. + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. */ - rfi 1 + rfe /* And return from "exception" */ /**************************************************************************** * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS. diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index ca118aae80d..39c9eb1c7f9 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -372,9 +372,9 @@ _xtensa_syscall_handler: l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ - /* Return from exception. RFE returns from either the UserExceptionVector - * or the KernelExceptionVector. RFE sets PS.EXCM back to 0 and then jumps - * to the address in EPC[1]. + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. */ rfe diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig index 073954b7d6b..9edff0ce33e 100644 --- a/arch/xtensa/src/lx6/Kconfig +++ b/arch/xtensa/src/lx6/Kconfig @@ -5,27 +5,4 @@ if ARCH_CHIP_LX6 -choice - prompt "LX6 implementation" - default ARCH_CHIP_ESP32 - -config ARCH_CHIP_ESP32 - bool "Expressif ESP32" - ---help--- - The ESP32 is a dual-core system with two Harvard Architecture Xtensa - LX6 CPUs. All embedded memory, external memory and peripherals are - located on the data bus and/or the instruction bus of these CPUs. - With some minor exceptions the address mapping of two CPUs is - symmetric, meaning they use the same addresses to access the same - memory. Multiple peripherals in the system can access embedded - memory via DMA. - - The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and - "application"), however for most purposes the two CPUs are - interchangeable. - -endchoice # LX6 implementation - -source arch/xtensa/src/esp32/Kconfig - endif # ARCH_CHIP_LX6 From 05e798488baad93bbcf011e3e97c2550ea1b4c3a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 08:10:10 -0600 Subject: [PATCH 2/4] One register getting clobber on context save --- arch/xtensa/src/common/xtensa_context.S | 1 - arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index f927f99c051..10d772c12d8 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -116,7 +116,6 @@ _xtensa_context_save: - s32i a2, a2, (4 * REG_A2) s32i a3, a2, (4 * REG_A3) s32i a4, a2, (4 * REG_A4) s32i a5, a2, (4 * REG_A5) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index a7d12e5940e..f84992d2127 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -290,7 +290,7 @@ _xtensa_level1_handler: l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ - rsync /* Ensure EPS and EPC written */ + rsync /* Ensure PS and EPC written */ /* Return from exception. RFE returns from either the UserExceptionVector * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then From 38ebe6c13f3053788a8c22c4b074c0a228d4b8ff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 08:11:32 -0600 Subject: [PATCH 3/4] Xtensa ESP32: Change that should have been included in a previous commit was not. --- arch/xtensa/src/common/xtensa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 422ec0b96fb..9cf4778e54a 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -266,7 +266,7 @@ void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset); /* IRQs */ -uint32_t *xtensa_int_decode(uint32_t *regs); +uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask); From ec85425041396c87f636a3c4db4ca973d0ad1f38 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 17 Dec 2016 08:31:12 -0600 Subject: [PATCH 4/4] STM32: Fix some STM32F7 copy paste errors --- arch/arm/src/stm32/stm32_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 644c810817e..10919e878bc 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1945,11 +1945,11 @@ static int up_interrupt_common(struct up_dev_s *priv) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK;