diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 5c051980e68..b00d8f0d235 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,6 +22,10 @@ config ARCH_CHIP_ESP32
 		of two CPUs is symmetric, meaning they use the same addresses to
 		access the same memory.
 
+		The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
+		"application"), however for most purposes the two CPUs are
+		interchangeable.
+
 endchoice # XTENSA chip selection
 
 config ARCH_FAMILY_LX6
diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h
index 422ec0b96fb..9cf4778e54a 100644
--- a/arch/xtensa/src/common/xtensa.h
+++ b/arch/xtensa/src/common/xtensa.h
@@ -266,7 +266,7 @@ void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset);
 
 /* IRQs */
 
-uint32_t *xtensa_int_decode(uint32_t *regs);
+uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs);
 uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs);
 uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask);
 uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask);
diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S
index bbe68ede204..10d772c12d8 100644
--- a/arch/xtensa/src/common/xtensa_context.S
+++ b/arch/xtensa/src/common/xtensa_context.S
@@ -116,7 +116,6 @@
 
 _xtensa_context_save:
 
-	s32i	a2,  a2, (4 * REG_A2)
 	s32i	a3,  a2, (4 * REG_A3)
 	s32i	a4,  a2, (4 * REG_A4)
 	s32i	a5,  a2, (4 * REG_A5)
@@ -371,10 +370,15 @@ xtensa_context_restore:
 	l32i	a0, a2, (4 * REG_PS)			/* Restore PS */
 	wsr		a0, PS
 	l32i	a0, a2, (4 * REG_PC)			/* Set up for RFE */
-	rsr		a0, EPC
+	rsr		a0, EPC_1
 	l32i	a0, a2, (4 * REG_A0)			/* Restore a0 */
 	l32i	a2, a2, (4 * REG_A2)			/* Restore A2 */
 
+	/* Return from exception. RFE returns from either the UserExceptionVector
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
+	 */
+
 	rfe										/* And return from "exception" */
 
 	.size	xtensa_context_restore, . - xtensa_context_restore
diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S
index 5b59ac8774a..f84992d2127 100644
--- a/arch/xtensa/src/common/xtensa_int_handlers.S
+++ b/arch/xtensa/src/common/xtensa_int_handlers.S
@@ -290,13 +290,14 @@ _xtensa_level1_handler:
 	l32i	a0, a2, (4 * REG_A0)			/* Retrieve interruptee's A0 */
     l32i    sp, a2, (4 * REG_A1)            /* Remove interrupt stack frame */
 	l32i	a2, a2, (4 * REG_A2)			/* Retrieve interruptee's A2 */
-	rsync									/* Ensure EPS and EPC written */
+	rsync									/* Ensure PS and EPC written */
 
-	/* Return from interrupt.  RFI  restores the PS from EPS_1 and jumps to
-	 * the address in EPC_1.
+	/* Return from exception. RFE returns from either the UserExceptionVector
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
 	 */
 
-	rfi		1
+	rfe										/* And return from "exception" */
 
 /****************************************************************************
  * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS.
diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S
index ca118aae80d..39c9eb1c7f9 100644
--- a/arch/xtensa/src/common/xtensa_user_handler.S
+++ b/arch/xtensa/src/common/xtensa_user_handler.S
@@ -372,9 +372,9 @@ _xtensa_syscall_handler:
 	l32i	a2, a2, (4 * REG_A2)			/* Retrieve interruptee's A2 */
 	rsync									/* Ensure EPS and EPC written */
 
-	/* Return from exception.  RFE returns from either the UserExceptionVector
-	 * or the KernelExceptionVector. RFE sets PS.EXCM back to 0 and then jumps
-	 * to the address in EPC[1].
+	/* Return from exception. RFE returns from either the UserExceptionVector
+	 * or the KernelExceptionVector.  RFE sets PS.EXCM back to 0, and then
+	 * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
 	 */
 
 	rfe
diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig
index 073954b7d6b..9edff0ce33e 100644
--- a/arch/xtensa/src/lx6/Kconfig
+++ b/arch/xtensa/src/lx6/Kconfig
@@ -5,27 +5,4 @@
 
 if ARCH_CHIP_LX6
 
-choice
-	prompt "LX6 implementation"
-	default ARCH_CHIP_ESP32
-
-config ARCH_CHIP_ESP32
-	bool "Expressif ESP32"
-	---help---
-		The ESP32 is a dual-core system with two Harvard Architecture Xtensa
-		LX6 CPUs. All embedded memory, external memory and peripherals are
-		located on the data bus and/or the instruction bus of these CPUs.
-		With some minor exceptions the address mapping of two CPUs is
-		symmetric, meaning they use the same addresses to access the same
-		memory. Multiple peripherals in the system can access embedded
-		memory via DMA.
-
-		The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
-		"application"), however for most purposes the two CPUs are
-		interchangeable.
-
-endchoice # LX6 implementation
-
-source arch/xtensa/src/esp32/Kconfig
-
 endif # ARCH_CHIP_LX6