Add RX65N SPI (RSPI) driver support

arch/renesas/include/rx65n/irq.h

@@ -116,7 +116,9 @@
 #ifdef CONFIG_RX65N_RSPI0
 #  define RX65N_SPRI0_IRQ      (RX65N_RSPI0_IRQBASE)
 #  define RX65N_SPTI0_IRQ      (RX65N_RSPI0_IRQBASE + 1)
-#  define RX65N_RSPI1_IRQBASE  (RX65N_RSPI0_IRQBASE + 2)
+#  define RX65N_SPEI0_IRQ      (RX65N_RSPI0_IRQBASE + 2)
+#  define RX65N_SPII0_IRQ      (RX65N_RSPI0_IRQBASE + 3)
+#  define RX65N_RSPI1_IRQBASE  (RX65N_RSPI0_IRQBASE + 4)
 #else
 #  define RX65N_RSPI1_IRQBASE  (RX65N_RSPI0_IRQBASE)
 #endif
@@ -124,7 +126,9 @@
 #ifdef CONFIG_RX65N_RSPI1
 #  define RX65N_SPRI1_IRQ       (RX65N_RSPI1_IRQBASE)
 #  define RX65N_SPTI1_IRQ       (RX65N_RSPI1_IRQBASE + 1)
-#  define RX65N_QSPI_IRQBASE    (RX65N_RSPI1_IRQBASE + 2)
+#  define RX65N_SPEI1_IRQ       (RX65N_RSPI1_IRQBASE + 2)
+#  define RX65N_SPII1_IRQ       (RX65N_RSPI1_IRQBASE + 3)
+#  define RX65N_QSPI_IRQBASE    (RX65N_RSPI1_IRQBASE + 4)
 #else
 #  define RX65N_QSPI_IRQBASE    (RX65N_RSPI1_IRQBASE)
 #endif
@@ -374,7 +378,9 @@
 #ifdef CONFIG_RX65N_RSPI2
 #  define RX65N_SPRI2_IRQ               (RX65N_RSPI2_IRQBASE)
 #  define RX65N_SPTI2_IRQ               (RX65N_RSPI2_IRQBASE + 1)
-#  define RX65N_IRQ_GROUPBL_IRQBASE     (RX65N_RSPI2_IRQBASE + 2)
+#  define RX65N_SPEI2_IRQ               (RX65N_RSPI2_IRQBASE + 2)
+#  define RX65N_SPII2_IRQ               (RX65N_RSPI2_IRQBASE + 3)
+#  define RX65N_IRQ_GROUPBL_IRQBASE     (RX65N_RSPI2_IRQBASE + 4)
 #else
 #  define RX65N_IRQ_GROUPBL_IRQBASE     (RX65N_RSPI2_IRQBASE)
 #endif

arch/renesas/src/rx65n/Kconfig

@@ -203,6 +203,75 @@ config RX65N_RTC
 config RX65N_CARRY
 	bool "RTC"
 	default y
+
+config RX65N_RSPI
+	bool "RSPI"
+	select SPI
+	select SPI_DRIVER
+	default n
+
+if RX65N_RSPI
+
+config RX65N_DATA_TRANSFER_MODE
+	bool "Data transfer mode"
+	default y
+
+if RX65N_DATA_TRANSFER_MODE
+
+config RX65N_RSPI_SW_DT_MODE
+	bool "Software DT mode"
+	default n
+
+config RX65N_RSPI_DTC_DT_MODE
+	bool "DTC DT mode"
+	depends on !RX65N_RSPI_SW_DT_MODE
+	select RX65N_DTC
+	default y
+
+endif
+
+config RX65N_RSPI_HIGHSPEED
+	bool "Speed: 0:Normal,1:High"
+	default y
+
+config RX65N_RSPI_BITORDER
+	bool "Bit order: 0:MSBF,1:LSBF"
+	default y
+
+config RX65N_RSPI_BUF_SIZE
+	int "RSPI buffer size(1-4)"
+	default 1
+	range 1 4
+
+config RX65N_RSPI_SPCKD_DELAY
+	int "RSPI clock delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI_SSLND_DELAY
+	int "RSPI SSL negation delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI_SPND_DELAY
+	int "RSPI next access delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI0
+	bool "RSPI0"
+	default y
+
+config RX65N_RSPI1
+	bool "RSPI1"
+	default n
+
+config RX65N_RSPI2
+	bool "RSPI2"
+	default n
+
+endif
+
 config RX65N_RIIC0 
 	bool "RIIC0"
 	default n
@@ -341,6 +410,20 @@ config RX65N_RIIC2_RCV_IN_BYTE_UNITS
 	
 endif #RX65N_RIIC2
 
+config RX65N_USBDEV 
+	bool "USB0 Device"
+	default n
+	depends on USBDEV
+
+if RX65N_USBDEV
+
+config RX65N_TEST_INTEP
+	bool "Testing RX65N Interrupt endpoint"
+	default n
+	depends on SERIAL_IFLOWCONTROL && CDCACM_IFLOWCONTROL
+
+endif #RX65N_USBDEV
+
 config RX65N_DTC
 	bool "DTC"
 	default n
@@ -500,6 +583,74 @@ config RX65N_EMAC0
 	select NETDEVICES
 	select ARCH_HAVE_PHY
 
+config RX65N_RSPI
+	bool "RSPI"
+	select SPI
+	select SPI_DRIVER
+	default n
+
+if RX65N_RSPI
+
+config RX65N_DATA_TRANSFER_MODE
+	bool "Data transfer mode"
+	default y
+
+if RX65N_DATA_TRANSFER_MODE
+
+config RX65N_RSPI_SW_DT_MODE
+	bool "Software DT mode"
+	default n
+
+config RX65N_RSPI_DTC_DT_MODE
+	bool "DTC DT mode"
+	depends on !RX65N_RSPI_SW_DT_MODE
+	select RX65N_DTC
+	default y
+
+endif
+
+config RX65N_RSPI_HIGHSPEED
+	bool "Speed: 0:Normal,1:High"
+	default y
+
+config RX65N_RSPI_BITORDER
+	bool "Bit order: 0:MSBF,1:LSBF"
+	default y
+
+config RX65N_RSPI_BUF_SIZE
+	int "RSPI buffer size(1-4)"
+	default 1
+	range 1 4
+
+config RX65N_RSPI_SPCKD_DELAY
+	int "RSPI clock delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI_SSLND_DELAY
+	int "RSPI SSL negation delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI_SPND_DELAY
+	int "RSPI next access delay"
+	default 2
+	range 0 7
+
+config RX65N_RSPI0
+	bool "RSPI0"
+	default y
+
+config RX65N_RSPI1
+	bool "RSPI1"
+	default n
+
+config RX65N_RSPI2
+	bool "RSPI2"
+	default n
+
+endif
+
 config RX65N_RIIC0 
 	bool "RIIC0"
 	default n

arch/renesas/src/rx65n/Make.defs

@@ -63,6 +63,10 @@ ifeq ($(CONFIG_USBDEV),y)
 CHIP_CSRCS += rx65n_usbdev.c
 endif
 
+ifeq ($(CONFIG_RX65N_RSPI),y)
+CHIP_CSRCS += rx65n_rspi.c
+endif
+
 ifeq ($(CONFIG_I2C),y)
 CHIP_CSRCS += rx65n_riic.c
 endif

arch/renesas/src/rx65n/rx65n_definitions.h

@@ -227,6 +227,12 @@
 #define RX65N_GRPAL0_ERI10_MASK         (1U <<  9)
 #define RX65N_GRPAL0_TEI11_MASK         (1U << 12)
 #define RX65N_GRPAL0_ERI11_MASK         (1U << 13)
+#define RX65N_GRPAL0_SPII0_MASK         (1U << 16)
+#define RX65N_GRPAL0_SPEI0_MASK         (1U << 17)
+#define RX65N_GRPAL0_SPII1_MASK         (1U << 18)
+#define RX65N_GRPAL0_SPEI1_MASK         (1U << 19)
+#define RX65N_GRPAL0_SPII2_MASK         (1U << 20)
+#define RX65N_GRPAL0_SPEI2_MASK         (1U << 21)
 #define RX65N_GRPBL0_TEI12_MASK         (1U << 16)
 #define RX65N_GRPBL0_ERI12_MASK         (1U << 17)
 
@@ -1443,6 +1449,163 @@
 #define USB_INT_BRDY                                 (0x0001u)
 #define USB_BMREQUESTTYPERECIP                       (0x001Fu)   /* b4-0: Recipient */
 
+/* Start of RSPI interface related definitions */
+
+#if defined(CONFIG_SPI) || defined(CONFIG_SPI_DRIVER)
+  #define HAVE_RSPI_DRIVER            1
+#endif
+
+#define RX65N_RSPI0_BASE              (0x000D0100)
+#define RX65N_RSPI1_BASE              (0x000D0140)
+#define RX65N_RSPI2_BASE              (0x000D0300)
+
+/* Tx and Rx vector number */
+
+#define RX65N_RSPI0_RXVECT            (38)
+#define RX65N_RSPI0_TXVECT            (39)
+#define RX65N_RSPI1_RXVECT            (40)
+#define RX65N_RSPI1_TXVECT            (41)
+#define RX65N_RSPI2_RXVECT            (108)
+#define RX65N_RSPI2_TXVECT            (109)
+
+#define RX65N_PCLK_FREQUENCY RX_PCLKA
+
+/* RSPI Register offsets */
+
+#define RX65N_RSPI_SPCR_OFFSET        (0x0000)   /* RSPI Control Register */
+#define RX65N_RSPI_SSLP_OFFSET        (0x0001)   /* RSPI Slave Select Polarity Register */
+#define RX65N_RSPI_SPPCR_OFFSET       (0x0002)   /* RSPI Pin Control Register */
+#define RX65N_RSPI_SPSR_OFFSET        (0x0003)   /* RSPI Status Register */
+#define RX65N_RSPI_SPDR_OFFSET        (0x0004)   /* RSPI Data Register */
+#define RX65N_RSPI_SPSCR_OFFSET       (0x0008)   /* RSPI Sequence Control Register */
+#define RX65N_RSPI_SPSSR_OFFSET       (0x0009)   /* RSPI Sequence Status Register */
+#define RX65N_RSPI_SPBR_OFFSET        (0x000A)   /* RSPI Bit Rate Register */
+#define RX65N_RSPI_SPDCR_OFFSET       (0x000B)   /* RSPI Data Control Register */
+#define RX65N_RSPI_SPCKD_OFFSET       (0x000C)   /* RSPI Clock Delay Register */
+#define RX65N_RSPI_SSLND_OFFSET       (0x000D)   /* RSPI Slave Select Negation Delay Register */
+#define RX65N_RSPI_SPND_OFFSET        (0x000E)   /* RSPI Next-Access Delay Register */
+#define RX65N_RSPI_SPCR2_OFFSET       (0x000F)   /* RSPI Control Register 2 */
+#define RX65N_RSPI_SPCMD0_OFFSET      (0x0010)   /* RSPI Command Registers 0 */
+#define RX65N_RSPI_SPCMD1_OFFSET      (0x0012)   /* RSPI Command Registers 1 */
+#define RX65N_RSPI_SPCMD2_OFFSET      (0x0014)   /* RSPI Command Registers 2 */
+#define RX65N_RSPI_SPCMD3_OFFSET      (0x0016)   /* RSPI Command Registers 3 */
+#define RX65N_RSPI_SPCMD4_OFFSET      (0x0018)   /* RSPI Command Registers 4 */
+#define RX65N_RSPI_SPCMD5_OFFSET      (0x001A)   /* RSPI Command Registers 5 */
+#define RX65N_RSPI_SPCMD6_OFFSET      (0x001C)   /* RSPI Command Registers 6 */
+#define RX65N_RSPI_SPCMD7_OFFSET      (0x001E)   /* RSPI Command Registers 7 */
+#define RX65N_RSPI_SPDCR2_OFFSET      (0x0020)   /* RSPI Data Control Register 2 */
+
+/* RSPI Control Register bits */
+
+#define RSPI_SPCR_SMPS                (1 << 0) /* RSPI Mode Select */
+#define RSPI_SPCR_TXMD                (1 << 1) /* Communications Operating Mode Select */
+#define RSPI_SPCR_MODFEN              (1 << 2) /* Mode Fault Error Detection Enable */
+#define RSPI_SPCR_MSTR                (1 << 3) /* RSPI Master/Slave Mode Select */
+#define RSPI_SPCR_SPEIE               (1 << 4) /* RSPI Error Interrupt Enable */
+#define RSPI_SPCR_SPTIE               (1 << 5) /* Transmit Buffer Empty Interrupt Enable */
+#define RSPI_SPCR_SPE                 (1 << 6) /* RSPI Function Enable */
+#define RSPI_SPCR_SPRIE               (1 << 7) /* RSPI Receive Buffer Full Interrupt Enable */
+
+/* RSPI Slave Select Polarity Register bits */
+
+#define RSPI_SSLP_SSL0P               (1 << 0)  /* SSL0 Signal Polarity Setting */
+#define RSPI_SSLP_SSL1P               (1 << 1)  /* SSL0 Signal Polarity Setting */
+#define RSPI_SSLP_SSL2P               (1 << 2)  /* SSL0 Signal Polarity Setting */
+#define RSPI_SSLP_SSL3P               (1 << 3)  /* SSL0 Signal Polarity Setting */
+
+/* RSPI Pin Control Register bits */
+
+#define RSPI_SPPCR_SPLP               (1 << 0)  /* 0: Normal mode. 1: Loopback mode (reversed transmit data = receive). */
+#define RSPI_SPPCR_SPLP2              (1 << 1)  /* 0: Normal mode. 1: Loopback mode (transmit data = receive data). */
+#define RSPI_SPPCR_MOIFV              (1 << 4)  /* 0: MOSI pin idles low. 1: MOSI pin idles high. */
+#define RSPI_SPPCR_MOIFE              (1 << 5)  /* 0: MOSI pin idles at final previous data. 1: MOSI pin idles at MOIFV. */
+
+/* RSPI status register bits */
+
+#define RSPI_SPSR_OVRF                (1 << 0)  /* Overrun Error Flag */
+#define RSPI_SPSR_IDLNF               (1 << 1)  /* RSPI Idle Flag */
+#define RSPI_SPSR_MODF                (1 << 2)  /* Mode Fault Error Flag */
+#define RSPI_SPSR_PERF                (1 << 3)  /* Parity Error Flag */
+#define RSPI_SPSR_UDRF                (1 << 4)  /* Underrun Error Flag */
+#define RSPI_SPSR_SPTEF               (1 << 5)  /* Transmit Buffer Empty Flag */
+#define RSPI_SPSR_SPRF                (1 << 7)  /* Receive Buffer Full Flag */
+#define RSPI_SPSR_MODF_UDRF_MASK      (0xAB)    /* Protect reserved bits. */
+
+/* RSPI Data Control Register bit and mask */
+
+#define RSPI_SPDCR_MASK               (0x73)   /* Mask for SPDCR*/
+#define RSPI_SPDCR_SPFC0              (1 << 0) /* b0 used for number of frame calculation with b1 */
+#define RSPI_SPDCR_SPFC1              (1 << 1) /* b1 used for number of frame calculation with b0 */
+#define RSPI_SPDCR_SPRDTD             (1 << 4) /* RSPI Receive/Transmit Data Select*/
+#define RSPI_SPDCR_SPLW               (1 << 5) /* RSPI Longword Access Word Access Specification */
+#define RSPI_SPDCR_SPBYT              (1 << 6) /* RSPI Byte Access Specification*/
+#define RSPI_SPDCR_SPFC_MASK          (0x3)    /* SPFC mask */
+
+/* RSPI command register bits */
+
+#define RSPI_SPCMD_MASK               (0xFF << 0) /* RSPI Command Register mask */
+#define RSPI_SPCMD_PHA                (1 << 0)    /* RSPCK Phase Setting */
+#define RSPI_SPCMD_POL                (1 << 1)    /* RSPCK Polarity Setting */
+#define RSPI_SPCMD_BRDV0              (1 << 2)    /* Bit Rate Division Setting bit b2 */
+#define RSPI_SPCMD_BRDV1              (1 << 3)    /* Bit Rate Division Setting bit b3 */
+#define RSPI_SPCMD_SSLA0              (1 << 4)    /* SSL Signal Assertion Setting bit b4 */
+#define RSPI_SPCMD_SSLA1              (1 << 5)    /* SSL Signal Assertion Setting bit b5 */
+#define RSPI_SPCMD_SSLA2              (1 << 6)    /* SSL Signal Assertion Setting bit b6 */
+#define RSPI_SPCMD_SSLKP              (1 << 7)    /* SSL Signal Level Keeping bit b7 */
+#define RSPI_SPCMD_SPB0               (1 << 8)    /* RSPI Data Length Setting bit b8 */
+#define RSPI_SPCMD_SPB1               (1 << 9)    /* RSPI Data Length Setting bit b9 */
+#define RSPI_SPCMD_SPB2               (1 << 10)   /* RSPI Data Length Setting bit b10 */
+#define RSPI_SPCMD_SPB3               (1 << 11)   /* RSPI Data Length Setting bit b11 */
+#define RSPI_SPCMD_LSBF               (1 << 12)   /* RSPI LSB First bit b12 */
+#define RSPI_SPCMD_SPNDEN             (1 << 13)   /* RSPI Next-Access Delay Enable bit */
+#define RSPI_SPCMD_SLNDEN             (1 << 14)   /* SSL Negation Delay Setting Enable bit */
+#define RSPI_SPCMD_SCKDEN             (1 << 15)   /* SCKDEN RSPCK Delay Setting Enable bit */
+#define RSPI_SPCMD_BRDV_MASK          (3 << 2)    /* Bit Rate Division Setting mask */
+#define RSPI_SPCMD_SPB_MASK           (15 << 8)   /* RSPI Data Length Setting */
+
+/* RSPI clock delay register bit */
+
+#define RSPI_SPCKD_MASK               (7 << 0)  /* RSPCK Delay Setting mask */
+#define RSPI_SPCKD_SCKDL0             (1 << 0)  /* SCKDL0 bit */
+#define RSPI_SPCKD_SCKDL1             (1 << 1)  /* SCKDL1 bit */
+#define RSPI_SPCKD_SCKDL2             (1 << 2)  /* SCKDL2 bit */
+
+/* RSPI Slave Select Negation Delay Register bit */
+
+#define RSPI_SSLND_MASK               (7 << 0)  /* SSL Negation Delay Setting mask */
+#define RSPI_SSLND_SLNDL0             (1 << 0)  /* SLNDL0 bit */
+#define RSPI_SSLND_SLNDL1             (1 << 1)  /* SLNDL1 bit */
+#define RSPI_SSLND_SLNDL2             (1 << 2)  /* SLNDL2 bit */
+
+/* RSPI clock delay register bit */
+
+#define RSPI_SPND_MASK                (7 << 0)  /* RSPI Next-Access Delay mask */
+#define RSPI_SPND_SPNDL0              (1 << 0)  /* SPNDL0 bit */
+#define RSPI_SPND_SPNDL1              (1 << 1)  /* SPNDL1 bit */
+#define RSPI_SPND_SPNDL2              (1 << 2)  /* SPNDL2 bit */
+
+/* RSPI RSPI Control Register 2 bit */
+
+#define RSPI_SPCR2_MASK               (0x1F << 0)  /* RSPI Control Register 2 mask */
+#define RSPI_SPCR2_SPPE               (1 << 0)     /* Parity Enable bit */
+#define RSPI_SPCR2_SPOE               (1 << 1)     /* Parity Mode bit */
+#define RSPI_SPCR2_SPIIE              (1 << 2)     /* RSPI Idle Interrupt Enable */
+#define RSPI_SPCR2_PTE                (1 << 3)     /* Parity Self-Diagnosis bit */
+#define RSPI_SPCR2_SCKASE             (1 << 4)     /* RSPCK Auto-Stop Function Enable bit */
+
+/* RSPI Sequence Control Register 2 bit */
+
+#define RSPI_SPSCR_MASK               (7 << 0) /* RSPI Sequence Control Register mask */
+#define RSPI_SPSCR_SPSLN0             (1 << 0) /* SPSLN0 bit */
+#define RSPI_SPSCR_SPSLN1             (1 << 1) /* SPSLN1 bit */
+#define RSPI_SPSCR_SPSLN2             (1 << 2) /* SPSLN2 bit */
+
+/* Set RSPI data control register 2 bit */
+
+#define RSPI_SPDCR2_BYSW              (1 << 0) /* RSPI Byte Swap */
+
+/* End of RSPI interface related definitions */
+
 /* RIIC related definitions */
 
 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)

arch/renesas/src/rx65n/rx65n_irq.c

@@ -426,6 +426,74 @@ void up_disable_irq(int irq)
 
 #endif
 #endif
+
+#ifdef CONFIG_RX65N_RSPI0
+  if (irq == RX65N_SPRI0_IRQ)
+    {
+      ICU.IER[0x04].BIT.IEN6 = 0;
+    }
+
+  if (irq == RX65N_SPTI0_IRQ)
+    {
+      ICU.IER[0x04].BIT.IEN7 = 0;
+    }
+
+  if (irq == RX65N_SPEI0_IRQ)
+    {
+      ICU.GENAL0.BIT.EN17 = 0;
+    }
+
+  if (irq == RX65N_SPII0_IRQ)
+    {
+      ICU.GENAL0.BIT.EN16 = 0;
+    }
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+  if (irq == RX65N_SPRI1_IRQ)
+    {
+      ICU.IER[0x05].BIT.IEN0 = 0;
+    }
+
+  if (irq == RX65N_SPTI1_IRQ)
+    {
+      ICU.IER[0x05].BIT.IEN1 = 0;
+    }
+
+  if (irq == RX65N_SPEI1_IRQ)
+    {
+      ICU.GENAL0.BIT.EN19 = 0;
+    }
+
+  if (irq == RX65N_SPII1_IRQ)
+    {
+      ICU.GENAL0.BIT.EN18 = 0;
+    }
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+  if (irq == RX65N_SPRI2_IRQ)
+    {
+      ICU.IER[13].BIT.IEN4 = 0;
+    }
+
+  if (irq == RX65N_SPTI2_IRQ)
+    {
+      ICU.IER[13].BIT.IEN5 = 0;
+    }
+
+  if (irq == RX65N_SPEI2_IRQ)
+    {
+      ICU.GENAL0.BIT.EN21 = 0;
+    }
+
+  if (irq == RX65N_SPII2_IRQ)
+    {
+      ICU.GENAL0.BIT.EN20 = 0;
+    }
+
+#endif
+
 #ifdef CONFIG_RX65N_RIIC0
   if (irq == RX65N_RIIC0_RXI0_IRQ)
     {
@@ -856,6 +924,74 @@ void up_enable_irq(int irq)
 
 #endif
 #endif
+
+#ifdef CONFIG_RX65N_RSPI0
+  if (irq == RX65N_SPRI0_IRQ)
+    {
+      ICU.IER[0x04].BIT.IEN6 = 1;
+    }
+
+  if (irq == RX65N_SPTI0_IRQ)
+    {
+      ICU.IER[0x04].BIT.IEN7 = 1;
+    }
+
+  if (irq == RX65N_SPEI0_IRQ)
+    {
+      ICU.GENAL0.BIT.EN17 = 1;
+    }
+
+  if (irq == RX65N_SPII0_IRQ)
+    {
+      ICU.GENAL0.BIT.EN16 = 1;
+    }
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+  if (irq == RX65N_SPRI1_IRQ)
+    {
+      ICU.IER[0x05].BIT.IEN0 = 1;
+    }
+
+  if (irq == RX65N_SPTI1_IRQ)
+    {
+      ICU.IER[0x05].BIT.IEN1 = 1;
+    }
+
+  if (irq == RX65N_SPEI1_IRQ)
+    {
+      ICU.GENAL0.BIT.EN19 = 1;
+    }
+
+  if (irq == RX65N_SPII1_IRQ)
+    {
+      ICU.GENAL0.BIT.EN18 = 1;
+    }
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+  if (irq == RX65N_SPRI2_IRQ)
+    {
+      ICU.IER[13].BIT.IEN4 = 1;
+    }
+
+  if (irq == RX65N_SPTI2_IRQ)
+    {
+      ICU.IER[13].BIT.IEN5 = 1;
+    }
+
+  if (irq == RX65N_SPEI2_IRQ)
+    {
+      ICU.GENAL0.BIT.EN21 = 1;
+    }
+
+  if (irq == RX65N_SPII2_IRQ)
+    {
+      ICU.GENAL0.BIT.EN20 = 1;
+    }
+
+#endif
+
 #ifdef CONFIG_RX65N_RIIC0
   if (irq == RX65N_RIIC0_RXI0_IRQ)
     {

arch/renesas/src/rx65n/rx65n_rspi.h

@@ -0,0 +1,167 @@
+/****************************************************************************
+ * arch/renesas/src/rx65n/rx65n_rspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_RSPI_H
+#define __ARCH_RENESAS_SRC_RX65N_RX65N_RSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/spi/spi.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+struct spi_dev_s;
+
+/****************************************************************************
+ * Name: rx65n_rspibus_initialize
+ *
+ * Description:
+ *   Initialize the selected SPI bus
+ *
+ * Input Parameters:
+ *   bus number (for hardware that has multiple SPI interfaces)
+ *
+ * Returned Value:
+ *   Valid SPI device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct spi_dev_s *rx65n_rspibus_initialize(int bus);
+
+/****************************************************************************
+ * Name:  rx65n_rspi0/1/2 select and rx65n_rspi0/1/2 status
+ *
+ * Description:
+ *   The external functions, rx65n_rspi0/1/2 select, rx65n_rspi0/1/2 status,
+ *   and rx65n_rspi0/1/2 cmddata must be provided by board-specific logic.
+ *   These are implementations of the select, status, and cmddata methods of
+ *   the SPI interface defined by struct spi_ops_s
+ *   (see include/nuttx/spi/spi.h). All other methods (including
+ *   rx65n_rspibus_initialize()) are provided by common R656N logic.
+ *   To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in stm32_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status()
+ *      functions in your board-specific logic.  These functions will
+ *      perform chip selection and status operations using GPIOs in the
+ *      way your board is configured.
+ *   3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
+ *      then provide stm32_spi1/2/...cmddata() functions in your
+ *      board-specific logic. These functions will perform cmd/data
+ *      selection operations using GPIOs in the way your board is
+ *      configured.
+ *   4. Add a calls to stm32_spibus_initialize() in your low level
+ *      application initialization logic
+ *   5. The handle returned by stm32_spibus_initialize() may then be used
+ *      to bind the SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+#ifdef CONFIG_RX65N_RSPI0
+void rx65n_rspi0select(FAR struct spi_dev_s *dev, uint32_t devid,
+                        bool selected);
+uint8_t rx65n_rspi0status(FAR struct spi_dev_s *dev, uint32_t devid);
+int rx65n_rspi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+void rx65n_rspi1select(FAR struct spi_dev_s *dev, uint32_t devid,
+                        bool selected);
+uint8_t rx65n_rspi1status(FAR struct spi_dev_s *dev, uint32_t devid);
+int rx65n_rspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+void rx65n_rspi2select(FAR struct spi_dev_s *dev, uint32_t devid,
+                        bool selected);
+uint8_t rx65n_rspi2status(FAR struct spi_dev_s *dev, uint32_t devid);
+int rx65n_rspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+
+/****************************************************************************
+ * Name: rx65n_rspi0/1/2register
+ *
+ * Description:
+ *   If the board supports a card detect callback to inform the SPI-based
+ *   MMC/SD driver when an SD card is inserted or removed, then
+ *   CONFIG_SPI_CALLBACK should be defined and the following function(s)
+ *   must be implemented.  These functions implements the registercallback
+ *   method of the SPI interface (see include/nuttx/spi/spi.h for details)
+ *
+ * Input Parameters:
+ *   dev -      Device-specific state data
+ *   callback - The function to call on the media change
+ *   arg -      A caller provided value to return with the callback
+ *
+ * Returned Value:
+ *   0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_CALLBACK
+#ifdef CONFIG_RX65N_RSPI0
+int rx65n_rspi0register(FAR struct spi_dev_s *dev,
+                        spi_mediachange_t callback,
+                       FAR void *arg);
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+int rx65n_rspi1register(FAR struct spi_dev_s *dev,
+                        spi_mediachange_t callback,
+                       FAR void *arg);
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+int rx65n_rspi2register(FAR struct spi_dev_s *dev,
+                         spi_mediachange_t callback,
+                       FAR void *arg);
+#endif
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_RSPI_H */

arch/renesas/src/rx65n/rx65n_vector.S

@@ -580,6 +580,21 @@ _uprx65_groupal0_handler:
   multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 13, RX65N_ERI11_IRQ
 #endif /* CONFIG_RX65N_SCI11 */
 
+#ifdef CONFIG_RX65N_RSPI0
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 16, RX65N_SPII0_IRQ
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 17, RX65N_SPEI0_IRQ
+#endif /* CONFIG_RX65N_RSPI0 */
+
+#ifdef CONFIG_RX65N_RSPI1
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 18, RX65N_SPII1_IRQ
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 19, RX65N_SPEI1_IRQ
+#endif /* CONFIG_RX65N_RSPI1 */
+
+#ifdef CONFIG_RX65N_RSPI2
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 20, RX65N_SPII2_IRQ
+  multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 21, RX65N_SPEI2_IRQ
+#endif /* CONFIG_RX65N_RSPI2 */
+
 /* TODO: Please write the others with
  * definition RX65N_XXX_IRQ in irq.h as IRQ number
  */

boards/renesas/rx65n/rx65n-grrose/README.txt

@@ -14,6 +14,9 @@ Contents
   - Contents
   - RTC
   - USB Device
+  - RSPI
+  - RIIC
+  - DTC
   - Debugging
   - Debugging
 
@@ -215,6 +218,13 @@ Configure UDP blaster application as mentioned below :
 CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801  (10.75.24.1) ------> Gateway IP
 CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
 CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
+
+RSPI
+-----------
+
+For GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only brought out as 
+Pin number 2 and 3 in CN4 is used for MOSIB and MISOB respectively.
+
 RTC
 ==========
 
@@ -251,6 +261,44 @@ xd 0 0x20000 > /dev/ttyACM0
 
 The output of the commands mentioned above should be seen on the USB Device COM port on teraterm
 
+RSPI Configurations
+--------------------------
+The following configurations need to be enabled for RSPI
+
+CONFIG_SYSTEM_SPITOOL=y
+
+RSPI Testing
+------------------------
+The following testing is executed as part of RSPI testing on RX65N target for GRROSE board
+
+On GRROSE board only channel 1 can be tested since RSPI channel1 pinout is only brought out.
+
+Following command can be used for testing RSPI communication to slave device.
+spi exch -b 0 -x 4 aabbccdd
+where b is bus number and x is Number of word to exchange.
+
+RIIC Configurations
+--------------------------
+The following configurations need to be enabled for RIIC
+
+CONFIG_SYSTEM_I2CTOOL=y
+
+RIIC Testing
+------------------------
+
+On GRROSE board, none of the RIIC channel pins are brought out in the board so not tested for communication.
+
+DTC Configurations
+--------------------------
+The following configurations need to be enabled for DTC.
+
+CONFIG_SYSTEM_SPITOOL=y
+
+DTC Testing
+------------------------
+
+DTC has been tested using RSPI driver.
+
 Debugging
 ==========
 

boards/renesas/rx65n/rx65n-grrose/include/rx65n_gpio.h

@@ -49,6 +49,12 @@
   #define RX65N_MAC_ADDRH 0x00000000
 #endif
 
+/* RSPI channel number */
+
+#define RX65N_RSPI_CHANNEL0 0
+#define RX65N_RSPI_CHANNEL1 1
+#define RX65N_RSPI_CHANNEL2 2
+
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
@@ -246,6 +252,23 @@ void sci6_init_port(void);
 #ifdef CONFIG_RX65N_SCI8
 void sci8_init_port(void);
 #endif
+
+/****************************************************************************
+ * Name: rspi_pinconfig
+ *
+ * Description: RSPI pinconfiguration for channel
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Description:
+ *RSPI pin(SCK,MOSI and MISO) configuration
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_RSPI
+  void rspi_pinconfig(int bus);
+#endif
+
 /****************************************************************************
  * Name: riic0_init_port
  *

boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c

@@ -51,6 +51,11 @@
 #  include "rx65n_dtc.h"
 #endif
 
+#ifdef HAVE_RSPI_DRIVER
+#  include <nuttx/spi/spi_transfer.h>
+#  include "rx65n_rspi.h"
+#endif
+
 #ifdef HAVE_RIIC_DRIVER
 #  include <nuttx/i2c/i2c_master.h>
 #  include "rx65n_riic.h"
@@ -59,6 +64,80 @@
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: rx65n_rspi_initialize
+ *
+ * Description:
+ *   Initialize and register the RSPI driver.
+ *
+ ****************************************************************************/
+#ifdef CONFIG_RX65N_RSPI
+static void rx65n_rspi_initialize(void)
+{
+  int ret;
+#ifdef CONFIG_RX65N_RSPI0
+  struct spi_dev_s *rspi0;
+#endif
+#ifdef CONFIG_RX65N_RSPI1
+  struct spi_dev_s *rspi1;
+#endif
+#ifdef CONFIG_RX65N_RSPI2
+  struct spi_dev_s *rspi2;
+#endif
+
+#ifdef CONFIG_RX65N_RSPI0
+  rspi0 = rx65n_rspibus_initialize(0);
+  if (!rspi0)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 0\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi0, 0);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 0\n");
+    }
+#endif
+
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+  rspi1 = rx65n_rspibus_initialize(1);
+  if (!rspi1)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 1\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi1, 1);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 1\n");
+    }
+#endif
+
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+  rspi2 = rx65n_rspibus_initialize(2);
+  if (!rspi2)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 2\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi2, 2);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 2\n");
+    }
+#endif
+
+#endif
+}
+#endif
+
 /****************************************************************************
  * Name: rtc_driver_initialize
  *
@@ -150,6 +229,11 @@ int rx65n_bringup(void)
 
   (void)rx65n_dtc_initialize();
 #endif
+
+#ifdef CONFIG_RX65N_RSPI
+  (void)rx65n_rspi_initialize();
+#endif
+
 #if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
   /* Initialize CDCACM */
 

boards/renesas/rx65n/rx65n-grrose/src/rx65n_gpio.c

@@ -356,6 +356,106 @@ inline void sci8_init_port(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: rspi_pinconfig
+ *
+ * Description: RSPI pinconfiguration for channel
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Description:
+ *RSPI pin(SCK,MOSI and MISO) configuration
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_RSPI
+void rspi_pinconfig(int bus)
+{
+  /* Set RSPI signal ports to peripheral mode */
+
+  switch (bus)
+    {
+      case RX65N_RSPI_CHANNEL0:
+#ifdef CONFIG_RX65N_RSPI0
+
+        /* Configure RSPCKA */
+
+        MPC.PC5PFS.BYTE = 0x0d;
+        PORTC.PMR.BIT.B5 = 1;
+
+        /* Configure MOSIA */
+
+        MPC.PC6PFS.BYTE = 0x0d; /* This config will block SCI8 function */
+        PORTC.PMR.BIT.B6 = 1;
+
+        /* Configure MISOA */
+
+        MPC.PC7PFS.BYTE = 0x0d; /* This config will block SCI8 function */
+        PORTC.PMR.BIT.B7 = 1;
+
+        /* Configure SSLA0 */
+
+        MPC.PC4PFS.BYTE = 0x0d;
+        PORTC.PMR.BIT.B4 = 1;
+#endif
+        break;
+
+      case RX65N_RSPI_CHANNEL1:
+#ifdef CONFIG_RX65N_RSPI1
+
+        /* Configure RSPCKB */
+
+        MPC.PE5PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B5 = 1;
+
+        /* Configure MOSIB */
+
+        MPC.PE6PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B6 = 1;
+
+        /* Configure MISOB */
+
+        MPC.PE7PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B7 = 1;
+
+        /* Configure SSLB0 */
+
+        MPC.PE4PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B4 = 1;
+#endif
+        break;
+
+    case RX65N_RSPI_CHANNEL2:
+#ifdef CONFIG_RX65N_RSPI2
+
+        /* Configure RSPCKC */
+
+        MPC.PD3PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B3 = 1;
+
+        /* Configure MOSIC */
+
+        MPC.PD1PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B1 = 1;
+
+        /* Configure MISOC */
+
+        MPC.PD2PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B2 = 1;
+
+        /* Configure SSLC0 */
+
+        MPC.PD4PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B4 = 1;
+#endif
+        break;
+
+      default:
+        break;
+    }
+}
+#endif
+
 /****************************************************************************
  * Name: riic0_init_port
  *

boards/renesas/rx65n/rx65n-rsk2mb/README.txt

@@ -13,6 +13,9 @@ Contents
   - Networking
   - RTC
   - USB Device
+  - RSPI
+  - RIIC
+  - DTC
   - Debugging
 
 Board Features
@@ -180,6 +183,16 @@ Configure UDP blaster application as mentioned below :
 CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801  (10.75.24.1) ------> Gateway IP
 CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask
 CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP
+
+RSPI
+-----------
+
+For RX65N RSK2MB board, Following pin is configured for all channels in JA3.
+Channel0: Pin number 7 and 8 in JA3 is used for MOSIA and MISOA respectively
+Channel1: Pin number 35 and 36 in JA3 is used for MOSIB and MISOB respectively
+Channel2: Pin number 18 and 19 in JA3 is used for MOSIC and MISOC respectively
+and for enabling these pin need to select DSW-SEL0 by making off SW4-4
+
 RTC
 ==========
 
@@ -216,6 +229,49 @@ xd 0 0x20000 > /dev/ttyACM0
 
 The output of the commands mentioned above should be seen on the USB Device COM port on teraterm
 
+RSPI Configurations
+--------------------------
+The following configurations need to be enabled for RSPI
+
+CONFIG_SYSTEM_SPITOOL=y
+
+RSPI Testing
+------------------------
+The following testing is executed as part of RSPI testing on RX65N target for RSK2MB board
+
+On RSK2MB board, all three channels 0, 1 and 2 has been brought out and tested.
+
+Following command can be used for testing RSPI communication to slave device.
+spi exch -b 0 -x 4 aabbccdd
+where b is bus number and x is Number of word to exchange.
+
+RIIC Configurations
+--------------------------
+The following configurations need to be enabled for RIIC.
+
+CONFIG_SYSTEM_I2CTOOL=y
+
+RIIC Testing
+------------------------
+The following testing is executed as part of RIIC testing on RX65N target for RSK2MB board
+
+On RSK2MB board only channel 0 can be tested.
+
+Following command can be used for testing RIIC communication with slave device.
+i2c set -b 0 -a 53 -r 0 10
+where b is bus number, a is the slave address, r is the register address and 10 is the value to be written.
+
+DTC Configurations
+--------------------------
+The following configurations need to be enabled for DTC.
+
+CONFIG_SYSTEM_SPITOOL=y
+
+DTC Testing
+------------------------
+
+DTC has been tested using RSPI driver.
+
 Debugging
 ==========
 1. NuttX needs to be compiled in Cygwin environment on Windows.

boards/renesas/rx65n/rx65n-rsk2mb/include/rx65n_gpio.h

@@ -49,6 +49,16 @@
   #define RX65N_MAC_ADDRH 0x00000000
 #endif
 
+/* RSPI channel number */
+
+#define RX65N_RSPI_CHANNEL0 0
+#define RX65N_RSPI_CHANNEL1 1
+#define RX65N_RSPI_CHANNEL2 2
+
+/* DSW_SEL0 hardware setting in RSK2MB baord accordingly change this macro */
+
+#define DSW_SEL0_ON 0 /* 1 means ON and 0 means OFF*/
+
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
@@ -192,6 +202,23 @@ void sci8_init_port(void);
 #ifdef CONFIG_RX65N_SCI12
 void sci12_init_port(void);
 #endif
+
+/****************************************************************************
+ * Name: rspi_pinconfig
+ *
+ * Description: RSPI pinconfiguration for channel
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Description:
+ *RSPI pin(SCK,MOSI and MISO) configuration
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_RSPI
+void rspi_pinconfig(int bus);
+#endif
+
 /****************************************************************************
  * Name: riic0_init_port
  *

boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c

@@ -50,6 +50,12 @@
 #ifdef HAVE_DTC_DRIVER
 #  include "rx65n_dtc.h"
 #endif
+
+#ifdef HAVE_RSPI_DRIVER
+#  include <nuttx/spi/spi_transfer.h>
+#  include "rx65n_rspi.h"
+#endif
+
 #ifdef HAVE_RIIC_DRIVER
 #  include <nuttx/i2c/i2c_master.h>
 #  include "rx65n_riic.h"
@@ -58,6 +64,80 @@
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: rx65n_rspi_initialize
+ *
+ * Description:
+ *   Initialize and register the RSPI driver.
+ *
+ ****************************************************************************/
+#ifdef CONFIG_RX65N_RSPI
+static void rx65n_rspi_initialize(void)
+{
+  int ret;
+#ifdef CONFIG_RX65N_RSPI0
+  struct spi_dev_s *rspi0;
+#endif
+#ifdef CONFIG_RX65N_RSPI1
+  struct spi_dev_s *rspi1;
+#endif
+#ifdef CONFIG_RX65N_RSPI2
+  struct spi_dev_s *rspi2;
+#endif
+
+#ifdef CONFIG_RX65N_RSPI0
+  rspi0 = rx65n_rspibus_initialize(0);
+  if (!rspi0)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 0\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi0, 0);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 0\n");
+    }
+#endif
+
+#endif
+
+#ifdef CONFIG_RX65N_RSPI1
+  rspi1 = rx65n_rspibus_initialize(1);
+  if (!rspi1)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 1\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi1, 1);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 1\n");
+    }
+#endif
+
+#endif
+
+#ifdef CONFIG_RX65N_RSPI2
+  rspi2 = rx65n_rspibus_initialize(2);
+  if (!rspi2)
+    {
+      spierr("ERROR: [boot] FAILED to initialize SPI port 2\n");
+    }
+
+#ifdef CONFIG_SPI_DRIVER
+  ret = spi_register(rspi2, 2);
+  if (ret < 0)
+    {
+      spierr("ERROR: [boot] FAILED to register driver for channel 2\n");
+    }
+#endif
+
+#endif
+}
+#endif
+
 /****************************************************************************
  * Name: rtc_driver_initialize
  *
@@ -149,6 +229,11 @@ int rx65n_bringup(void)
 
   (void)rx65n_dtc_initialize();
 #endif
+
+#ifdef CONFIG_RX65N_RSPI
+  (void)rx65n_rspi_initialize();
+#endif
+
 #if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
   /* Initialize CDCACM */
 

boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_gpio.c

@@ -321,6 +321,147 @@ inline void sci12_init_port(void)
 }
 #endif
 
+/****************************************************************************
+ * Name: rspi_pinconfig
+ *
+ * Description: RSPI pinconfiguration for channel
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple SPI interfaces)
+ *
+ * Description:
+ *RSPI pin(SCK,MOSI and MISO) configuration
+ ****************************************************************************/
+
+#ifdef CONFIG_RX65N_RSPI
+void rspi_pinconfig(int bus)
+{
+  /* Set RSPI signal ports to peripheral mode */
+
+  switch (bus)
+    {
+      case RX65N_RSPI_CHANNEL0:
+#ifdef CONFIG_RX65N_RSPI0
+
+        /* Configure RSPCKA */
+
+        MPC.PA5PFS.BYTE = 0x0d;
+        PORTA.PMR.BIT.B5 = 1;
+
+        /* Configure MOSIA */
+
+        MPC.PA6PFS.BYTE = 0x0d;
+        PORTA.PMR.BIT.B6 = 1;
+
+        /* Configure MISOA */
+
+        MPC.PA7PFS.BYTE = 0x0d;
+        PORTA.PMR.BIT.B7 = 1;
+
+        /* Configure SSLA0 */
+
+        MPC.PA4PFS.BYTE = 0x0d;
+        PORTC.PMR.BIT.B4 = 1;
+#endif
+        break;
+
+      case RX65N_RSPI_CHANNEL1:
+#ifdef CONFIG_RX65N_RSPI1
+
+        /* Configure RSPCKB */
+
+#if DSW_SEL0_ON
+        MPC.P27PFS.BYTE = 0x0d;
+        PORT2.PMR.BIT.B7 = 1;
+#else
+        MPC.PE5PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B5 = 1;
+#endif
+
+        /* Configure MOSIB */
+
+#if DSW_SEL0_ON
+        MPC.P26PFS.BYTE = 0x0d;
+        PORT2.PMR.BIT.B6 = 1;
+#else
+        MPC.PE6PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B6 = 1;
+#endif
+
+        /* Configure MISOB */
+
+#if DSW_SEL0_ON
+        MPC.P30PFS.BYTE = 0x0d;
+        PORT3.PMR.BIT.BT0 = 1;
+#else
+        MPC.PE7PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B7 = 1;
+#endif
+
+        /* Configure SSLB0 */
+
+#if DSW_SEL0_ON
+        MPC.P57PFS.BYTE = 0x0d;
+        PORT5.PMR.BIT.B7 = 1;
+#else
+        MPC.PE4PFS.BYTE = 0x0d;
+        PORTE.PMR.BIT.B4 = 1;
+#endif
+
+#endif
+        break;
+
+      case RX65N_RSPI_CHANNEL2:
+#ifdef CONFIG_RX65N_RSPI2
+
+        /* Configure RSPCKC */
+
+#if DSW_SEL0_ON
+        MPC.P56PFS.BYTE = 0x0d;
+        PORT5.PMR.BIT.B6 = 1;
+#else
+        MPC.PD3PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B3 = 1;
+#endif
+        /* Configure MOSIC */
+
+#if DSW_SEL0_ON
+        MPC.P54PFS.BYTE = 0x0d;
+        PORT5.PMR.BIT.B4 = 1;
+#else
+        MPC.PD1PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B1 = 1;
+#endif
+
+        /* Configure MISOC */
+
+#if DSW_SEL0_ON
+        MPC.P55PFS.BYTE = 0x0d;
+        PORT5.PMR.BIT.B5 = 1;
+#else
+        MPC.PD2PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B2 = 1;
+#endif
+
+        /* Configure SSLC0 */
+
+#if DSW_SEL0_ON
+        MPC.P57PFS.BYTE = 0x0d;
+        PORT5.PMR.BIT.B7 = 1;
+#else
+        MPC.PD4PFS.BYTE = 0x0d;
+        PORTD.PMR.BIT.B4 = 1;
+#endif
+
+#endif
+        break;
+
+      default:
+        break;
+    }
+}
+#endif 
+
 /****************************************************************************
  * Name: riic0_init_port
  *