diff --git a/arch/arm/src/sam34/hardware/sam_hsmci.h b/arch/arm/src/sam34/hardware/sam_hsmci.h
index 006446ace9c..b58b09dc554 100644
--- a/arch/arm/src/sam34/hardware/sam_hsmci.h
+++ b/arch/arm/src/sam34/hardware/sam_hsmci.h
@@ -57,7 +57,7 @@
 #define SAM_HSMCI_IDR_OFFSET          0x0048 /* Interrupt Disable Register */
 #define SAM_HSMCI_IMR_OFFSET          0x004c /* Interrupt Mask Register */
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #  define SAM_HSMCI_DMA_OFFSET        0x0050 /* DMA Configuration Register */
 #endif
 
@@ -90,7 +90,7 @@
 #define SAM_HSMCI_IDR                 (SAM_HSMCI_BASE+SAM_HSMCI_IDR_OFFSET)
 #define SAM_HSMCI_IMR                 (SAM_HSMCI_BASE+SAM_HSMCI_IMR_OFFSET)
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #  define SAM_HSMCI_DMA               (SAM_HSMCI_BASE+SAM_HSMCI_DMA_OFFSET)
 #endif
 
@@ -140,7 +140,7 @@
 #  define HSMCI_MR_PDCMODE            (1 << 15) /* Bit 15: PDC-oriented Mode */
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #  define HSMCI_MR_BLKLEN_SHIFT       (16)      /* Bits 16-31: Data Block Length */
 #  define HSMCI_MR_BLKLEN_MASK        (0xffff << HSMCI_MR_BLKLEN_SHIFT)
 #endif
@@ -297,7 +297,7 @@
 #define HSMCI_INT_DTOE                (1 << 22) /* Bit 22: Data Time-out Error */
 #define HSMCI_INT_CSTOE               (1 << 23) /* Bit 23: Completion Signal Time-out Error */
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #  define HSMCI_INT_BLKOVRE           (1 << 24) /* Bit 24: DMA Block Overrun Error */
 #  define HSMCI_INT_DMADONE           (1 << 25) /* Bit 25: DMA Transfer done */
 #endif
@@ -311,7 +311,7 @@
 
 /* HSMCI DMA Configuration Register */
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #  define HSMCI_DMA_OFFSET_SHIFT      (0)       /* Bits 0-1: DMA Write Buffer Offset */
 #  define HSMCI_DMA_OFFSET_MASK       (3 << HSMCI_DMA_OFFSET_SHIFT)
 #  define HSMCI_DMA_CHKSIZE           (1 << 4)  /* Bit 4:  DMA Channel Read and Write Chunk Size */
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index 602d6854e94..5363ec426cc 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -187,7 +187,7 @@
  */
 
 #ifdef CONFIG_SAM34_DMAC0
-#  if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #    define HSMCI_DATA_ERRORS \
        (HSMCI_INT_UNRE | HSMCI_INT_OVRE  | HSMCI_INT_BLKOVRE | HSMCI_INT_CSTOE | \
         HSMCI_INT_DTOE | HSMCI_INT_DCRCE)
@@ -206,7 +206,7 @@
   (HSMCI_INT_CSTOE | HSMCI_INT_DTOE)
 
 #ifdef CONFIG_SAM34_DMAC0
-#  if defined(CONFIG_ARCH_CHIP_SAM3U)
+#  if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
 #    define HSMCI_DATA_DMARECV_ERRORS \
       (HSMCI_INT_OVRE  | HSMCI_INT_BLKOVRE | HSMCI_INT_CSTOE | HSMCI_INT_DTOE | \
        HSMCI_INT_DCRCE)
@@ -355,7 +355,7 @@ struct sam_hsmciregs_s
   uint32_t rsp3;     /* Response Register 3 */
   uint32_t sr;       /* Status Register */
   uint32_t imr;      /* Interrupt Mask Register */
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   uint32_t dma;      /* DMA Configuration Register */
 #endif
   uint32_t cfg;      /* Configuration Register */
@@ -784,7 +784,7 @@ static void sam_hsmcisample(struct sam_hsmciregs_s *regs)
   regs->rsp3     = getreg32(SAM_HSMCI_RSPR3);
   regs->sr       = getreg32(SAM_HSMCI_SR);
   regs->imr      = getreg32(SAM_HSMCI_IMR);
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   regs->dma      = getreg32(SAM_HSMCI_DMA);
 #endif
   regs->cfg      = getreg32(SAM_HSMCI_CFG);
@@ -844,7 +844,7 @@ static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg)
          SAM_HSMCI_SR, regs->sr);
   mcinfo("    IMR[%08x]: %08x\n",
          SAM_HSMCI_IMR, regs->imr);
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   mcinfo("    DMA[%08x]: %08x\n",
          SAM_HSMCI_DMA, regs->dma);
 #endif
@@ -1182,7 +1182,7 @@ static void sam_endtransfer(struct sam_dev_s *priv,
   sam_dmastop(priv->dma);
   priv->dmabusy = false;
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   /* Disable the DMA handshaking */
 
   putreg32(0, SAM_HSMCI_DMA);
@@ -1225,7 +1225,7 @@ static void sam_notransfer(struct sam_dev_s *priv)
 
   regval = getreg32(SAM_HSMCI_MR);
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF | HSMCI_MR_BLKLEN_MASK);
 #else
   regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF);
@@ -1437,7 +1437,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
 
   /* Disable the DMA interface */
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   putreg32(0, SAM_HSMCI_DMA);
 #endif
 
@@ -1849,7 +1849,7 @@ static void sam_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
 
   regval = getreg32(SAM_HSMCI_MR);
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF | HSMCI_MR_BLKLEN_MASK);
   regval |= HSMCU_PROOF_BITS;
   regval |= (blocklen << HSMCI_MR_BLKLEN_SHIFT);
@@ -1916,7 +1916,7 @@ static int sam_cancel(FAR struct sdio_dev_s *dev)
   priv->dmabusy = false;
 #endif
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   /* Disable the DMA handshaking */
 
   putreg32(0, SAM_HSMCI_DMA);
@@ -2510,7 +2510,7 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
 
   sam_cmcc_invalidate((uintptr_t)buffer, (uintptr_t)buffer + buflen);
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   /* Enable DMA handshaking */
 
   putreg32(HSMCI_DMA_DMAEN, SAM_HSMCI_DMA);
@@ -2580,7 +2580,7 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev,
 
   sam_dmatxsetup(priv->dma, SAM_HSMCI_TDR, (uint32_t)buffer, buflen);
 
-#if defined(CONFIG_ARCH_CHIP_SAM3U)
+#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X)
   /* Enable DMA handshaking */
 
   putreg32(HSMCI_DMA_DMAEN, SAM_HSMCI_DMA);