diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S
index 07115b193ef..0b2983d1dc5 100644
--- a/arch/risc-v/src/bl602/bl602_head.S
+++ b/arch/risc-v/src/bl602/bl602_head.S
@@ -126,20 +126,6 @@ bl602_entry_zero_wifi_bss_loop:
     bltu a0, a1, bl602_entry_zero_wifi_bss_loop
 bl602_entry_zero_wifi_bss_end:
 
-#ifndef __riscv_float_abi_soft
-
-    /* Enable FPU */
-
-    li t0, MSTATUS_FS
-    csrs mstatus, t0
-    csrr t1, mstatus
-    and t1, t1, t0
-    beqz t1, bl602_entry_enable_fpu_end
-    fssr x0
-
-bl602_entry_enable_fpu_end:
-#endif
-
     auipc ra, 0
     addi sp, sp, -16
     sw ra, 8(sp)
diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c
index f90bf8ed109..9bad097c07e 100644
--- a/arch/risc-v/src/bl602/bl602_start.c
+++ b/arch/risc-v/src/bl602/bl602_start.c
@@ -160,6 +160,10 @@ __cyg_profile_func_exit(void *this_fn, void *call_site)
 
 void bfl_main(void)
 {
+  /* Configure FPU */
+
+  riscv_fpuconfig();
+
   /* set interrupt vector */
 
   asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
diff --git a/arch/risc-v/src/c906/c906_head.S b/arch/risc-v/src/c906/c906_head.S
index 4bc4999de85..22c5a5d838d 100644
--- a/arch/risc-v/src/c906/c906_head.S
+++ b/arch/risc-v/src/c906/c906_head.S
@@ -52,13 +52,6 @@ __start:
 
   sfence.vma x0,x0
 
-  /* enable FPU if CFLAGS has 'f' or 'd' in -march */
-
-#ifdef __riscv_flen
-    li      a0, MSTATUS_FS_INIT
-    csrs    mstatus, a0
-#endif
-
   /* enable thead ISA extension:
    * BIT22: enable the THEAD ISA extensions.
    * BIT21: enable extended attributes in PTE.
diff --git a/arch/risc-v/src/c906/c906_start.c b/arch/risc-v/src/c906/c906_start.c
index 6f2868320c3..3d53297e049 100644
--- a/arch/risc-v/src/c906/c906_start.c
+++ b/arch/risc-v/src/c906/c906_start.c
@@ -73,6 +73,10 @@ void __c906_start(uint32_t mhartid)
   const uint32_t *src;
   uint32_t *dest;
 
+  /* Configure FPU */
+
+  riscv_fpuconfig();
+
   if (0 != mhartid)
     {
       while (true);
diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S
index 94baa804d5e..ffaad627529 100755
--- a/arch/risc-v/src/mpfs/mpfs_head.S
+++ b/arch/risc-v/src/mpfs/mpfs_head.S
@@ -116,20 +116,15 @@ __start:
 
   sfence.vma x0, x0
 
-  /* enable FPU and accelerator if present, setting ignored on E51
+  /* Enable accelerator if present, setting ignored on E51
    * 15,16 = MSTATUS_XS, 17,18 = MSTATUS_MPRV
    * not defined on riscv-v/include/csr.h
    */
 
-  /*  li      t0, MSTATUS_FS_DIRTY | (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18) */
-  li t0, 0x00006000 | 0x00018000 /* MSTATUS_FS | MSTATUS_XS */
+  /*  li      t0, (1 << 15) | (1 << 16) | (1 << 17) | (1 << 18) */
+  li t0, 0x00018000 /* MSTATUS_XS */
   csrs    mstatus, t0
 
-  /* Init floating point control register to zero */
-#ifdef __riscv_flen
-    fscsr x0
-#endif
-
 .skip_e51:
 
 /* initialize global pointer, global data
diff --git a/arch/risc-v/src/mpfs/mpfs_start.c b/arch/risc-v/src/mpfs/mpfs_start.c
index d197c0156d4..ea4e004dd23 100755
--- a/arch/risc-v/src/mpfs/mpfs_start.c
+++ b/arch/risc-v/src/mpfs/mpfs_start.c
@@ -116,6 +116,13 @@ void __mpfs_start(uint64_t mhartid)
   const uint32_t *src;
   uint32_t *dest;
 
+  /* Configure FPU (hart 0 don't have an FPU) */
+
+  if (mhartid != 0)
+    {
+      riscv_fpuconfig();
+    }
+
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c
index 9e612e51449..f1a9f4e73d7 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_start.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_start.c
@@ -63,6 +63,10 @@ void qemu_rv_start(int mhartid)
 {
   uint32_t *dest;
 
+  /* Configure FPU */
+
+  riscv_fpuconfig();
+
   if (mhartid > 0)
     {
       goto cpux;