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Fix ording of bytes in ENC28J60 MAC address; Web server refactoring from Kate

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5159 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-09-18 12:34:43 +00:00
parent c4b2ce70ba
commit 8f3559bd34
2 changed files with 17 additions and 10 deletions
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drivers/net/enc28j60.c
+14 -7
View File
@@ -2244,14 +2244,21 @@ static void enc_pwrfull(FAR struct enc_driver_s *priv)
static void enc_setmacaddr(FAR struct enc_driver_s *priv) static void enc_setmacaddr(FAR struct enc_driver_s *priv)
{ {
/* Program the hardware with it's MAC address (for filtering) */ /* Program the hardware with it's MAC address (for filtering).
* MAADR1 MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1
* MAADR2 MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2
* MAADR3 MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3
* MAADR4 MAC Address Byte 4 (MAADR<23:16>)
* MAADR5 MAC Address Byte 5 (MAADR<15:8>)
* MAADR6 MAC Address Byte 6 (MAADR<7:0>)
*/
enc_wrbreg(priv, ENC_MAADR1, priv->dev.d_mac.ether_addr_octet[5]); enc_wrbreg(priv, ENC_MAADR1, priv->dev.d_mac.ether_addr_octet[0]);
enc_wrbreg(priv, ENC_MAADR2, priv->dev.d_mac.ether_addr_octet[4]); enc_wrbreg(priv, ENC_MAADR2, priv->dev.d_mac.ether_addr_octet[1]);
enc_wrbreg(priv, ENC_MAADR3, priv->dev.d_mac.ether_addr_octet[3]); enc_wrbreg(priv, ENC_MAADR3, priv->dev.d_mac.ether_addr_octet[2]);
enc_wrbreg(priv, ENC_MAADR4, priv->dev.d_mac.ether_addr_octet[2]); enc_wrbreg(priv, ENC_MAADR4, priv->dev.d_mac.ether_addr_octet[3]);
enc_wrbreg(priv, ENC_MAADR5, priv->dev.d_mac.ether_addr_octet[1]); enc_wrbreg(priv, ENC_MAADR5, priv->dev.d_mac.ether_addr_octet[4]);
enc_wrbreg(priv, ENC_MAADR6, priv->dev.d_mac.ether_addr_octet[0]); enc_wrbreg(priv, ENC_MAADR6, priv->dev.d_mac.ether_addr_octet[5]);
} }
/**************************************************************************** /****************************************************************************
drivers/net/enc28j60.h
+3 -3
View File
@@ -304,7 +304,7 @@
#define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */ #define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
#define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */ #define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */
#define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */ #define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */ #define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 */
#define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */ #define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
#define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */ #define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */
#define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */ #define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
@@ -361,11 +361,11 @@
/* PHY Control Register 1 Register Bit Definitions */ /* PHY Control Register 1 Register Bit Definitions */
#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */ #define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */
#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */ #define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power Save */
#define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */ #define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */
#define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */ #define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */
/* HY Status 1 Register Bit Definitions */ /* PHY Status 1 Register Bit Definitions */
#define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */ #define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */
#define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */ #define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */