Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-06 00:14:22 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

More changes, getting closer to a clean STM3240 compile

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4120 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-11-22 17:43:11 +00:00
parent 6d47e3fcb6
commit 8eabbf0a7a
5 changed files with 338 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32/chip/stm32f40xxx_dma.h
+8
View File
@@ -379,6 +379,14 @@
* sources/sinks of data. The requests from peripherals assigned to a stream * sources/sinks of data. The requests from peripherals assigned to a stream
* are simply OR'ed together before entering the DMA block. This means that only * are simply OR'ed together before entering the DMA block. This means that only
* one request on a given stream can be enabled at once. * one request on a given stream can be enabled at once.
*
* Alternative stream selections are provided with a numeric suffix like _1, _2, etc.
* The DMA driver, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* SPI3_RX connects via DMA STREAM0, then following should be application-specific
* mapping should be used:
*
* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
*/ */
#define STM32_DMA_MAP(d,c,s) ((d) << 6 | (s) << 3 | (c)) #define STM32_DMA_MAP(d,c,s) ((d) << 6 | (s) << 3 | (c))
arch/arm/src/stm32/chip/stm32f40xxx_gpio.h
+1 -1
View File
@@ -320,7 +320,7 @@
/* GPIO port bit set/reset register */ /* GPIO port bit set/reset register */
#define GPIO_BSRR_SET(n) (1 << (n)) #define GPIO_BSRR_SET(n) (1 << (n))
#define GPIO_BSRR_RESET(n) (1 << ((n)+16) #define GPIO_BSRR_RESET(n) (1 << ((n)+16))
/* GPIO port configuration lock register */ /* GPIO port configuration lock register */
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
+2
View File
@@ -294,6 +294,7 @@
/* AHB1 Peripheral Clock enable register */ /* AHB1 Peripheral Clock enable register */
#define RCC_AH1BENR_GPIOEN(n) (1 << (n))
#define RCC_AH1BENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */ #define RCC_AH1BENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
#define RCC_AH1BENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */ #define RCC_AH1BENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
#define RCC_AH1BENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */ #define RCC_AH1BENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
@@ -371,6 +372,7 @@
/* RCC AHB1 low power modeperipheral clock enable register */ /* RCC AHB1 low power modeperipheral clock enable register */
#define RCC_AH1BLPENR_GPIOLPEN(n) (1 << (n))
#define RCC_AH1BLPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */ #define RCC_AH1BLPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
#define RCC_AH1BLPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */ #define RCC_AH1BLPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
#define RCC_AH1BLPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */ #define RCC_AH1BLPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
arch/arm/src/stm32/stm32_flash.c
+110 -89
View File
@@ -52,8 +52,11 @@
#include "stm32_flash.h" #include "stm32_flash.h"
#include "stm32_rcc.h" #include "stm32_rcc.h"
#include "stm32_waste.h" #include "stm32_waste.h"
#include "up_arch.h" #include "up_arch.h"
#ifdef CONFIG_STM32_STM32F10XX
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
@@ -67,158 +70,176 @@
void stm32_flash_unlock(void) void stm32_flash_unlock(void)
{ {
while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste(); while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
up_waste();
}
if ( getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK ) { if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
{
/* Unlock sequence */
/* Unlock sequence */ putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
putreg32(FLASH_KEY1, STM32_FLASH_KEYR);
putreg32(FLASH_KEY2, STM32_FLASH_KEYR);
} }
} }
void stm32_flash_lock(void) void stm32_flash_lock(void)
{ {
modifyreg16(STM32_FLASH_CR, 0, FLASH_CR_LOCK); modifyreg16(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
} }
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions
************************************************************************************/ ************************************************************************************/
uint16_t up_progmem_npages(void) uint16_t up_progmem_npages(void)
{ {
return STM32_FLASH_NPAGES; return STM32_FLASH_NPAGES;
} }
bool up_progmem_isuniform(void) bool up_progmem_isuniform(void)
{ {
return TRUE; return true;
} }
uint16_t up_progmem_pagesize(uint16_t page) uint16_t up_progmem_pagesize(uint16_t page)
{ {
return STM32_FLASH_PAGESIZE; return STM32_FLASH_PAGESIZE;
} }
int up_progmem_getpage(uint32_t addr) int up_progmem_getpage(uint32_t addr)
{ {
if (addr >= STM32_FLASH_SIZE) if (addr >= STM32_FLASH_SIZE)
return -EFAULT; {
return -EFAULT;
}
return addr / STM32_FLASH_PAGESIZE; return addr / STM32_FLASH_PAGESIZE;
} }
int up_progmem_erasepage(uint16_t page) int up_progmem_erasepage(uint16_t page)
{ {
uint32_t addr; uint32_t addr;
uint16_t count; uint16_t count;
if (page >= STM32_FLASH_NPAGES) if (page >= STM32_FLASH_NPAGES)
return -EFAULT; {
return -EFAULT;
/* Get flash ready and begin erasing single page */
if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) )
return -EPERM;
stm32_flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER);
putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste();
modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
/* Verify */
for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
count; count-=4, addr += 4) {
if (getreg32(addr) != 0xFFFFFFFF)
return -EIO;
} }
return STM32_FLASH_PAGESIZE; /* Get flash ready and begin erasing single page */
}
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
return -EPERM;
}
stm32_flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER);
putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
/* Verify */
for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
count; count-=4, addr += 4)
{
if (getreg32(addr) != 0xffffffff)
{
return -EIO;
}
}
return STM32_FLASH_PAGESIZE;
}
int up_progmem_ispageerased(uint16_t page) int up_progmem_ispageerased(uint16_t page)
{ {
uint32_t addr; uint32_t addr;
uint16_t count; uint16_t count;
uint16_t bwritten = 0; uint16_t bwritten = 0;
if (page >= STM32_FLASH_NPAGES) if (page >= STM32_FLASH_NPAGES)
return -EFAULT; {
return -EFAULT;
/* Verify */
for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
count; count--, addr++) {
if (getreg8(addr) != 0xFF) bwritten++;
} }
return bwritten; /* Verify */
}
for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE;
count; count--, addr++)
{
if (getreg8(addr) != 0xff)
{
bwritten++;
}
}
return bwritten;
}
int up_progmem_write(uint32_t addr, const void *buf, size_t count) int up_progmem_write(uint32_t addr, const void *buf, size_t count)
{ {
uint16_t *hword = (uint16_t *)buf; uint16_t *hword = (uint16_t *)buf;
size_t written = count; size_t written = count;
/* STM32 requires half-word access */ /* STM32 requires half-word access */
if (count & 1) if (count & 1)
return -EINVAL; {
return -EINVAL;
}
/* Check for valid address range */ /* Check for valid address range */
if ( (addr+count) >= STM32_FLASH_SIZE) if ((addr+count) >= STM32_FLASH_SIZE)
return -EFAULT; {
return -EFAULT;
}
/* Get flash ready and begin flashing */ /* Get flash ready and begin flashing */
if ( !(getreg32(STM32_RCC_CR) & RCC_CR_HSION) ) if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
return -EPERM; {
return -EPERM;
}
stm32_flash_unlock(); stm32_flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) { for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2)
{
/* Write half-word and wait to complete */
/* Write half-word and wait to complete */ putreg16(*hword, addr);
putreg16(*hword, addr); while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
while( getreg32(STM32_FLASH_SR) & FLASH_SR_BSY ) up_waste(); /* Verify */
/* Verify */ if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRPRT_ERR)
{
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRPRT_ERR) { modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); return -EROFS;
return -EROFS;
} }
if (getreg16(addr) != *hword) { if (getreg16(addr) != *hword)
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); {
return -EIO; modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
return -EIO;
} }
} }
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
return written; return written;
} }
#endif /* CONFIG_STM32_STM32F10XX */
arch/arm/src/stm32/stm32_gpio.c
+202 -103
View File
@@ -45,7 +45,9 @@
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <errno.h>
#include <debug.h> #include <debug.h>
#include <arch/irq.h> #include <arch/irq.h>
#include "up_arch.h" #include "up_arch.h"
@@ -58,38 +60,41 @@
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
/* Base addresses for each GPIO block */
static const uint32_t g_gpiobase[STM32_NGPIO_PORTS] = static const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
{ {
#if STM32_NGPIO_PORTS > 0 #if STM32_NGPIO_PORTS > 0
STM32_GPIOA_BASE, STM32_GPIOA_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 1 #if STM32_NGPIO_PORTS > 1
STM32_GPIOB_BASE, STM32_GPIOB_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 2 #if STM32_NGPIO_PORTS > 2
STM32_GPIOC_BASE, STM32_GPIOC_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 3 #if STM32_NGPIO_PORTS > 3
STM32_GPIOD_BASE, STM32_GPIOD_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 4 #if STM32_NGPIO_PORTS > 4
STM32_GPIOE_BASE, STM32_GPIOE_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 5 #if STM32_NGPIO_PORTS > 5
STM32_GPIOF_BASE, STM32_GPIOF_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 6 #if STM32_NGPIO_PORTS > 6
STM32_GPIOG_BASE, STM32_GPIOG_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 7 #if STM32_NGPIO_PORTS > 7
STM32_GPIOH_BASE, STM32_GPIOH_BASE,
#endif #endif
#if STM32_NGPIO_PORTS > 8 #if STM32_NGPIO_PORTS > 8
STM32_GPIOI_BASE, STM32_GPIOI_BASE,
#endif #endif
}; };
/* Port letters for prettier debug output */
#ifdef CONFIG_DEBUG #ifdef CONFIG_DEBUG
static const char g_portchar[STM32_NGPIO_PORTS] = static const char g_portchar[STM32_NGPIO_PORTS] =
{ {
@@ -119,13 +124,20 @@ static const char g_portchar[STM32_NGPIO_PORTS] =
}; };
#endif #endif
/* Interrupt handles attached to each EXTI */
static xcpt_t stm32_exti_callbacks[16]; static xcpt_t stm32_exti_callbacks[16];
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
int stm32_gpio_configlock(uint32_t cfgset, bool altlock) /****************************************************************************
* Name: stm32_gpio_configlock (for the STM32F10xxx family
****************************************************************************/
#if defined(CONFIG_STM32_STM32F10XX)
static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
{ {
uint32_t base; uint32_t base;
uint32_t cr; uint32_t cr;
@@ -142,7 +154,7 @@ int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32_NGPIO_PORTS) if (port >= STM32_NGPIO_PORTS)
{ {
return ERROR; return -EINVAL;
} }
/* Get the port base address */ /* Get the port base address */
@@ -189,7 +201,7 @@ int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
( ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) < GPIO_CR_CNF_ALTPP || /* new state is not output ALT? */ ( ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) < GPIO_CR_CNF_ALTPP || /* new state is not output ALT? */
input ) ) /* or it is input */ input ) ) /* or it is input */
{ {
return ERROR; return -EINVAL;
} }
if (input) if (input)
@@ -279,6 +291,19 @@ int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
putreg32(regval, regaddr); putreg32(regval, regaddr);
return OK; return OK;
} }
#endif
/****************************************************************************
* Name: stm32_gpio_configlock (for the STM32F40xxx family
****************************************************************************/
#if defined(CONFIG_STM32_STM32F40XX)
static int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
{
# warning "Missing logic"
return -ENOSYS;
}
#endif
/**************************************************************************** /****************************************************************************
* Interrupt Service Routines - Dispatchers * Interrupt Service Routines - Dispatchers
@@ -417,11 +442,98 @@ static int stm32_exti1510_isr(int irq, void *context)
return stm32_exti_multiisr(irq, context, 10, 15); return stm32_exti_multiisr(irq, context, 10, 15);
} }
/****************************************************************************
* Function: stm32_gpioremap
*
* Description:
*
* Based on configuration within the .config file, this function will
* remaps positions of alternative functions.
*
****************************************************************************/
static inline void stm32_gpioremap(void)
{
#if defined(CONFIG_STM32_STM32F10XX)
/* Remap according to the configuration within .config file */
uint32_t val = 0;
#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
/* The reset default */
#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */
#elif CONFIG_STM32_JTAG_SW_ENABLE
val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */
#else
val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */
#endif
#ifdef CONFIG_STM32_TIM1_FULL_REMAP
val |= AFIO_MAPR_TIM1_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP
val |= AFIO_MAPR_TIM1_PARTREMAP;
#endif
#ifdef CONFIG_STM32_TIM2_FULL_REMAP
val |= AFIO_MAPR_TIM2_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1
val |= AFIO_MAPR_TIM2_PARTREMAP1;
#endif
#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2
val |= AFIO_MAPR_TIM2_PARTREMAP2;
#endif
#ifdef CONFIG_STM32_TIM3_FULL_REMAP
val |= AFIO_MAPR_TIM3_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP
val |= AFIO_MAPR_TIM3_PARTREMAP;
#endif
#ifdef CONFIG_STM32_TIM4_REMAP
val |= AFIO_MAPR_TIM4_REMAP;
#endif
#ifdef CONFIG_STM32_USART1_REMAP
val |= AFIO_MAPR_USART1_REMAP;
#endif
#ifdef CONFIG_STM32_USART2_REMAP
val |= AFIO_MAPR_USART2_REMAP;
#endif
#ifdef CONFIG_STM32_USART3_FULL_REMAP
val |= AFIO_MAPR_USART3_FULLREMAP;
#endif
#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP
val |= AFIO_MAPR_USART3_PARTREMAP;
#endif
#ifdef CONFIG_STM32_SPI1_REMAP
val |= AFIO_MAPR_SPI1_REMAP;
#endif
#ifdef CONFIG_STM32_SPI3_REMAP
#endif
#ifdef CONFIG_STM32_I2C1_REMAP
val |= AFIO_MAPR_I2C1_REMAP;
#endif
#ifdef CONFIG_STM32_CAN1_REMAP1
val |= AFIO_MAPR_PB89;
#endif
#ifdef CONFIG_STM32_CAN1_REMAP2
val |= AFIO_MAPR_PD01;
#endif
putreg32(val, STM32_AFIO_MAPR);
#endif
}
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Function: stm32_gpioinit * Function: stm32_gpioinit
* *
* Description: * Description:
@@ -429,84 +541,16 @@ static int stm32_exti1510_isr(int irq, void *context)
* - Remaps positions of alternative functions. * - Remaps positions of alternative functions.
* *
* Typically called from stm32_start(). * Typically called from stm32_start().
************************************************************************************/ ****************************************************************************/
void stm32_gpioinit(void) void stm32_gpioinit(void)
{ {
/* Remap according to the configuration within .config file */ /* Remap according to the configuration within .config file */
uint32_t val = 0; stm32_gpioremap();
#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
// the reset default
#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */
#elif CONFIG_STM32_JTAG_SW_ENABLE
val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */
#else
val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */
#endif
#ifdef CONFIG_STM32_TIM1_FULL_REMAP
val |= AFIO_MAPR_TIM1_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP
val |= AFIO_MAPR_TIM1_PARTREMAP;
#endif
#ifdef CONFIG_STM32_TIM2_FULL_REMAP
val |= AFIO_MAPR_TIM2_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1
val |= AFIO_MAPR_TIM2_PARTREMAP1;
#endif
#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2
val |= AFIO_MAPR_TIM2_PARTREMAP2;
#endif
#ifdef CONFIG_STM32_TIM3_FULL_REMAP
val |= AFIO_MAPR_TIM3_FULLREMAP;
#endif
#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP
val |= AFIO_MAPR_TIM3_PARTREMAP;
#endif
#ifdef CONFIG_STM32_TIM4_REMAP
val |= AFIO_MAPR_TIM4_REMAP;
#endif
#ifdef CONFIG_STM32_USART1_REMAP
val |= AFIO_MAPR_USART1_REMAP;
#endif
#ifdef CONFIG_STM32_USART2_REMAP
val |= AFIO_MAPR_USART2_REMAP;
#endif
#ifdef CONFIG_STM32_USART3_FULL_REMAP
val |= AFIO_MAPR_USART3_FULLREMAP;
#endif
#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP
val |= AFIO_MAPR_USART3_PARTREMAP;
#endif
#ifdef CONFIG_STM32_SPI1_REMAP
val |= AFIO_MAPR_SPI1_REMAP;
#endif
#ifdef CONFIG_STM32_SPI3_REMAP
#endif
#ifdef CONFIG_STM32_I2C1_REMAP
val |= AFIO_MAPR_I2C1_REMAP;
#endif
#ifdef CONFIG_STM32_CAN1_REMAP1
val |= AFIO_MAPR_PB89;
#endif
#ifdef CONFIG_STM32_CAN1_REMAP2
val |= AFIO_MAPR_PD01;
#endif
putreg32(val, STM32_AFIO_MAPR);
} }
/****************************************************************************
/************************************************************************************
* Name: stm32_configgpio * Name: stm32_configgpio
* *
* Description: * Description:
@@ -517,18 +561,18 @@ void stm32_gpioinit(void)
* *
* Returns: * Returns:
* OK on success * OK on success
* ERROR on invalid port, or when pin is locked as ALT function. * A negated errono valu on invalid port, or when pin is locked as ALT
* function.
* *
* \todo Auto Power Enable * To-Do: Auto Power Enable
************************************************************************************/ ****************************************************************************/
int stm32_configgpio(uint32_t cfgset) int stm32_configgpio(uint32_t cfgset)
{ {
return stm32_gpio_configlock(cfgset, true); return stm32_gpio_configlock(cfgset, true);
} }
/****************************************************************************
/************************************************************************************
* Name: stm32_unconfiggpio * Name: stm32_unconfiggpio
* *
* Description: * Description:
@@ -543,24 +587,29 @@ int stm32_configgpio(uint32_t cfgset)
* *
* Returns: * Returns:
* OK on success * OK on success
* ERROR on invalid port * A negated errno value on invalid port
* *
* \todo Auto Power Disable * To-Do: Auto Power Disable
************************************************************************************/ ****************************************************************************/
int stm32_unconfiggpio(uint32_t cfgset) int stm32_unconfiggpio(uint32_t cfgset)
{ {
/* Reuse port and pin number and set it to default HiZ INPUT */ /* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK; cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; #if defined(CONFIG_STM32_STM32F10XX)
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
#elif defined(CONFIG_STM32_STM32F40XX)
cfgset |= GPIO_INPUT | GPIO_FLOAT;
#else
# error "Unsupported STM32 chip"
#endif
/* \todo : Mark its unuse for automatic power saving options */ /* To-Do: Mark its unuse for automatic power saving options */
return stm32_gpio_configlock(cfgset, false); return stm32_gpio_configlock(cfgset, false);
} }
/**************************************************************************** /****************************************************************************
* Name: stm32_gpiowrite * Name: stm32_gpiowrite
* *
@@ -572,7 +621,11 @@ int stm32_unconfiggpio(uint32_t cfgset)
void stm32_gpiowrite(uint32_t pinset, bool value) void stm32_gpiowrite(uint32_t pinset, bool value)
{ {
uint32_t base; uint32_t base;
#if defined(CONFIG_STM32_STM32F10XX)
uint32_t offset; uint32_t offset;
#elif defined(CONFIG_STM32_STM32F40XX)
uint32_t bit;
#endif
unsigned int port; unsigned int port;
unsigned int pin; unsigned int pin;
@@ -589,15 +642,35 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
/* Set or clear the output on the pin */ /* Set or clear the output on the pin */
#if defined(CONFIG_STM32_STM32F10XX)
if (value) if (value)
{ {
offset = STM32_GPIO_BSRR_OFFSET; offset = STM32_GPIO_BSRR_OFFSET;
} }
else else
offset = STM32_GPIO_BRR_OFFSET;
{ {
offset = STM32_GPIO_BRR_OFFSET;
} }
putreg32((1 << pin), base + offset); putreg32((1 << pin), base + offset);
#elif defined(CONFIG_STM32_STM32F40XX)
if (value)
{
bit = GPIO_BSRR_SET(pin);
}
else
{
bit = GPIO_BSRR_RESET(pin);
}
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
#else
# error "Unsupported STM32 chip"
#endif
} }
} }
@@ -630,7 +703,7 @@ bool stm32_gpioread(uint32_t pinset)
return 0; return 0;
} }
/************************************************************************************ /****************************************************************************
* Name: stm32_gpiosetevent * Name: stm32_gpiosetevent
* *
* Description: * Description:
@@ -647,7 +720,7 @@ bool stm32_gpioread(uint32_t pinset)
* for example, be used to restore the previous handler when multiple handlers are * for example, be used to restore the previous handler when multiple handlers are
* used. * used.
* *
************************************************************************************/ ****************************************************************************/
xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func) bool event, xcpt_t func)
@@ -759,6 +832,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */ /* The following requires exclusive access to the GPIO registers */
flags = irqsave(); flags = irqsave();
#if defined(CONFIG_STM32_STM32F10XX)
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n", lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg); g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
@@ -777,6 +851,31 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" GPIO%c not enabled: APB2ENR: %08x\n", lldbg(" GPIO%c not enabled: APB2ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_APB2ENR)); g_portchar[port], getreg32(STM32_RCC_APB2ENR));
} }
#elif defined(CONFIG_STM32_STM32F40XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_APB1ENR) & RCC_AH1BENR_GPIOEN(port)) != 0)
{
lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET));
lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(STM32_GPIO_IDR_OFFSET), getreg32(STM32_GPIO_ODR_OFFSET),
getreg32(STM32_GPIO_BSRR_OFFSET), getreg32(STM32_GPIO_LCKR_OFFSET));
lldbg(" AFRH: %08x AFRL: %08x\n",
getreg32(STM32_GPIO_ARFH_OFFSET), getreg32(STM32_GPIO_AFRL_OFFSET));
}
else
{
lldbg(" GPIO%c not enabled: APB1ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_APB1ENR));
}
#else
# error "Unsupported STM32 chip"
#endif
irqrestore(flags); irqrestore(flags);
return OK; return OK;
} }