More INTC logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2991 42af7a65-404d-4744-a932-0658087f49c3

arch/avr/include/at91uc3/irq.h

@@ -106,14 +106,24 @@
  *  number takes priority."
  */
 
+/* Only 19 groups (0-18) are used with the AT91UC3A/B: */
+
+#define AVR32_IRQ_INTPRIOS      4 /* 4 interrupt priorities */
+#define AVR32_IRQ_MAXGROUPS    64 /* Architecture supports up to 64 groups */
+#define AVR32_IRQ_NGROUPS      19 /* UC3 A/B support only 19 */
+
 /* Group 0 */
 
-#define AVR32_IRQ_GROUP0       22
+#define AVR32_IRQ_BASEIRQGRP0  22
+#define AVR32_IRQ_NREQGRP0      1
+
 #define AVR32_IRQ_UC           22 /* 0 AVR32 UC CPU */
 
 /* Group 1 */
 
-#define AVR32_IRQ_GROUP1       23
+#define AVR32_IRQ_BASEIRQGRP1  23
+#define AVR32_IRQ_NREQGRP1     10
+
 #define AVR32_IRQ_EIC0         23 /* 0 External Interrupt Controller 0 */
 #define AVR32_IRQ_EIC1         24 /* 1 External Interrupt Controller 1 */
 #define AVR32_IRQ_EIC2         25 /* 2 External Interrupt Controller 2 */
@@ -127,7 +137,9 @@
 
 /* Group 2 */
 
-#define AVR32_IRQ_GROUP2       33
+#define AVR32_IRQ_BASEIRQGRP2  33
+#define AVR32_IRQ_NREQGRP2      6
+
 #define AVR32_IRQ_GPIO0        33 /* 0 General Purpose Input/Output Controller 0 */
 #define AVR32_IRQ_GPIO1        34 /* 1 General Purpose Input/Output Controller 1 */
 #define AVR32_IRQ_GPIO2        35 /* 2 General Purpose Input/Output Controller 2 */
@@ -137,7 +149,9 @@
 
 /* Group 3 */
 
-#define AVR32_IRQ_GROUP3       39
+#define AVR32_IRQ_BASEIRQGRP3  39
+#define AVR32_IRQ_NREQGRP3      6
+
 #define AVR32_IRQ_PDCA0        40 /* 0 Peripheral DMA Controller 0 */
 #define AVR32_IRQ_PDCA1        41 /* 1 Peripheral DMA Controller 1 */
 #define AVR32_IRQ_PDCA2        42 /* 2 Peripheral DMA Controller 2 */
@@ -148,74 +162,99 @@
 
 /* Group 4 */
 
-#define AVR32_IRQ_GROUP4       47
+#define AVR32_IRQ_BASEIRQGRP4  47
+#define AVR32_IRQ_NREQGRP4      1
+
 #define AVR32_IRQ_FLASHC       47 /* 0 Flash Controller */
 
 /* Group 5 */
 
-#define AVR32_IRQ_GROUP5       48
+#define AVR32_IRQ_BASEIRQGRP5  48
+#define AVR32_IRQ_NREQGRP5      1
+
 #define AVR32_IRQ_USART0       48 /* 0 Universal Synchronous/Asynchronous
                                    *   Receiver/Transmitter 0 */
 /* Group 6 */
 
-#define AVR32_IRQ_GROUP6       49
+#define AVR32_IRQ_BASEIRQGRP6  49
+#define AVR32_IRQ_NREQGRP6      1
+
 #define AVR32_IRQ_USART1       49 /* 0 Universal Synchronous/Asynchronous
                                    *   Receiver/Transmitter 1 */
 /* Group 7 */
 
-#define AVR32_IRQ_GROUP7       50
+#define AVR32_IRQ_BASEIRQGRP7  50
+#define AVR32_IRQ_NREQGRP7      1
+
 #define AVR32_IRQ_USART2       50 /* 0 Universal Synchronous/Asynchronous
                                    *   Receiver/Transmitter 2 */
 
-#define AVR32_IRQ_GROUP8       51
+#define AVR32_IRQ_BASEIRQGRP8  51
+#define AVR32_IRQ_NREQGRP8      0
 
 /* Group 9 */
 
-#define AVR32_IRQ_GROUP9       51
+#define AVR32_IRQ_BASEIRQGRP9  51
+#define AVR32_IRQ_NREQGRP9      1
+
 #define AVR32_IRQ_SPI          51 /* 0 Serial Peripheral Interface */
 
-#define AVR32_IRQ_GROUP10      52
+#define AVR32_IRQ_BASEIRQGRP10 52
+#define AVR32_IRQ_NREQGRP10     0
 
 /* Group 11 */
 
-#define AVR32_IRQ_GROUP11      52
+#define AVR32_IRQ_BASEIRQGRP11 52
+#define AVR32_IRQ_NREQGRP11     1
+
 #define AVR32_IRQ_TWI          52 /* 0 Two-wire Interface TWI */
 
 /* Group 12 */
 
-#define AVR32_IRQ_GROUP12      53
+#define AVR32_IRQ_BASEIRQGRP12 53
+#define AVR32_IRQ_NREQGRP12    1
+
 #define AVR32_IRQ_PWM          53 /* 0 Pulse Width Modulation Controller */
 
 /* Group 13 */
 
-#define AVR32_IRQ_GROUP13      54
+#define AVR32_IRQ_BASEIRQGRP13 54
+#define AVR32_IRQ_NREQGRP13     1
+
 #define AVR32_IRQ_SSC          54 /* 0 Synchronous Serial Controller */
 
 /* Group 14 */
 
-#define AVR32_IRQ_GROUP14      55
+#define AVR32_IRQ_BASEIRQGRP14 55
+#define AVR32_IRQ_NREQGRP14     3
+
 #define AVR32_IRQ_TC0          55 /* 0 Timer/Counter 0 */
 #define AVR32_IRQ_TC1          56 /* 1 Timer/Counter 1 */
 #define AVR32_IRQ_TC2          57 /* 2 Timer/Counter 2 */
 
 /* Group 15 */
 
-#define AVR32_IRQ_GROUP15      58
+#define AVR32_IRQ_BASEIRQGRP15 58
+#define AVR32_IRQ_NREQGRP15     1
+
 #define AVR32_IRQ_ADC          58 /* 0 Analog to Digital Converter */
 
-#define AVR32_IRQ_GROUP16      59
+#define AVR32_IRQ_BASEIRQGRP16 59
+#define AVR32_IRQ_NREQGRP16     0
 
 /* Group 17 */
 
-#define AVR32_IRQ_GROUP17      59
+#define AVR32_IRQ_BASEIRQGRP17 59
+#define AVR32_IRQ_NREQGRP17     1
+
 #define AVR32_IRQ_USBB         59 /* 0 USB 2.0 Interface USBB */
 
 /* Group 18 */
 
-#define AVR32_IRQ_GROUP18      60
+#define AVR32_IRQ_BASEIRQGRP18 60
-#define AVR32_IRQ_ABDAC        60 /* 0 Audio Bitstream DAC */
+#define AVR32_IRQ_NREQGRP18     1
 
-#define AVR32_IRQ_GROUP10      61
+#define AVR32_IRQ_ABDAC        60 /* 0 Audio Bitstream DAC */
 
 /* Total number of IRQ numbers */
 

arch/avr/src/at91uc3/at91uc3_intc.h

@@ -48,38 +48,39 @@
 
 /* Register offsets *****************************************************************/
 
-#define AVR32_INTC_PRIO_OFFSET(n)  ((n) << 2)           /* Interrupt priority registers */
+#define AVR32_INTC_IPR_OFFSET(n)  ((n) << 2)           /* Interrupt priority registers */
-#define AVR32_INTC_REQ_OFFSET(n)   (0x100 + ((n) << 2)) /* Interrupt request registers */
+#define AVR32_INTC_IRR_OFFSET(n)  (0x100 + ((n) << 2)) /* Interrupt request registers */
-#define AVR32_INTC_CAUSE_OFFSET(n) (0x20c - ((n) << 2)) /* Interrupt cause registers */
+#define AVR32_INTC_ICR_OFFSET(n)  (0x20c - ((n) << 2)) /* Interrupt cause registers */
 
 /* Register Addresses ***************************************************************/
 
-#define AVR32_INTC_PRIO(n)         (AVR32_INTC_BASE+AVR32_INTC_PRIO_OFFSET(n))
+#define AVR32_INTC_IPR(n)         (AVR32_INTC_BASE+AVR32_INTC_IPR_OFFSET(n))
-#define AVR32_INTC_REQ(n)          (AVR32_INTC_BASE+AVR32_INTC_REQ_OFFSET(n))
+#define AVR32_INTC_IRR(n)         (AVR32_INTC_BASE+AVR32_INTC_IRR_OFFSET(n))
-#define AVR32_INTC_CAUSE(n)        (AVR32_INTC_BASE+AVR32_INTC_CAUSE_OFFSET(n))
+#define AVR32_INTC_ICR(n)         (AVR32_INTC_BASE+AVR32_INTC_ICR_OFFSET(n))
 
 /* Register Bit-field Definitions ***************************************************/
 
 /* Interrupt priority register bit-field definitions */
 
-#define INTC_PRIO_AUTOVECTOR_SHIFT (0)       /* Bits 0-13: Autovector address */
+#define INTC_IPR_AUTOVECTOR_SHIFT (0)       /* Bits 0-13: Autovector address */
-#define INTC_PRIO_AUTOVECTOR_MASK  (0x3fff << INTC_PRIO_AUTOVECTOR_SHIFT)
+#define INTC_IPR_AUTOVECTOR_MASK  (0x3fff << INTC_IPR_AUTOVECTOR_SHIFT)
-#define INTC_PRIO_INTLEVEL_SHIFT   (30)      /* Bits 30-31: Interrupt Level */
+#define INTC_IPR_INTLEVEL_SHIFT   (30)      /* Bits 30-31: Interrupt Level */
-#define INTC_PRIO_INTLEVEL_MASK    (3 << INTC_PRIO_INTLEVEL_SHIFT)
+#define INTC_IPR_INTLEVEL_MASK    (3 << INTC_IPR_INTLEVEL_SHIFT)
-#  define INTC_PRIO_INTLEVEL_INT0  (0 << INTC_PRIO_INTLEVEL_SHIFT) /* Lowest priority */
+#  define INTC_IPR_INTLEVEL_INT0  (0 << INTC_IPR_INTLEVEL_SHIFT) /* Lowest priority */
-#  define INTC_PRIO_INTLEVEL_INT1  (1 << INTC_PRIO_INTLEVEL_SHIFT)
+#  define INTC_IPR_INTLEVEL_INT1  (1 << INTC_IPR_INTLEVEL_SHIFT)
-#  define INTC_PRIO_INTLEVEL_INT2  (2 << INTC_PRIO_INTLEVEL_SHIFT)
+#  define INTC_IPR_INTLEVEL_INT2  (2 << INTC_IPR_INTLEVEL_SHIFT)
-#  define INTC_PRIO_INTLEVEL_INT3  (3 << INTC_PRIO_INTLEVEL_SHIFT) /* Highest priority */
+#  define INTC_IPR_INTLEVEL_INT3  (3 << INTC_IPR_INTLEVEL_SHIFT) /* Highest priority */
 
 /* Interrupt request register bit-field definitions */
 
-#define INTC_PRIO(n)               (AVR32_INTC_PRIO((n) >> 5))
+#define INTC_IRR_REG(n)           (AVR32_INTC_IPR((n) >> 5))
-#define INTC_PRIO_IRR(n)           (1 << ((n) & 0x1f))
+#define INTC_IRR_SHIFT(n)         (1 << ((n) & 0x1f))
+#define INTC_IRR_MASK(n)          (1 << NTC_IRR_SHIFT(n))
 
 /* Interrupt cause register bit-field definitions */
 
-#define INTC_CAUSE_SHIFT           (0)       /* Bits 0-5: Interrupt Group Causing Interrupt of Priority n */
+#define INTC_ICR_CAUSE_SHIFT      (0)       /* Bits 0-5: Interrupt Group Causing Interrupt of Priority n */
-#define INTC_CAUSE_MASK            (0x3f << INTC_CAUSE_SHIFT)
+#define INTC_ICR_CAUSE_MASK       (0x3f << INTC_ICR_CAUSE_SHIFT)
 
 /************************************************************************************
  * Public Types

arch/avr/src/at91uc3/at91uc3_irq.c

@@ -53,24 +53,119 @@
 #include "up_internal.h"
 #include "at91uc3_internal.h"
 
+#include "chip.h"
+#include "at91uc3_intc.h"
+
 /****************************************************************************
  * Definitions
  ****************************************************************************/
 
+/* These symbols are exported from up_exceptions.S:
+ */
+
+extern uint32_t vectortab;
+extern uint32_t avr32_int0;
+extern uint32_t avr32_int1;
+extern uint32_t avr32_int2;
+extern uint32_t avr32_int3;
+
+/* The provide interrupt handling offsets relative to the EVBA
+ * address (which should be vectortab).
+ */
+
+#define AVR32_INT0_RADDR ((uint32_t)&avr32_int0 - (uint32_t)&vectortab)
+#define AVR32_INT1_RADDR ((uint32_t)&avr32_int1 - (uint32_t)&vectortab)
+#define AVR32_INT2_RADDR ((uint32_t)&avr32_int2 - (uint32_t)&vectortab)
+#define AVR32_INT3_RADDR ((uint32_t)&avr32_int3 - (uint32_t)&vectortab)
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
 
 uint32_t *current_regs;
 
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct irq_groups_s
+{
+  uint8_t baseirq;  /* IRQ number associated with bit 0 */
+  uint8_t nirqs;    /* Number of IRQs in this group */
+};
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
 
+/* This table maps groups into (1) the base IRQ number for the group and (2)
+ * the number of valid interrupts in the group.
+ */
+
+static const struct irq_groups_s g_grpirqs[AVR32_IRQ_NGROUPS] =
+{
+  {AVR32_IRQ_BASEIRQGRP0,  AVR32_IRQ_NREQGRP0 }, /* Group  0 */
+  {AVR32_IRQ_BASEIRQGRP1,  AVR32_IRQ_NREQGRP1 }, /* Group  1 */
+  {AVR32_IRQ_BASEIRQGRP2,  AVR32_IRQ_NREQGRP2 }, /* Group  2 */
+  {AVR32_IRQ_BASEIRQGRP3,  AVR32_IRQ_NREQGRP3 }, /* Group  3 */
+  {AVR32_IRQ_BASEIRQGRP4,  AVR32_IRQ_NREQGRP4 }, /* Group  4 */
+  {AVR32_IRQ_BASEIRQGRP5,  AVR32_IRQ_NREQGRP5 }, /* Group  5 */
+  {AVR32_IRQ_BASEIRQGRP6,  AVR32_IRQ_NREQGRP6 }, /* Group  6 */
+  {AVR32_IRQ_BASEIRQGRP7,  AVR32_IRQ_NREQGRP7 }, /* Group  7 */
+  {AVR32_IRQ_BASEIRQGRP8,  AVR32_IRQ_NREQGRP8 }, /* Group  8 */
+  {AVR32_IRQ_BASEIRQGRP9,  AVR32_IRQ_NREQGRP9 }, /* Group  9 */
+  {AVR32_IRQ_BASEIRQGRP10, AVR32_IRQ_NREQGRP10}, /* Group 10 */
+  {AVR32_IRQ_BASEIRQGRP11, AVR32_IRQ_NREQGRP11}, /* Group 11 */
+  {AVR32_IRQ_BASEIRQGRP12, AVR32_IRQ_NREQGRP12}, /* Group 12 */
+  {AVR32_IRQ_BASEIRQGRP13, AVR32_IRQ_NREQGRP13}, /* Group 13 */
+  {AVR32_IRQ_BASEIRQGRP14, AVR32_IRQ_NREQGRP14}, /* Group 14 */
+  {AVR32_IRQ_BASEIRQGRP15, AVR32_IRQ_NREQGRP15}, /* Group 15 */
+  {AVR32_IRQ_BASEIRQGRP16, AVR32_IRQ_NREQGRP16}, /* Group 16 */
+  {AVR32_IRQ_BASEIRQGRP17, AVR32_IRQ_NREQGRP17}, /* Group 17 */
+  {AVR32_IRQ_BASEIRQGRP18, AVR32_IRQ_NREQGRP18}, /* Group 18 */
+};
+
+/* The following table provides the value of the IPR register to
+ * use to assign a group to different interrupt priorities.
+ */
+
+#if 0 /* REVISIT -- Can we come up with a way to statically initialize? */
+static const uint32_t g_ipr[AVR32_IRQ_INTPRIOS] =
+{
+  ((AVR32_INT0_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT0),
+  ((AVR32_INT1_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT1),
+  ((AVR32_INT2_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT2),
+  ((AVR32_INT3_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT3),
+};
+#else
+static uint32_t g_ipr[AVR32_IRQ_INTPRIOS];
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: up_getgrp
+ ****************************************************************************/
+
+static int up_getgrp(unsigned int irq)
+{
+  int i;
+
+  if (irq >= AVR32_IRQ_BASEIRQGRP0)
+    {
+      for (i = 0; i < AVR32_IRQ_NGROUPS; i++)
+        {
+          if (irq < g_grpirqs[i].baseirq + g_grpirqs[i].nirqs)
+            {
+              return i;
+            }
+        }
+    }
+  return -EINVAL;
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -81,18 +176,30 @@ uint32_t *current_regs;
 
 void up_irqinitialize(void)
 {
+  int group;
+
   /* Disable all interrupts */
 #warning "Missing logic"
 
-  /* The standard location for the vector table is at the beginning of FLASH
+  /* Initialize the table that provides the value of the IPR register to
-   * at address 0x0800:0000.  If we are using the STMicro DFU bootloader, then
+   * use to assign a group to different interrupt priorities.
-   * the vector table will be offset to a different location in FLASH and we
-   * will need to set the EVBA vector location to this alternative location.
    */
-#warning "Missing logic"
 
-  /* Set all interrupts (and exceptions) to the default priority */
+#if 1 /* REVISIT -- Can we come up with a way to statically initialize? */
-#warning "Missing logic"
+  g_ipr[0] = ((AVR32_INT0_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT0);
+  g_ipr[1] = ((AVR32_INT1_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT1);
+  g_ipr[2] = ((AVR32_INT2_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT2);
+  g_ipr[3] = ((AVR32_INT3_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT3);
+#endif
+
+  /* Set the interrupt group priority to a default value.  All are linked to
+   * interrupt priority level 0 and to interrupt vector INT0.
+   */
+
+  for (group = 0; group < AVR32_IRQ_MAXGROUPS; group++)
+  {
+    putreg32(g_ipr[0], AVR32_INTC_IPR(group));
+  }
 
   /* currents_regs is non-NULL only while processing an interrupt */
 
@@ -164,7 +271,72 @@ void up_maskack_irq(int irq)
 #ifdef CONFIG_ARCH_IRQPRIO
 int up_prioritize_irq(int irq, int priority)
 {
-#warning "Missing logic"
+  if (priority >= 0 && priority < AVR32_IRQ_INTPRIOS)
-  return -ENOSYS;
+    {
+      int group = up_getgrp(irq);
+      if (group >= 0)
+        {
+          putreg32(g_ipr[priority], AVR32_INTC_IPR(group));
+          return OK;
+        }
+    }
+  return -EINVAL;
 }
 #endif
+
+/****************************************************************************
+ * Name: avr32_intirqno
+ *
+ * Description:
+ *   Return the highest priority pending INT0 interrupt.
+ *
+ ****************************************************************************/
+#warning "Is this safe to call from assembly?"
+unsigned int avr32_int0irqno(unsigned int level)
+{
+  /* Get the group that caused the interrupt: "ICRn identifies the group with
+   * the highest priority that has a pending interrupt of level n. This value
+   * is only defined when at least one interrupt of level n is pending.
+   */
+
+  uint32_t group = getreg32(AVR32_INTC_ICR(level)) & INTC_ICR_CAUSE_MASK;
+  if (group < AVR32_IRQ_NGROUPS)
+    {
+      /* Now get the set of pending interrupt requests for this group.
+       * Note that we may get spurious interrupts due to races conditions
+       */
+
+      uint32_t irr = getreg32(AVR32_INTC_IRR(group));
+      unsigned irq  = g_grpirqs[group].baseirq;
+      uint32_t mask = 1;
+      int i;
+
+      /* Check each interrupt source for this group */
+
+      for (i = 0; i < g_grpirqs[group].nirqs; i++)
+        {
+          /* Is there an interrupt pending? */
+
+          if ((irr & mask) != 0)
+            {
+              /* Yes.. return its IRQ number */
+
+              return irq;
+            }
+
+          /* No.. this is interrupt is not pending */
+
+          irq++;
+          mask <<= 1;
+        }
+
+       lldbg("Spurious interrupt: group=%d IRR=%08x\n", group, IRR);
+       return -ENODEV;
+    }
+
+  lldbg("Bad group: %d\n", group);
+  return AVR32_IRQ_BADVECTOR;
+}
+
+
+

arch/avr/src/avr32/up_exceptions.S

@@ -47,7 +47,11 @@
  * External Symbols
  ****************************************************************************/
 
-	.global		avr32_getirqno
+	.global		avr32_int0irqno	/* Returns the IRQ number of an INT0 interrupt */
+	.global		avr32_int1irqno	/* Returns the IRQ number of an INT1 interrupt */
+	.global		avr32_int2irqno	/* Returns the IRQ number of an INT2 interrupt */
+	.global		avr32_int3irqno	/* Returns the IRQ number of an INT3 interrupt */
+	.global		up_doirq		/* Dispatch an IRQ */
 
 /****************************************************************************
  * Macros
@@ -122,31 +126,44 @@ vectortab:
  * the exception table.
  * On entry to each interrupt handler, R8-R12, LR, PC and SR have already been
  * pushed onto the system stack by the MCU.
+ *
+ * An interrupt may disappear while it is being fetched by the CPU and, hence,
+ * spurious interrupt may result.
  */
 
 	.balign 4
+	.global	avr32_int0
 avr32_int0:
-	mov		r12, 0				/* r12=interrupt level parameter */
+	mov		r12, 0				/* r12=interrupt level 0 */
-	rjmp	avr32_intcommon		/* Jump to common interrupt logic */
+	rjmp	avr32_intcommon		/* Jump to common interrupt handling logic */
 
 	.balign	4
+	.global	avr32_int1
 avr32_int1:
-	mov		r12, 1				/* r12=interrupt level parameter */
+	mov		r12, 1				/* r12=interrupt level 1 */
-	rjmp	avr32_intcommon		/* Jump to common interrupt logic */
+	rjmp	avr32_intcommon		/* Jump to common interrupt handling logic */
 
 	.balign	4
+	.global	avr32_int2
 avr32_int2:
-	mov		r12, 2				/* r12=interrupt level parameter */
+	mov		r12, 2				/* r12=interrupt level 2 */
-	rjmp	avr32_intcommon		/* Jump to common interrupt logic */
+	rjmp	avr32_intcommon		/* Jump to common interrupt handling logic */
 
+	.balign	4
+	.global	avr32_int3
 avr32_int3:
-	mov		r12, 2				/* r12=interrupt level parameter */
+	mov		r12, 3				/* r12=interrupt level 3 */
 
-/* Common interrupt handling logic */
+/* Common interrupt handling logic.  R12 holds the interrupt level index */
 
 avr32_intcommon:
-	call	avr32_getirqno		/* Get the IRQ number of the interrupt to process */
+	mcall	.Lavr32_intirqno	/* Get the IRQ number of the int0 event */
-	rjmp	avr32_common		/* Then go to the common exception handling logic */
+	cp.w	r12, 0				/* Negated errno returned if spurious interrupt */
+	brge	avr32_common		/* Jump to the common exception handling logic */
+	rete						/* Ignore spurious interrupt */
+
+.Lavr32_intirqno:
+	.word	avr32_intirqno
 
 /****************************************************************************
  * Exception Vector Handlers

arch/avr/src/common/up_internal.h

@@ -142,7 +142,6 @@ extern uint32_t _ebss;            /* End+1 of .bss */
 
 extern void up_boot(void);
 extern void up_copystate(uint32_t *dest, uint32_t *src);
-extern void up_decodeirq(uint32_t *regs);
 extern void up_irqinitialize(void);
 #ifdef CONFIG_ARCH_DMA
 extern void weak_function up_dmainitialize(void);
@@ -156,14 +155,6 @@ extern void up_lowputc(char ch);
 extern void up_puts(const char *str);
 extern void up_lowputs(const char *str);
 extern uint32_t *up_doirq(int irq, uint32_t *regs);
-extern int  up_svcall(int irq, FAR void *context);
-extern int  up_hardfault(int irq, FAR void *context);
-#ifdef CONFIG_PAGING
-extern void up_pginitialize(void);
-extern uint32_t *up_va2pte(uintptr_t vaddr);
-#else /* CONFIG_PAGING */
-# define up_pginitialize()
-#endif /* CONFIG_PAGING */
 
 /* Defined in common/up_allocateheap.c or chip/xxx_allocateheap.c */