arch/stm32h5: add basic ADC support

Adds ADC support with minimal feature set (no DMA or Timers etc). A new nucleo-h563zi configuration was added to
provide easy testing with the adc example NSH addon.

Fix Kconfig spacing to tabs

arch/arm/src/stm32h5/Kconfig

@@ -30,7 +30,7 @@ endchoice # STM32 H5 Chip Selection
 config STM32H5_STM32H5XXXX
 	bool
 	default n
-        select ARCH_HAVE_FPU
+		select ARCH_HAVE_FPU
 
 config STM32H5_STM32H56XXX
 	bool
@@ -64,12 +64,12 @@ choice
 		that designates the FLASH size.
 
 			Designator  Size in KiB
-			     8          64
+				 8          64
-			     B         128
+				 B         128
-			     C         256
+				 C         256
-			     E         512
+				 E         512
-			     G        1024
+				 G        1024
-			     I        2048
+				 I        2048
 
 		This configuration option defaults to using the configuration based on that designator
 		or the default smaller size if there is no last character designator is present in the
@@ -198,6 +198,7 @@ menu "STM32H5 Peripheral Selection"
 # These "hidden" settings determine if a peripheral option is available
 # for the selected MCU
 
+
 config STM32H5_HAVE_ETHERNET
 	bool
 	default n
@@ -265,8 +266,22 @@ config STM32H5_USART
 	bool
 	default n
 
+config STM32H5_ADC
+  bool
+  default n
+
 # These are the peripheral selections proper
 
+config STM32H5_ADC1
+  bool "ADC1"
+  default n
+  select STM32H5_ADC
+
+config STM32H5_ADC2
+  bool "ADC2"
+  default n
+  select STM32H5_ADC
+
 config STM32H5_ETHMAC
 	bool "Ethernet MAC"
 	default n
@@ -367,8 +382,8 @@ config STM32H5_LPUART1
 	select STM32H5_USART
 
 config STM32H5_I2C
-        bool
+		bool
-        default n
+		default n
 
 config STM32H5_I2C1
 	bool "I2C1"
@@ -1092,119 +1107,119 @@ menu "I2C Configuration"
 menu "Clock Selection"
 
 choice
-        depends on STM32H5_I2C1
+	depends on STM32H5_I2C1
-        prompt "I2C1 Input Clock Selection"
+	prompt "I2C1 Input Clock Selection"
-        default STM32H5_I2C1_CLK_PCLK1
+	default STM32H5_I2C1_CLK_PCLK1
 config STM32H5_I2C1_CLK_CSI
-        bool "CSI"
+	bool "CSI"
 config STM32H5_I2C1_CLK_HSI
-        bool "HSI"
+	bool "HSI"
 config STM32H5_I2C1_CLK_PCLK1
-        bool "PCLK1"
+	bool "PCLK1"
 config STM32H5_I2C1_CLK_PLL3R
-        bool "PLL3R"
+	bool "PLL3R"
 endchoice
 choice
-        depends on STM32H5_I2C2
+	depends on STM32H5_I2C2
-        prompt "I2C2 Input Clock Selection"
+	prompt "I2C2 Input Clock Selection"
-        default STM32H5_I2C2_CLK_PCLK1
+	default STM32H5_I2C2_CLK_PCLK1
 config STM32H5_I2C2_CLK_CSI
-        bool "CSI"
+	bool "CSI"
 config STM32H5_I2C2_CLK_HSI
-        bool "HSI"
+	bool "HSI"
 config STM32H5_I2C2_CLK_PCLK1
-        bool "PCLK1"
+	bool "PCLK1"
 config STM32H5_I2C2_CLK_PLL3R
-        bool "PLL3R"
+	bool "PLL3R"
 endchoice
 choice
-        depends on STM32H5_I2C3
+	depends on STM32H5_I2C3
-        prompt "I2C3 Input Clock Selection"
+	prompt "I2C3 Input Clock Selection"
-        default STM32H5_I2C3_CLK_PCLK3
+	default STM32H5_I2C3_CLK_PCLK3
 config STM32H5_I2C3_CLK_CSI
-        bool "CSI"
+	bool "CSI"
 config STM32H5_I2C3_CLK_HSI
-        bool "HSI"
+	bool "HSI"
 config STM32H5_I2C3_CLK_PCLK3
-        bool "PCLK3"
+	bool "PCLK3"
 config STM32H5_I2C3_CLK_PLL3R
-        bool "PLL3R"
+	bool "PLL3R"
 endchoice
 choice
-        depends on STM32H5_I2C4
+	depends on STM32H5_I2C4
-        prompt "I2C4 Input Clock Selection"
+	prompt "I2C4 Input Clock Selection"
-        default STM32H5_I2C4_CLK_PCLK3
+	default STM32H5_I2C4_CLK_PCLK3
 config STM32H5_I2C4_CLK_CSI
-        bool "CSI"
+	bool "CSI"
 config STM32H5_I2C4_CLK_HSI
-        bool "HSI"
+	bool "HSI"
 config STM32H5_I2C4_CLK_PCLK3
-        bool "PCLK3"
+	bool "PCLK3"
 config STM32H5_I2C4_CLK_PLL3R
-        bool "PLL3R"
+	bool "PLL3R"
 endchoice
 
 endmenu
 
 menu "Rise/Fall Override"
 config STM32H5_I2C1_RF_OVERRIDE
-        bool "I2C1"
+	bool "I2C1"
-        default n
+	default n
-        depends on STM32H5_I2C1
+	depends on STM32H5_I2C1
 config STM32H5_I2C2_RF_OVERRIDE
-        bool "I2C2"
+	bool "I2C2"
-        default n
+	default n
-        depends on STM32H5_I2C2
+	depends on STM32H5_I2C2
 config STM32H5_I2C3_RF_OVERRIDE
-        bool "I2C3"
+	bool "I2C3"
-        default n
+	default n
-        depends on STM32H5_I2C3
+	depends on STM32H5_I2C3
 config STM32H5_I2C4_RF_OVERRIDE
-        bool "I2C4"
+	bool "I2C4"
-        default n
+	default n
-        depends on STM32H5_I2C4
+	depends on STM32H5_I2C4
 
 menu "Rise/Fall Values"
 config STM32H5_I2C1_RISE
-        int "I2C1 Rise Time (ns)"
+	int "I2C1 Rise Time (ns)"
-        range 0 1000
+	range 0 1000
-        default 20
+	default 20
-        depends on STM32H5_I2C1_RF_OVERRIDE
+	depends on STM32H5_I2C1_RF_OVERRIDE
 config STM32H5_I2C1_FALL
-        int "I2C1 Fall Time (ns)"
+	int "I2C1 Fall Time (ns)"
-        range 0 300
+	range 0 300
-        default 20
+	default 20
-        depends on STM32H5_I2C1_RF_OVERRIDE
+	depends on STM32H5_I2C1_RF_OVERRIDE
 config STM32H5_I2C2_RISE
-        int "I2C2 Rise Time (ns)"
+	int "I2C2 Rise Time (ns)"
-        range 0 1000
+	range 0 1000
-        default 20
+	default 20
-        depends on STM32H5_I2C2_RF_OVERRIDE
+	depends on STM32H5_I2C2_RF_OVERRIDE
 config STM32H5_I2C2_FALL
-        int "I2C2 Fall Time (ns)"
+	int "I2C2 Fall Time (ns)"
-        range 0 300
+	range 0 300
-        default 20
+	default 20
-        depends on STM32H5_I2C2_RF_OVERRIDE
+	depends on STM32H5_I2C2_RF_OVERRIDE
 config STM32H5_I2C3_RISE
-        int "I2C3 Rise Time (ns)"
+	int "I2C3 Rise Time (ns)"
-        range 0 1000
+	range 0 1000
-        default 20
+	default 20
-        depends on STM32H5_I2C3_RF_OVERRIDE
+	depends on STM32H5_I2C3_RF_OVERRIDE
 config STM32H5_I2C3_FALL
-        int "I2C3 Fall Time (ns)"
+	int "I2C3 Fall Time (ns)"
-        range 0 300
+	range 0 300
-        default 20
+	default 20
-        depends on STM32H5_I2C3_RF_OVERRIDE
+	depends on STM32H5_I2C3_RF_OVERRIDE
 config STM32H5_I2C4_RISE
-        int "I2C4 Rise Time (ns)"
+	int "I2C4 Rise Time (ns)"
-        range 0 1000
+	range 0 1000
-        default 20
+	default 20
-        depends on STM32H5_I2C4_RF_OVERRIDE
+	depends on STM32H5_I2C4_RF_OVERRIDE
 config STM32H5_I2C4_FALL
-        int "I2C4 Fall Time (ns)"
+	int "I2C4 Fall Time (ns)"
-        range 0 300
+	range 0 300
-        default 20
+	default 20
-        depends on STM32H5_I2C4_RF_OVERRIDE
+	depends on STM32H5_I2C4_RF_OVERRIDE
 endmenu
 endmenu
 
@@ -1212,51 +1227,51 @@ menu "Filtering"
 
 menu "Digital Filters"
 config STM32H5_I2C1_DNF
-        int "I2C1 Digital Noise Filter"
+	int "I2C1 Digital Noise Filter"
-        range 0 15
+	range 0 15
-        default 0
+	default 0
-        depends on STM32H5_I2C1
+	depends on STM32H5_I2C1
 config STM32H5_I2C2_DNF
-        int "I2C2 Digital Noise Filter"
+	int "I2C2 Digital Noise Filter"
-        range 0 15
+	range 0 15
-        default 0
+	default 0
-        depends on STM32H5_I2C2
+	depends on STM32H5_I2C2
 config STM32H5_I2C3_DNF
-        int "I2C3 Digital Noise Filter"
+	int "I2C3 Digital Noise Filter"
-        range 0 15
+	range 0 15
-        default 0
+	default 0
-        depends on STM32H5_I2C3
+	depends on STM32H5_I2C3
 config STM32H5_I2C4_DNF
-        int "I2C4 Digital Noise Filter"
+	int "I2C4 Digital Noise Filter"
-        range 0 15
+	range 0 15
-        default 0
+	default 0
-        depends on STM32H5_I2C4
+	depends on STM32H5_I2C4
 endmenu
 
 menu "Analog Filters"
 config STM32H5_I2C1_ANFOFF
-        int "Turn off I2C1 Analog Filter (0=on, 1=off)"
+	int "Turn off I2C1 Analog Filter (0=on, 1=off)"
-        default 1
+	default 1
-        range 0 1
+	range 0 1
-        depends on STM32H5_I2C1
+	depends on STM32H5_I2C1
 
 config STM32H5_I2C2_ANFOFF
-        int "Turn off I2C2 Analog Filter (0=on, 1=off)"
+	int "Turn off I2C2 Analog Filter (0=on, 1=off)"
-        default 1
+	default 1
-        range 0 1
+	range 0 1
-        depends on STM32H5_I2C2
+	depends on STM32H5_I2C2
 
 config STM32H5_I2C3_ANFOFF
-        int "Turn off I2C3 Analog Filter (0=on, 1=off)"
+	int "Turn off I2C3 Analog Filter (0=on, 1=off)"
-        default 1
+	default 1
-        range 0 1
+	range 0 1
-        depends on STM32H5_I2C3
+	depends on STM32H5_I2C3
 
 config STM32H5_I2C4_ANFOFF
-        int "Turn off I2C4 Analog Filter (0=on, 1=off)"
+	int "Turn off I2C4 Analog Filter (0=on, 1=off)"
-        default 1
+	default 1
-        range 0 1
+	range 0 1
-        depends on STM32H5_I2C4
+	depends on STM32H5_I2C4
 endmenu
 
 endmenu

arch/arm/src/stm32h5/Make.defs

@@ -48,6 +48,10 @@ ifeq ($(CONFIG_STM32H5_I2C),y)
 CHIP_CSRCS += stm32_i2c.c
 endif
 
+ifeq ($(CONFIG_ADC),y)
+CHIP_CSRCS += stm32_adc.c
+endif
+
 # Required chip type specific files
 
 ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)

arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h

@@ -196,5 +196,47 @@
 #define GPIO_LPUART1_CTS_1     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN11)
 #define GPIO_LPUART1_RTS_DE_1  (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN12)
 
+/* ADC1 */
+
+#define GPIO_ADC1_IN0_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_ADC1_IN1_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_ADC1_IN2_0   (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN11)
+#define GPIO_ADC1_IN3_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_ADC1_IN4_0   (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
+#define GPIO_ADC1_IN5_0   (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_ADC1_IN6_0   (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN12)
+#define GPIO_ADC1_IN7_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_ADC1_IN8_0   (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
+#define GPIO_ADC1_IN9_0   (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_ADC1_IN10_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
+#define GPIO_ADC1_IN11_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
+#define GPIO_ADC1_IN12_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
+#define GPIO_ADC1_IN13_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_ADC1_IN14_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_ADC1_IN15_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_ADC1_IN18_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_ADC1_IN19_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+
+/* ADC2 */
+
+#define GPIO_ADC2_IN0_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_ADC2_IN1_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_ADC2_IN2_0   (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN13)
+#define GPIO_ADC2_IN3_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_ADC2_IN4_0   (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
+#define GPIO_ADC2_IN5_0   (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_ADC2_IN6_0   (GPIO_ANALOG | GPIO_PORTF | GPIO_PIN14)
+#define GPIO_ADC2_IN7_0   (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_ADC2_IN8_0   (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
+#define GPIO_ADC2_IN9_0   (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_ADC2_IN10_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
+#define GPIO_ADC2_IN11_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
+#define GPIO_ADC2_IN12_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
+#define GPIO_ADC2_IN13_0  (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_ADC2_IN14_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_ADC2_IN15_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_ADC2_IN18_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_ADC2_IN19_0  (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+
 #endif /* CONFIG_STM32H5_STM32H563XX*/
 #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */

arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h

@@ -1130,7 +1130,7 @@
 #  define RCC_CCIPR5_ADCDACSEL_PLL2RCK    (2 << RCC_CCIPR5_ADCDACSEL_SHIFT)
 #  define RCC_CCIPR5_ADCDACSEL_HSECK      (3 << RCC_CCIPR5_ADCDACSEL_SHIFT)
 #  define RCC_CCIPR5_ADCDACSEL_HSEKERCK   (4 << RCC_CCIPR5_ADCDACSEL_SHIFT)
-#  define RCC_CCIPR5_ADCDACSEL_CSIKERCK   (4 << RCC_CCIPR5_ADCDACSEL_SHIFT)
+#  define RCC_CCIPR5_ADCDACSEL_CSIKERCK   (5 << RCC_CCIPR5_ADCDACSEL_SHIFT)
 
 #define RCC_CCIPR5_DACSEL                 (1 << 3)
 

arch/arm/src/stm32h5/stm32.h

@@ -43,4 +43,6 @@
 #include "stm32_uart.h"
 #include "stm32_lowputc.h"
 #include "stm32_i2c.h"
+#include "stm32_adc.h"
+
 #endif /* __ARCH_ARM_SRC_STM32H5_STM32_H */

arch/arm/src/stm32h5/stm32_adc.h

@@ -0,0 +1,85 @@
+/****************************************************************************
+ * arch/arm/src/stm32h5/stm32_adc.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H5_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32H5_STM32_ADC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/analog/adc.h>
+#include "chip.h"
+#include "hardware/stm32_adc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32h5_adc_initialize
+ *
+ * Description:
+ *    Initialize the ADC.
+ *
+ * Input Parameters:
+ *    intf      - Could be {1,2} for ADC1, ADC2
+ *    chanlist  - The list of channels
+ *    nchannels - Number of channels
+ *
+ * Returned Value:
+ *    Valid ADC device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct adc_dev_s;
+struct adc_dev_s *stm32h5_adc_initialize(int intf,
+                                         const uint8_t *chanlist,
+                                         int nchannels);
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2*/
+#endif /* __ARCH_ARM_SRC_STM32H5_STM32_ADC_H */

arch/arm/src/stm32h5/stm32h5xx_rcc.c

@@ -1195,6 +1195,15 @@ void stm32_stdclockconfig(void)
         }
 
 #endif /* STM32_USE_LSE */
+
+      /* Configure ADC source clock */
+
+#if defined(STM32_RCC_CCIPR5_ADCDACSEL)
+      regval = getreg32(STM32_RCC_CCIPR5);
+      regval &= ~RCC_CCIPR5_ADCDACSEL_MASK;
+      regval |= STM32_RCC_CCIPR5_ADCDACSEL;
+      putreg32(regval, STM32_RCC_CCIPR5);
+#endif
     }
 }
 #endif

boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig

@@ -0,0 +1,56 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ADC=y
+CONFIG_ANALOG=y
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h563zi"
+CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32h5"
+CONFIG_ARCH_CHIP_STM32H563ZI=y
+CONFIG_ARCH_CHIP_STM32H5=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV8M_STACKCHECK=y
+CONFIG_BOARD_LOOPSPERMSEC=9251
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_EXAMPLES_ADC=y
+CONFIG_EXAMPLES_ADC_NSAMPLES=10
+CONFIG_EXAMPLES_ADC_SWTRIG=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=655360
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_STM32H5_ADC1=y
+CONFIG_STM32H5_USART3=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y

boards/arm/stm32h5/nucleo-h563zi/include/board.h

@@ -87,6 +87,20 @@
 #define STM32_PLL1Q_FREQUENCY     (STM32_VCO1_FRQ / 2)
 #define STM32_PLL1R_FREQUENCY     (STM32_VCO1_FRQ / 2)
 
+/* PLL2 config: Needed to use 2 ADC at max speed. */
+
+#define STM32_PLLCFG_PLL2CFG      (RCC_PLL2CFGR_PLL2SRC_HSI | \
+                                   RCC_PLL2CFGR_PLL2RGE_4_8M | \
+                                   RCC_PLL2CFGR_PLL2M(8) | \
+                                   RCC_PLL2CFGR_PLL2REN)
+#define STM32_PLLCFG_PLL2N         RCC_PLL2DIVR_PLL2N(75)
+#define STM32_PLLCFG_PLL2R         RCC_PLL2DIVR_PLL2R(4)
+#define STM32_PLLCFG_PLL2DIVR     (STM32_PLLCFG_PLL2N | \
+                                   STM32_PLLCFG_PLL2R)
+
+#define STM32_VCO2_FRQ            ((STM32_HSI_FREQUENCY / 8) * 75)
+#define STM32_PLL2R_FREQUENCY     (STM32_VCO2_FRQ / 4)
+
 /* Enable CLK48; get it from HSI48 */
 
 #if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
@@ -180,6 +194,14 @@
 #define GPIO_ETH_RMII_CRS_DV  (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz)  /* PA7 */
 #define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */
 
+/* ADC Clock Source *********************************************************/
+
+#define STM32_RCC_CCIPR5_ADCDACSEL RCC_CCIPR5_ADCDACSEL_PLL2RCK
+#define STM32_ADC_CLK_FREQUENCY    STM32_PLL2R_FREQUENCY
+
+#define GPIO_ADC1_IN3   (GPIO_ADC1_IN3_0)
+#define GPIO_ADC1_IN10  (GPIO_ADC1_IN10_0)
+
 /* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder
  * bridges SB123 to SB130 are re-worked accordingly).
  */

boards/arm/stm32h5/nucleo-h563zi/src/Makefile

@@ -39,4 +39,8 @@ ifeq ($(CONFIG_BOARDCTL),y)
 CSRCS += stm32_appinit.c
 endif
 
+ifeq ($(CONFIG_ADC),y)
+CSRCS += stm32_adc.c
+endif
+
 include $(TOPDIR)/boards/Board.mk

boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h

@@ -118,5 +118,16 @@
 
 int stm32_bringup(void);
 
+/****************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ ****************************************************************************/
+
+#ifdef CONFIG_ADC
+int stm32_adc_setup(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */

boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c

@@ -0,0 +1,133 @@
+/****************************************************************************
+ * boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include <nuttx/analog/adc.h>
+
+#include "stm32.h"
+
+#if defined(CONFIG_ADC) && defined(CONFIG_STM32H5_ADC1)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* The number of ADC channels in the conversion list */
+
+#define ADC1_NCHANNELS 2
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
+
+static const uint8_t g_chanlist1[2] =
+{
+  3,
+  10
+};
+
+/* Configurations of pins used by each ADC channel */
+
+static const uint32_t g_pinlist1[2]  =
+{
+  GPIO_ADC1_IN3,
+  GPIO_ADC1_IN10,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+int stm32_adc_setup(void)
+{
+  static bool initialized = false;
+  struct adc_dev_s *adc;
+  int ret;
+  int i;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC1_NCHANNELS; i++)
+        {
+          stm32_configgpio(g_pinlist1[i]);
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32h5_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS);
+      if (adc == NULL)
+        {
+          aerr("ERROR: Failed to get ADC interface 1\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0" */
+
+      ret = adc_register("/dev/adc0", adc);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
+          return ret;
+        }
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif

boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c

@@ -102,6 +102,14 @@ int stm32_bringup(void)
 #endif
 #endif /* CONFIG_INPUT_BUTTONS */
 
+#ifdef CONFIG_ADC
+  ret = stm32_adc_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
+    }
+#endif /* CONFIG_ADC*/
+
   UNUSED(ret);
   return OK;
 }