diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index 6ecaf9b88fd..2da386c3daa 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -2,7 +2,8 @@ * arch/arm/include/kinetis/chip.h * * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,6 +42,7 @@ ************************************************************************************/ #include +#include /************************************************************************************ * Pre-processor Definitions @@ -73,6 +75,7 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ #if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) # define KINETIS_FLASH_SIZE (64*1024) /* 32Kb */ @@ -155,6 +158,7 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ #if defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) # define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ @@ -210,6 +214,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ @@ -261,6 +267,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ @@ -304,6 +312,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ @@ -346,6 +356,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ # define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ @@ -388,6 +400,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ # define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ @@ -432,6 +446,8 @@ # define KINETIS_K40 1 /* Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ # define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ @@ -474,6 +490,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -519,6 +537,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ @@ -564,6 +584,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -610,6 +632,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -655,6 +679,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -700,6 +726,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -745,6 +773,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -790,6 +820,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -835,6 +867,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -880,6 +914,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -925,6 +961,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -970,6 +1008,8 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -1016,6 +1056,8 @@ # define KINETIS_K60 1 /* Kinetis K60 family */ # define KINETIS_NEW_MCG 1 /* Kinetis New MCG - different VDIV */ # undef KINETIS_K64 /* Not Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -1056,8 +1098,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1090,8 +1134,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1124,8 +1170,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1158,8 +1206,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1192,8 +1242,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1226,8 +1278,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1260,8 +1314,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1294,8 +1350,10 @@ # undef KINETIS_K40 /* Not Kinetis K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ # define KINETIS_K64 1 /* Kinetis K64 family */ +# undef KINETIS_K66 /* Not Kinetis K66 family */ + # define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ -# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ # define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ # define KINETIS_MPU 1 /* Memory protection unit */ @@ -1323,6 +1381,66 @@ # define KINETIS_NMMCAU 1 /* Hardware encryption */ # define KINETIS_NCRC 1 /* CRC */ +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ + +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || \ + defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) +# undef KINETIS_K20 /* Not Kinetis K20 family */ +# undef KINETIS_K40 /* Not Kinetis K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ +# define KINETIS_K66 1 /* Kinetis K66 family */ + +# if defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# endif +# if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) +# define KINETIS_FLASH_SIZE (2048*1024) /* 2Mb */ +# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# endif +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 32 /* Up to 32 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 4 /* Four I2C modules */ +# define KINETIS_NUART 5 /* Five UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 2 /* Two CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# undef KINETIS_NSLCD /* No segment LCD interface */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 4 /* Four analog comparators */ +# define KINETIS_NDAC6 4 /* Four 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* ? Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* ? Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ #else # error "Unsupported Kinetis chip" #endif diff --git a/arch/arm/include/kinetis/kinetis_mcg.h b/arch/arm/include/kinetis/kinetis_mcg.h new file mode 100644 index 00000000000..e4816954811 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_mcg.h @@ -0,0 +1,616 @@ +/************************************************************************************ + * arch/arm/include/kinetis/kinetis_mcg.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Note: It is envisioned that in the long term as a chip is added. The author of + * the new chip definitions will either find the exact configuration in an existing + * chip define and add the new chip to it Or add the MCG feature configuration + * #defines to the chip ifdef list below. In either case the author should mark + * it as "Verified to Document Number:" taken from the reference manual. + * + * To maintain backward compatibility to the version of NuttX prior to + * 2/5/2017, the catch all KINETIS_MCG_VERSION_UKN configuration is assigned + * to all the chips that did not have any conditional compilation based on + * NEW_MCG or KINETIS_K64. This is a "No worse" than the original code solution. + * N.B. Each original chip "if"definitions have been left intact so that the complete + * legacy definitions prior to 2/5/2017 may be filled in completely when vetted. + */ + +/* MCG Configuration Parameters + * + * KINETIS_MCG_PLL_REF_MIN - OSCCLK/PLL_R minimum + * KINETIS_MCG_PLL_REF_MAX - OSCCLK/PLL_R maximum + * KINETIS_MCG_PLL_INTERNAL_DIVBY - The PLL clock is divided by n before VCO divider + * KINETIS_MCG_HAS_PLL_EXTRA_DIVBY - Is PLL clock divided by n before MCG PLL/FLL clock selection in the SIM module + * KINETIS_MCG_FFCLK_DIVBY - MCGFFCLK divided by n + * KINETIS_MCG_HAS_IRC_48M - Has 48MHz internal oscillator + * KINETIS_MCG_HAS_LOW_FREQ_IRC - Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] + * KINETIS_MCG_HAS_HIGH_FREQ_IRC - Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] + * KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode + * KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI + * + * MCD Register Configuration + * + * KINETIS_MCG_HAS_C1 - SoC has C1 Register + * KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS] + * KINETIS_MCG_HAS_C1_FRDIV - SoC has C1[FRDIV] + * KINETIS_MCG_C1_FRDIV_MAX - C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 + * KINETIS_MCG_HAS_C2 - SoC has C2 Register + * KINETIS_MCG_HAS_C2_HGO - SoC has C2[HGO] + * KINETIS_MCG_HAS_C2_RANGE - SoC has C2[RANG] + * KINETIS_MCG_HAS_C2_FCFTRIM - SoC has C2[FCFTRIM] + * KINETIS_MCG_HAS_C2_LOCRE0 - SoC has C2[LOCRE0] + * KINETIS_MCG_HAS_C3 - SoC has C3 Register + * KINETIS_MCG_HAS_C4 - SoC has C4 Register + * KINETIS_MCG_HAS_C5 - SoC has C5 Register + * KINETIS_MCG_HAS_C5_PRDIV - SoC has C5[PRDIV] + * KINETIS_MCG_C5_PRDIV_BASE - PRDIV base value corresponding to 0 in C5[PRDIV] + * KINETIS_MCG_C5_PRDIV_MAX - The Maximum value of C5[PRVDIV]) + * KINETIS_MCG_C5_PRDIV_BITS - Has n bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] + * KINETIS_MCG_HAS_C5_PLLREFSEL0 - SoC has C5[PLLREFSEL0] + * KINETIS_MCG_HAS_C6 - SoC has C6 Register + * KINETIS_MCG_HAS_C6_VDIV - SoC has C6[VDIV] + * KINETIS_MCG_C6_VDIV_BASE - VDIV base value corresponding to 0 in C6[VDIV] + * KINETIS_MCG_C6_VDIV_MAX - The Maximum value of C6[VDIV] + * KINETIS_MCG_HAS_C6_CME - SoC has C6[CME] + * KINETIS_MCG_HAS_C6_PLLS - SoC has C6[PLLS] + * KINETIS_MCG_HAS_C6_LOLIE0 - SoC has C6[LOLIE0] + * KINETIS_MCG_HAS_S - SoC has S Register + * KINETIS_MCG_HAS_S_PLLST - SoC has S[PLLST] + * KINETIS_MCG_HAS_S_LOCK0 - SoC has S[LOCK0] + * KINETIS_MCG_HAS_S_LOLS - SoC has S[LOLS] + * KINETIS_MCG_HAS_ATC - SoC has ATC Register + * KINETIS_MCG_HAS_ATCVH - SoC has ATCVH Register + * KINETIS_MCG_HAS_ATCVL - SoC has ATCVL Register + * KINETIS_MCG_HAS_SC - SoC has SC Register + * KINETIS_MCG_HAS_SC_ATMS - SoC has SC[ATMS] + * KINETIS_MCG_HAS_SC_ATMF - SoC has SC[ATMF] + * KINETIS_MCG_HAS_SC_ATME - SoC has SC[ATME] + * KINETIS_MCG_HAS_C7 - SoC has C7 Register + * KINETIS_MCG_HAS_C7_OSCSEL - SoC has C7[OSCSEL] + * KINETIS_MCG_C7_OSCSEL_BITS - C7[OSCSEL] is n bits wide + * KINETIS_MCG_HAS_C8 - SoC has C8 Register + * KINETIS_MCG_HAS_C8_LOCS1 - SoC has C8[LOCS1] + * KINETIS_MCG_HAS_C8_CME1 - SoC has C8[CME1] + * KINETIS_MCG_HAS_C8_LOLRE - SoC has C8[LOLRE] + * KINETIS_MCG_HAS_C8_LOCRE1 - SoC has C8[LOCRE1] + * KINETIS_MCG_HAS_C9 - SoC has C9 Register + * KINETIS_MCG_HAS_C9_EXT_PLL_LOCS - SoC has C9_EXT_PLL[LOCS] + * KINETIS_MCG_HAS_C9_PLL_LOCRE - SoC has C9_PLL[LOCRE] + * KINETIS_MCG_HAS_C9_PLL_CME - SoC has C9_PLL[CME] + * KINETIS_MCG_HAS_C10 - SoC has C10 Register + * KINETIS_MCG_HAS_C10_LOCS1 - SoC has C10[LOCS1] + * KINETIS_MCG_HAS_C11 - SoC has C11 Register + * KINETIS_MCG_HAS_C11_PLL1OSC1 - SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1], + * KINETIS_MCG_HAS_C11_PLLCS - SoC has C11[PLLCS] + * KINETIS_MCG_HAS_C11_PLLREFSEL1 - SoC has C11[PLLREFSEL1] + * KINETIS_MCG_HAS_C12 - SoC has C12 Register + * KINETIS_MCG_HAS_S2 - SoC has S2 Register + * KINETIS_MCG_HAS_S2_PLL1OSC1 - SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] + * KINETIS_MCG_HAS_S2_PLLCST - SoC has S2[PLLCST] + */ + +/* Describe the version of the MCG + * + * These defines are not related to any NXP reference but are merely + * a way to label the versions we are using + */ + +#define KINETIS_MCG_VERSION_UKN -1 /* What was in nuttx prior to 2/5/2017 */ +#define KINETIS_MCG_VERSION_01 1 /* The addition of MK60FN1M0VLQ12 Previously known as KINETIS_NEW_MCG + * Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */ +#define KINETIS_MCG_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ +#define KINETIS_MCG_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +/* MK20DX/DN---VLH5 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40 + * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40 + * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40 + * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40 + * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40 + */ + +#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \ + defined(CONFIG_ARCH_CHIP_MK20DX128VLH5) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +/* MK20DX---VLH7 + * + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40 + * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40 + * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40 + * ------------- ------ --- ------- ------ ------- ------ ----- ---- + */ + +#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \ + defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \ + defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \ + defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100) + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN + +#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) + +/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */ + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_01 + +/* MCG Configuration Parameters */ + +# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */ +# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */ +# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */ +# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 2 /* Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module */ +# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */ +# undef KINETIS_MCG_HAS_IRC_48M /* Has no 48MHz internal oscillator */ +# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */ +# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */ +# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ +# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ + +/* MCD Register Configuration */ + +# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ +# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ +# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */ +# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */ +# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */ +# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */ +# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */ +# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */ +# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */ +# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */ +# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */ +# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */ +# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */ +# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */ +# define KINETIS_MCG_HAS_C5_PLLREFSEL0 1 /* SoC has C5[PLLREFSEL0] */ +# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */ +# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */ +# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */ +# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */ +# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */ +# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */ +# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */ +# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */ +# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */ +# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */ +# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */ +# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */ +# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */ +# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */ +# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */ +# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */ +# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */ +# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */ +# define KINETIS_MCG_C7_OSCSEL_BITS 1 /* C7[OSCSEL] is n bits wide */ +# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */ +# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */ +# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */ +# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */ +# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */ +# undef KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */ +# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */ +# undef KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */ +# undef KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */ +# define KINETIS_MCG_HAS_C10 /* SoC has C10 Register */ +# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */ +# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */ +# define KINETIS_MCG_HAS_C11_PLL1OSC1 1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */ +# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */ +# define KINETIS_MCG_HAS_C11_PLLREFSEL1 1 /* SoC has C11[PLLREFSEL1] */ +# define KINETIS_MCG_HAS_C12 /* SoC has C12 Register */ +# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */ +# define KINETIS_MCG_HAS_S2_PLL1OSC1 1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */ +# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */ + +# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_04 + +/* MCG Configuration Parameters */ + +# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */ +# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */ +# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */ +# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */ +# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */ +# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */ +# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */ +# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */ +# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ +# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ + +/* MCD Register Configuration */ + +# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ +# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ +# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */ +# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */ +# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */ +# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */ +# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */ +# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */ +# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */ +# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */ +# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */ +# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */ +# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */ +# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */ +# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */ +# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */ +# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */ +# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */ +# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */ +# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */ +# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */ +# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */ +# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */ +# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */ +# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */ +# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */ +# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */ +# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */ +# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */ +# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */ +# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */ +# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */ +# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */ +# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */ +# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */ +# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */ +# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */ +# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */ +# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */ +# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */ +# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */ +# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */ +# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */ +# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */ +# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */ +# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */ +# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */ +# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */ +# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */ +# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */ +# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */ +# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */ +# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */ + +/* MK66F N/X 1M0/2M0 V MD/LQ 18 + * + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO + * FREQ CNT FLASH FLASH + * --------------- ------- --- ------- ------- ------ ------ ------ ----- + * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100 + * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100 + * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100 + * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100 + */ +#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */ + +# define KINETIS_MCG_VERSION KINETIS_K_MCG_VERSION_06 + +/* MCG Configuration Parameters */ + +# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */ +# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */ +# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */ +# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */ +# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */ +# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */ +# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */ +# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */ +# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ +# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ + +/* MCD Register Configuration */ + +# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ +# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ +# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */ +# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */ +# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */ +# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */ +# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */ +# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */ +# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */ +# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */ +# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */ +# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */ +# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */ +# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */ +# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */ +# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */ +# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */ +# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */ +# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */ +# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */ +# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */ +# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */ +# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */ +# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */ +# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */ +# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */ +# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */ +# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */ +# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */ +# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */ +# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */ +# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */ +# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */ +# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */ +# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */ +# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */ +# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */ +# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */ +# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */ +# define KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */ +# define KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */ +# define KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */ +# define KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */ +# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */ +# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */ +# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */ +# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */ +# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */ +# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */ +# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */ +# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */ +# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */ +# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */ + +#else +# error "Unsupported Kinetis chip" +#endif + +/* Use the catch all configuration for the MCG based on the implementations in nuttx prior 2/3/2017 */ + +#if KINETIS_MCG_VERSION == KINETIS_MCG_VERSION_UKN + +/* MCG Configuration Parameters */ + +# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */ +# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */ +# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */ +# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */ +# define KINETIS_MCG_FFCLK_DIVBY 1 /* MCGFFCLK divided by 1 */ +# undef KINETIS_MCG_HAS_IRC_48M /* Has 48MHz internal oscillator */ +# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */ +# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */ +# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */ +# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */ + +/* MCD Register Configuration */ + +# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */ +# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */ +# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */ +# define KINETIS_MCG_C1_FRDIV_MAX 5 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */ +# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */ +# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */ +# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */ +# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */ +# undef KINETIS_MCG_HAS_C2_LOCRE0 /* SoC has C2[LOCRE0] */ +# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */ +# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */ +# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */ +# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */ +# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */ +# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */ +# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */ +# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */ +# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */ +# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */ +# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */ +# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */ +# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */ +# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */ +# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */ +# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */ +# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */ +# define KINETIS_MCG_HAS_ATC 1 /* SoC has ATC Register */ +# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */ +# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */ +# undef KINETIS_MCG_HAS_SC /* SoC has SC Register */ +# undef KINETIS_MCG_HAS_SC_ATMS /* SoC has SC[ATMS] */ +# undef KINETIS_MCG_HAS_SC_ATMF /* SoC has SC[ATMF] */ +# undef KINETIS_MCG_HAS_SC_ATME /* SoC has SC[ATME] */ +# undef KINETIS_MCG_HAS_C7 /* SoC has C7 Register */ +# undef KINETIS_MCG_HAS_C7_OSCSEL /* SoC has C7[OSCSEL] */ +# undef KINETIS_MCG_C7_OSCSEL_BITS /* C7[OSCSEL] is n bits wide */ +# undef KINETIS_MCG_HAS_C8 /* SoC has C8 Register */ +# undef KINETIS_MCG_HAS_C8_LOCS1 /* SoC has C8[LOCS1] */ +# undef KINETIS_MCG_HAS_C8_CME1 /* SoC has C8[CME1] */ +# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */ +# undef KINETIS_MCG_HAS_C8_LOCRE1 /* SoC has C8[LOCRE1] */ +# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */ +# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */ +# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */ +# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */ +# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */ +# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */ +# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */ +# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */ +# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */ +# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */ +# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */ +# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */ +# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */ +# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */ +#endif + +#if !defined(KINETIS_MCG_VERSION) +# error "No KINETIS_MCG_VERSION defined!" +#endif + +#if defined(KINETIS_MCG_HAS_C5_PRDIV) +# define KINETIS_MCG_C5_PRDIV_MASK ((1 << (KINETIS_MCG_C5_PRDIV_BITS))-1) +#endif + +#if defined(KINETIS_MCG_HAS_C7_OSCSEL) +# define KINETIS_MCG_C7_OSCSEL_MASK ((1 << (KINETIS_MCG_C7_OSCSEL_BITS))-1) +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H */ diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index dfabf05dc53..6ac01b909d2 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -168,6 +168,38 @@ config ARCH_CHIP_MK64FN1M0VMD12 select KINETIS_HAVE_I2C1 select KINETIS_HAVE_I2C2 +config ARCH_CHIP_MK66FX1M0VMD18 + bool "MK66FX1M0VMD18" + select ARCH_FAMILY_K66 + select KINETIS_HAVE_I2C1 + select KINETIS_HAVE_I2C2 + select KINETIS_HAVE_I2C3 + select KINETIS_HAVE_I2C4 + +config ARCH_CHIP_MK66FN2M0VMD18 + bool "MK66FN2M0VMD18" + select ARCH_FAMILY_K66 + select KINETIS_HAVE_I2C1 + select KINETIS_HAVE_I2C2 + select KINETIS_HAVE_I2C3 + select KINETIS_HAVE_I2C4 + +config ARCH_CHIP_MK66FX1M0VLQ18 + bool "MK66FX1M0VLQ18" + select ARCH_FAMILY_K66 + select KINETIS_HAVE_I2C1 + select KINETIS_HAVE_I2C2 + select KINETIS_HAVE_I2C3 + select KINETIS_HAVE_I2C4 + +config ARCH_CHIP_MK66FN2M0VLQ18 + bool "MK66FN2M0VLQ18" + select ARCH_FAMILY_K66 + select KINETIS_HAVE_I2C1 + select KINETIS_HAVE_I2C2 + select KINETIS_HAVE_I2C3 + select KINETIS_HAVE_I2C4 + endchoice # Chip families @@ -188,6 +220,10 @@ config ARCH_FAMILY_K64 bool default n +config ARCH_FAMILY_K66 + bool + default n + menu "Kinetis Peripheral Support" config KINETIS_HAVE_I2C1 @@ -198,6 +234,14 @@ config KINETIS_HAVE_I2C2 bool default n +config KINETIS_HAVE_I2C3 + bool + default n + +config KINETIS_HAVE_I2C4 + bool + default n + config KINETIS_TRACE bool "Trace" default n @@ -255,7 +299,7 @@ config KINETIS_UART5 config KINETIS_ENET bool "Ethernet" default n - depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64 + depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64 || ARCH_FAMILY_K66 select ARCH_HAVE_PHY select ARCH_HAVE_NETDEV_STATISTICS select NET @@ -266,7 +310,7 @@ config KINETIS_ENET config KINETIS_RNGB bool "Random number generator" default n - depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64 + depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64 || ARCH_FAMILY_K66 select ARCH_HAVE_RNG ---help--- Support the random number generator(K6x only) diff --git a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h index 235343de89d..45d50782b05 100644 --- a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h +++ b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h @@ -135,7 +135,7 @@ # define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ # define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ # define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */ +# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */ # define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ # define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ # define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k66memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k66memorymap.h new file mode 100644 index 00000000000..7850d1b74a5 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k66memorymap.h @@ -0,0 +1,241 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k66memorymap.h + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K66 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* K66 Family + * + * The memory map for the following parts is defined in NXP document + * K66P144M180SF5RMV2 Rev. 2, May 2015 + */ + +#if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ + defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) + +# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ + +# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped + * to same space of 0x88000000 - + * 0x8FFF_FFFF. See bit31 of + * SDRAMC */ +# if defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +# else +# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash + * only: Programming acceleration + * RAM */ +# endif +# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped + * to same space of 0x9800_0000 - + * 0x9BFF_FFFF. See bit31 of + * FlexBus chip select */ +# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * -0x21ffffff Reserved */ +# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x2fffffff Reserved */ +# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */ +# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */ +# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ +# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ +# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */ +# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */ +# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */ +# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */ +# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/ +# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */ +# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ +# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */ +# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ +# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ +# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +# define KINETIS_CRC_BASE 0x40032000 /* CRC */ +# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ +# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ +# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */ +# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */ +# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ +# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ +# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ +# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */ +# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */ +# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */ +# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ +# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */ +/* define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ +# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ +# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */ +# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */ +# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */ +# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ +# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */ +# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */ +# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + +#else + /* The memory map for other parts is defined in other documents and may or may not + * be the same as above (the family members are all very similar) This error just + * means that you have to look at the document and determine for yourself if the + * memory map is the same. + */ + +# error "No memory map for this K66 part" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_K66 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_mcg.h b/arch/arm/src/kinetis/chip/kinetis_mcg.h index 42e2f14412c..e9037ce1be4 100644 --- a/arch/arm/src/kinetis/chip/kinetis_mcg.h +++ b/arch/arm/src/kinetis/chip/kinetis_mcg.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/src/kinetis/chip/kinetis_mcg.h * - * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -39,30 +40,56 @@ /************************************************************************************ * Included Files ************************************************************************************/ - #include #include "chip.h" - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ - /* Register Offsets *****************************************************************/ -#define KINETIS_MCG_C1_OFFSET 0x0000 /* MCG Control 1 Register */ -#define KINETIS_MCG_C2_OFFSET 0x0001 /* MCG Control 2 Register */ -#define KINETIS_MCG_C3_OFFSET 0x0002 /* MCG Control 3 Register */ -#define KINETIS_MCG_C4_OFFSET 0x0003 /* MCG Control 4 Register */ -#define KINETIS_MCG_C5_OFFSET 0x0004 /* MCG Control 5 Register */ -#define KINETIS_MCG_C6_OFFSET 0x0005 /* MCG Control 6 Register */ -#define KINETIS_MCG_S_OFFSET 0x0006 /* MCG Status Register */ -#define KINETIS_MCG_ATC_OFFSET 0x0008 /* MCG Auto Trim Control Register */ -#define KINETIS_MCG_ATCVH_OFFSET 0x000a /* MCG Auto Trim Compare Value High Register */ -#define KINETIS_MCG_ATCVL_OFFSET 0x000b /* MCG Auto Trim Compare Value Low Register */ -#ifdef KINETIS_K64 -# define KINETIS_MCG_C7_OFFSET 0x000c /* MCG Control 7 Register */ -# define KINETIS_MCG_C8_OFFSET 0x000d /* MCG Control 8 Register */ +#define KINETIS_MCG_C1_OFFSET 0x0000 /* MCG Control 1 Register */ +#define KINETIS_MCG_C2_OFFSET 0x0001 /* MCG Control 2 Register */ +#define KINETIS_MCG_C3_OFFSET 0x0002 /* MCG Control 3 Register */ +#define KINETIS_MCG_C4_OFFSET 0x0003 /* MCG Control 4 Register */ +#define KINETIS_MCG_C5_OFFSET 0x0004 /* MCG Control 5 Register */ +#define KINETIS_MCG_C6_OFFSET 0x0005 /* MCG Control 6 Register */ +#define KINETIS_MCG_S_OFFSET 0x0006 /* MCG Status Register */ +#if defined(KINETIS_MCG_HAS_ATC) && !defined(KINETIS_MCG_HAS_SC) +# define KINETIS_MCG_ATC_OFFSET 0x0008 /* MCG Auto Trim Control Register */ +#endif +#if defined(KINETIS_MCG_HAS_SC) +# define KINETIS_MCG_SC_OFFSET 0x0008 /* MMCG Status and Control Register */ +#endif +#if defined(KINETIS_MCG_HAS_ATCVH) +# define KINETIS_MCG_ATCVH_OFFSET 0x000a /* MCG Auto Trim Compare Value High Register */ +#endif +#if defined(KINETIS_MCG_HAS_ATCVL) +# define KINETIS_MCG_ATCVL_OFFSET 0x000b /* MCG Auto Trim Compare Value Low Register */ +#endif +#if defined(KINETIS_MCG_HAS_C7) +# define KINETIS_MCG_C7_OFFSET 0x000c /* MCG Control 7 Register */ +#endif +#if defined(KINETIS_MCG_HAS_C8) +# define KINETIS_MCG_C8_OFFSET 0x000d /* MCG Control 8 Register */ +#endif +#if defined(KINETIS_MCG_HAS_C9) +# define KINETIS_MCG_C9_OFFSET 0x000e /* MCG Control 9 Register */ +#endif +#if defined(KINETIS_MCG_HAS_C10) +# define KINETIS_MCG_C10_OFFSET 0x000f /* MCG Control 10 Register */ +#endif +#if defined(KINETIS_MCG_HAS_C11) +# define KINETIS_MCG_C11_OFFSET 0x0010 /* MCG Control 11 Register */ +#endif +#if defined(KINETIS_MCG_HAS_C12) +# define KINETIS_MCG_C12_OFFSET 0x0011 /* MCG Control 12 Register */ +#endif +#if defined(KINETIS_MCG_HAS_S2) +# define KINETIS_MCG_S2_OFFSET 0x0012 /* MCG Control S2 Register */ +#endif +#if defined(KINETIS_MCG_HAS_T3) +# define KINETIS_MCG_T3_OFFSET 0x0013 /* MCG Control T3 Register */ #endif /* Register Addresses ***************************************************************/ @@ -74,119 +101,323 @@ #define KINETIS_MCG_C5 (KINETIS_MCG_BASE+KINETIS_MCG_C5_OFFSET) #define KINETIS_MCG_C6 (KINETIS_MCG_BASE+KINETIS_MCG_C6_OFFSET) #define KINETIS_MCG_S (KINETIS_MCG_BASE+KINETIS_MCG_S_OFFSET) -#define KINETIS_MCG_ATC (KINETIS_MCG_BASE+KINETIS_MCG_ATC_OFFSET) -#define KINETIS_MCG_ATCVH (KINETIS_MCG_BASE+KINETIS_MCG_ATCVH_OFFSET) -#define KINETIS_MCG_ATCVL (KINETIS_MCG_BASE+KINETIS_MCG_ATCVL_OFFSET) -#ifdef KINETIS_K64 +#if defined(KINETIS_MCG_HAS_ATC) && !defined(KINETIS_MCG_HAS_SC) +# define KINETIS_MCG_ATC (KINETIS_MCG_BASE+KINETIS_MCG_ATC_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_SC) +# define KINETIS_MCG_SC (KINETIS_MCG_BASE+KINETIS_MCG_SC_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_ATCVH) +# define KINETIS_MCG_ATCVH (KINETIS_MCG_BASE+KINETIS_MCG_ATCVH_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_ATCVL) +# define KINETIS_MCG_ATCVL (KINETIS_MCG_BASE+KINETIS_MCG_ATCVL_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_C7) # define KINETIS_MCG_C7 (KINETIS_MCG_BASE+KINETIS_MCG_C7_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_C8) # define KINETIS_MCG_C8 (KINETIS_MCG_BASE+KINETIS_MCG_C8_OFFSET) #endif +#if defined(KINETIS_MCG_HAS_C9) +# define KINETIS_MCG_C9 (KINETIS_MCG_BASE+KINETIS_MCG_C9_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_C10) +# define KINETIS_MCG_C10 (KINETIS_MCG_BASE+KINETIS_MCG_C10_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_C11) +# define KINETIS_MCG_C11 (KINETIS_MCG_BASE+KINETIS_MCG_C11_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_C12) +# define KINETIS_MCG_C12 (KINETIS_MCG_BASE+KINETIS_MCG_C12_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_S2) +# define KINETIS_MCG_S2 (KINETIS_MCG_BASE+KINETIS_MCG_S2_OFFSET) +#endif +#if defined(KINETIS_MCG_HAS_T3) +# define KINETIS_MCG_T3 (KINETIS_MCG_BASE+KINETIS_MCG_T3_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ /* MCG Control 1 Register (8-bit) */ -#define MCG_C1_IREFSTEN (1 << 0) /* Bit 0: Internal Reference Stop Enable */ -#define MCG_C1_IRCLKEN (1 << 1) /* Bit 1: Internal Reference Clock Enable */ -#define MCG_C1_IREFS (1 << 2) /* Bit 2: Internal Reference Select */ -#define MCG_C1_FRDIV_SHIFT (3) /* Bits 3-5: FLL External Reference Divider */ -#define MCG_C1_FRDIV_MASK (7 << MCG_C1_FRDIV_SHIFT) -# define MCG_C1_FRDIV_R0DIV1 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=1 */ -# define MCG_C1_FRDIV_R0DIV2 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=2 */ -# define MCG_C1_FRDIV_R0DIV4 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=4 */ -# define MCG_C1_FRDIV_R0DIV8 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=8 */ -# define MCG_C1_FRDIV_R0DIV16 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=16 */ -# define MCG_C1_FRDIV_R0DIV32 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=32 */ -# define MCG_C1_FRDIV_R0DIV64 (6 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=64 */ -# define MCG_C1_FRDIV_R0DIV128 (7 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=128 */ -# define MCG_C1_FRDIV_DIV32 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=32 */ -# define MCG_C1_FRDIV_DIV64 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=64 */ -# define MCG_C1_FRDIV_DIV128 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=128 */ -# define MCG_C1_FRDIV_DIV256 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=256 */ -# define MCG_C1_FRDIV_DIV512 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=512 */ -# define MCG_C1_FRDIV_DIV1024 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1024 */ -#define MCG_C1_CLKS_SHIFT (6) /* Bits 6-7: Clock Source Select */ -#define MCG_C1_CLKS_MASK (3 << MCG_C1_CLKS_SHIFT) -# define MCG_C1_CLKS_PLL (0 << MCG_C1_CLKS_SHIFT) /* FLL or PLL output */ -# define MCG_C1_CLKS_INTREF (1 << MCG_C1_CLKS_SHIFT) /* Internal reference clock */ -# define MCG_C1_CLKS_EXTREF (2 << MCG_C1_CLKS_SHIFT) /* External reference clock */ +#define MCG_C1_IREFSTEN (1 << 0) /* Bit 0: Internal Reference Stop Enable */ +#define MCG_C1_IRCLKEN (1 << 1) /* Bit 1: Internal Reference Clock Enable */ +#if defined(KINETIS_MCG_HAS_C1_IREFS) +# define MCG_C1_IREFS (1 << 2) /* Bit 2: Internal Reference Select */ +#endif +#if defined(KINETIS_MCG_HAS_C1_FRDIV) +# define MCG_C1_FRDIV_SHIFT (3) /* Bits 3-5: FLL External Reference Divider */ +# define MCG_C1_FRDIV_MASK (7 << MCG_C1_FRDIV_SHIFT) +# define MCG_C1_FRDIV_R0DIV1 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=1 */ +# define MCG_C1_FRDIV_R0DIV2 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=2 */ +# define MCG_C1_FRDIV_R0DIV4 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=4 */ +# define MCG_C1_FRDIV_R0DIV8 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=8 */ +# define MCG_C1_FRDIV_R0DIV16 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=16 */ +# define MCG_C1_FRDIV_R0DIV32 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=32 */ +# define MCG_C1_FRDIV_R0DIV64 (6 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=64 */ +# define MCG_C1_FRDIV_R0DIV128 (7 << MCG_C1_FRDIV_SHIFT) /* RANGE==0 divider=128 */ +# define MCG_C1_FRDIV_DIV32 (0 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=32 */ +# define MCG_C1_FRDIV_DIV64 (1 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=64 */ +# define MCG_C1_FRDIV_DIV128 (2 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=128 */ +# define MCG_C1_FRDIV_DIV256 (3 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=256 */ +# define MCG_C1_FRDIV_DIV512 (4 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=512 */ +# define MCG_C1_FRDIV_DIV1024 (5 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1024 */ +# if KINETIS_MCG_C1_FRDIV_MAX > 5 +# define MCG_C1_FRDIV_DIV1280 (6 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1280 */ +# endif +# if KINETIS_MCG_C1_FRDIV_MAX > 6 +# define MCG_C1_FRDIV_DIV1536 (7 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1536 */ +# endif +#endif /* defined (KINETIS_MCG_HAS _C1_FRDIV) */ +#define MCG_C1_CLKS_SHIFT (6) /* Bits 6-7: Clock Source Select */ +#define MCG_C1_CLKS_MASK (3 << MCG_C1_CLKS_SHIFT) +# define MCG_C1_CLKS_PLL (0 << MCG_C1_CLKS_SHIFT) /* FLL or PLL output */ +# define MCG_C1_CLKS_INTREF (1 << MCG_C1_CLKS_SHIFT) /* Internal reference clock */ +# define MCG_C1_CLKS_EXTREF (2 << MCG_C1_CLKS_SHIFT) /* External reference clock */ /* MCG Control 2 Register */ -#define MCG_C2_IRCS (1 << 0) /* Bit 0: Internal Reference Clock Select */ -#define MCG_C2_LP (1 << 1) /* Bit 1: Low Power Select */ -#define MCG_C2_EREFS (1 << 2) /* Bit 2: External Reference Select */ -#define MCG_C2_HGO (1 << 3) /* Bit 3: High Gain Oscillator Select */ -#define MCG_C2_RANGE_SHIFT (4) /* Bits 4-5: Frequency Range Select */ -#define MCG_C2_RANGE_MASK (3 << MCG_C2_RANGE_SHIFT) -# define MCG_C2_RANGE_LOW (0 << MCG_C2_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */ -# define MCG_C2_RANGE_HIGH (1 << MCG_C2_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */ -# define MCG_C2_RANGE_VHIGH (2 << MCG_C2_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */ - /* Bits 6-7: Reserved */ +#define MCG_C2_IRCS (1 << 0) /* Bit 0: Internal Reference Clock Select */ +#define MCG_C2_LP (1 << 1) /* Bit 1: Low Power Select */ +#define MCG_C2_EREFS (1 << 2) /* Bit 2: External Reference Select */ +#if defined(KINETIS_MCG_HAS_C2_HGO) +# define MCG_C2_HGO (1 << 3) /* Bit 3: High Gain Oscillator Select */ +#endif +#if defined(KINETIS_MCG_HAS_C2_RANGE) +# define MCG_C2_RANGE_SHIFT (4) /* Bits 4-5: Frequency Range Select */ +# define MCG_C2_RANGE_MASK (3 << MCG_C2_RANGE_SHIFT) +# define MCG_C2_RANGE_LOW (0 << MCG_C2_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */ +# define MCG_C2_RANGE_HIGH (1 << MCG_C2_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */ +# define MCG_C2_RANGE_VHIGH (2 << MCG_C2_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */ +#endif +#if defined(KINETIS_MCG_HAS_C2_FCFTRIM) +# define MCG_C2_FCFTRIM (1 << 6) /* Bit 6: Fast Internal Reference Clock Fine Trim */ +#endif +#if defined(KINETIS_MCG_HAS_C2_LOCRE0) +# define MCG_C2_LOCRE0 (1 << 7) /* Bit 7: Loss of Clock Reset Enable */ +#endif + /* MCG Control 3 Register (8-bit Slow Internal Reference Clock Trim Setting) */ /* MCG Control 4 Register (8-bit) */ -#define MCG_C4_SCFTRIM (1 << 0) /* Bit 0: Slow Internal Reference Clock Fine Trim */ -#define MCG_C4_FCTRIM_SHIFT (1) /* Bits 1-4: Fast Internal Reference Clock Trim Setting */ -#define MCG_C4_FCTRIM_MASK (15 << MCG_C4_FCTRIM_SHIFT) -#define MCG_C4_DRST_DRS_SHIFT (5) /* Bits 5-6: DCO Range Select */ -#define MCG_C4_DRST_DRS_MASK (3 << MCG_C4_DRST_DRS_SHIFT) -# define MCG_C4_DRST_DRS_LOW (nn << MCG_C4_DRST_DRS_SHIFT) -# define MCG_C4_DRST_DRS_MID (nn << MCG_C4_DRST_DRS_SHIFT) -# define MCG_C4_DRST_DRS_MIDHIGH (nn << MCG_C4_DRST_DRS_SHIFT) -# define MCG_C4_DRST_DRS_HIGH (nn << MCG_C4_DRST_DRS_SHIFT) -#define MCG_C4_DMX32 (1 << 7) /* Bit 7: DCO Maximum Frequency with 32.768 kHz Reference */ +#define MCG_C4_SCFTRIM (1 << 0) /* Bit 0: Slow Internal Reference Clock Fine Trim */ +#define MCG_C4_FCTRIM_SHIFT (1) /* Bits 1-4: Fast Internal Reference Clock Trim Setting */ +#define MCG_C4_FCTRIM_MASK (15 << MCG_C4_FCTRIM_SHIFT) +#define MCG_C4_DRST_DRS_SHIFT (5) /* Bits 5-6: DCO Range Select */ +#define MCG_C4_DRST_DRS_MASK (3 << MCG_C4_DRST_DRS_SHIFT) +# define MCG_C4_DRST_DRS_LOW (00 << MCG_C4_DRST_DRS_SHIFT) +# define MCG_C4_DRST_DRS_MID (01 << MCG_C4_DRST_DRS_SHIFT) +# define MCG_C4_DRST_DRS_MIDHIGH (10 << MCG_C4_DRST_DRS_SHIFT) +# define MCG_C4_DRST_DRS_HIGH (11 << MCG_C4_DRST_DRS_SHIFT) +#define MCG_C4_DMX32 (1 << 7) /* Bit 7: DCO Maximum Frequency with 32.768 kHz Reference */ /* MCG Control 5 Register */ -#define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-4: PLL External Reference Divider */ -#define MCG_C5_PRDIV_MASK (31 << MCG_C5_PRDIV_SHIFT) -# define MCG_C5_PRDIV(n) ((uint32_t)((n)-1) << MCG_C5_PRDIV_SHIFT) /* n=1..25 */ -#define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */ -#define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */ - /* Bit 7: Reserved */ +#if defined(KINETIS_MCG_HAS_C5_PRDIV) +# define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-[2|4]: PLL External Reference Divider */ +# define MCG_C5_PRDIV_MASK (KINETIS_MCG_C5_PRDIV_MASK << MCG_C5_PRDIV_SHIFT) +# define MCG_C5_PRDIV(n) ((((n) & KINETIS_MCG_C5_PRDIV_MASK)-KINETIS_MCG_C5_PRDIV_BASE) << MCG_C5_PRDIV_SHIFT) /* n=KINETIS_MCG_C5_PRDIV_BASE..KINETIS_MCG_C5_PRDIV_MAX */ +#endif +#define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */ +#define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */ +#if defined(KINETIS_MCG_HAS_C5_PLLREFSEL0) +# define MCG_C5_PLLREFSEL0 (1 << 7) /* Bit 7: PLL0 External Reference Select */ +#endif /* MCG Control 6 Register */ - -#define MCG_C6_VDIV_SHIFT (0) /* Bits 0-4: VCO Divider */ -#define MCG_C6_VDIV_MASK (31 << MCG_C6_VDIV_SHIFT) -#ifdef KINETIS_NEW_MCG -# define MCG_C6_VDIV(n) ((uint32_t)((n)-16) << MCG_C6_VDIV_SHIFT) /* n=16..47 */ -#else -# define MCG_C6_VDIV(n) ((uint32_t)((n)-24) << MCG_C6_VDIV_SHIFT) /* n=24..55 */ +#if defined(KINETIS_MCG_HAS_C6_VDIV) +# define MCG_C6_VDIV_SHIFT (0) /* Bits 0-4: VCO Divider */ +# define MCG_C6_VDIV_MASK (31 << MCG_C6_VDIV_SHIFT) +# define MCG_C6_VDIV(n) (((n)-KINETIS_MCG_C6_VDIV_BASE) << MCG_C6_VDIV_SHIFT) /* n=KINETIS_MCG_C6_VDIV_BASE..KINETIS_MCG_C6_VDIV_MAX */ +#endif +#if defined(KINETIS_MCG_HAS_C6_CME) +# define MCG_C6_CME (1 << 5) /* Bit 5: Clock Monitor Enable */ +#endif +#if defined(KINETIS_MCG_HAS_C6_PLLS) +# define MCG_C6_PLLS (1 << 6) /* Bit 6: PLL Select */ +#endif +#if defined(KINETIS_MCG_HAS_C6_LOLIE0) +# define MCG_C6__LOLIE0 (1 << 7) /* Bit 7: Loss of Lock Interrupt Enable */ #endif -#define MCG_C6_CME (1 << 5) /* Bit 5: Clock Monitor Enable */ -#define MCG_C6_PLLS (1 << 6) /* Bit 6: PLL Select */ -#define MCG_C6_LOLIE (1 << 7) /* Bit 7: Loss of Lock Interrrupt Enable */ /* MCG Status Register */ -#define MCG_S_IRCST (1 << 0) /* Bit 0: Internal Reference Clock Status */ -#define MCG_S_OSCINIT (1 << 1) /* Bit 1: OSC Initialization */ -#define MCG_S_CLKST_SHIFT (2) /* Bits 2-3: Clock Mode Status */ -#define MCG_S_CLKST_MASK (3 << MCG_S_CLKST_SHIFT) -# define MCG_S_CLKST_FLL (0 << MCG_S_CLKST_SHIFT) /* Output of the FLL */ -# define MCG_S_CLKST_INTREF (1 << MCG_S_CLKST_SHIFT) /* Internal reference clock */ -# define MCG_S_CLKST_EXTREF (2 << MCG_S_CLKST_SHIFT) /* External reference clock */ -# define MCG_S_CLKST_PLL (3 << MCG_S_CLKST_SHIFT) /* Output of the PLL */ -#define MCG_S_IREFST (1 << 4) /* Bit 4: Internal Reference Status */ -#define MCG_S_PLLST (1 << 5) /* Bit 5: PLL Select Status */ -#define MCG_S_LOCK (1 << 6) /* Bit 6: Lock Status */ -#define MCG_S_LOLS (1 << 7) /* Bit 7: Loss of Lock Status */ +#if defined(KINETIS_MCG_HAS_S) +# define MCG_S_IRCST (1 << 0) /* Bit 0: Internal Reference Clock Status */ +# define MCG_S_OSCINIT (1 << 1) /* Bit 1: OSC Initialization */ +# define MCG_S_CLKST_SHIFT (2) /* Bits 2-3: Clock Mode Status */ +# define MCG_S_CLKST_MASK (3 << MCG_S_CLKST_SHIFT) +# define MCG_S_CLKST_FLL (0 << MCG_S_CLKST_SHIFT) /* Output of the FLL */ +# define MCG_S_CLKST_INTREF (1 << MCG_S_CLKST_SHIFT) /* Internal reference clock */ +# define MCG_S_CLKST_EXTREF (2 << MCG_S_CLKST_SHIFT) /* External reference clock */ +# define MCG_S_CLKST_PLL (3 << MCG_S_CLKST_SHIFT) /* Output of the PLL */ +# define MCG_S_IREFST (1 << 4) /* Bit 4: Internal Reference Status */ +# if defined(KINETIS_MCG_HAS_S_PLLST) +# define MCG_S_PLLST (1 << 5) /* Bit 5: PLL Select Status */ +# endif +# if defined(KINETIS_MCG_HAS_S_LOCK0) +# define MCG_S_LOCK0 (1 << 6) /* Bit 6: Lock Status */ +# endif +# if defined(KINETIS_MCG_HAS_S_LOLS) +# define MCG_S_LOLS (1 << 7) /* Bit 7: Loss of Lock Status */ +# endif +#endif /* MCG Auto Trim Control Register */ - /* Bits 0-4: Reserved */ -#define MCG_ATC_ATMF (1 << 5) /* Bit 5: Automatic Trim machine Fail Flag */ -#define MCG_ATC_ATMS (1 << 6) /* Bit 6: Automatic Trim Machine Select */ -#define MCG_ATC_ATME (1 << 7) /* Bit 7: Automatic Trim Machine Enable */ + +#if defined(KINETIS_MCG_HAS_ATC) && !defined(KINETIS_MCG_HAS_SC) + /* Bits 0-4: Reserved */ +# define MCG_ATC_ATMF (1 << 5) /* Bit 5: Automatic Trim machine Fail Flag */ +# define MCG_ATC_ATMS (1 << 6) /* Bit 6: Automatic Trim Machine Select */ +# define MCG_ATC_ATME (1 << 7) /* Bit 7: Automatic Trim Machine Enable */ +#endif /* MCG Auto Trim Compare Value High/Low Registers (8-bit compare value) */ +#if defined(KINETIS_MCG_HAS_SC) +# define MCG_SC_LOCS0 (1 << 0) /* Bit 0: OSC0 Loss of Clock Status */ +# define MCG_SC_FCRDIV_SHIFT (1) /* Bits 1-3: Fast Clock Internal Reference Divider */ +# define MCG_SC_FCRDIV_MASK (7 << MCG_SC_FLTPRSRV_SHIFT) +# define MCG_SC_FCRDIV(n) (((n)) << MCG_SC_FLTPRSRV_SHIFT) /* n=0..7 */ +# define MCG_SC_FCRDIV_1 (0 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 1 */ +# define MCG_SC_FCRDIV_2 (1 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 2 */ +# define MCG_SC_FCRDIV_4 (2 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 4 */ +# define MCG_SC_FCRDIV_8 (3 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 8 */ +# define MCG_SC_FCRDIV_16 (4 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 16 */ +# define MCG_SC_FCRDIV_32 (5 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 32 */ +# define MCG_SC_FCRDIV_64 (6 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 64 */ +# define MCG_SC_FCRDIV_128 (7 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 128 */ +# define MCG_SC_FLTPRSRV (1 << 4) /* Bit 4: FLL Filter Preserve Enable */ +# if defined(KINETIS_MCG_HAS_SC_ATMF) +# define MCG_SC_ATMF (1 << 5) /* Bit 5: Automatic Trim machine Fail Flag */ +# endif +# if defined(KINETIS_MCG_HAS_SC_ATMS) +# define MCG_SC_ATMS (1 << 6) /* Bit 6: Automatic Trim Machine Select */ +# endif +# if defined(KINETIS_MCG_HAS_SC_ATME) +# define MCG_ASC_ATME (1 << 7) /* Bit 7: Automatic Trim Machine Enable */ +# endif +#endif + /* MCG Control 7 Register */ +#if defined(KINETIS_MCG_HAS_C7) +# if defined(KINETIS_MCG_HAS_C7_OSCSEL) +# define MCG_C7_OSCSEL_SHIFT (0) /* Bits 0-[1]: MCG OSC Clock Select */ +# define MCG_C7_OSCSEL_MASK (KINETIS_MCG_C7_OSCSEL_MASK << MCG_C7_OSCSEL_SHIFT) +# define MCG_C7_OSCSEL_OSCCLK (0 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK) */ +# define MCG_C7_OSCSEL_32KHZ (1 << MCG_C7_OSCSEL_SHIFT) /* Selects 32 kHz RTC Oscillator */ +# if (KINETIS_MCG_C7_OSCSEL_MASK & 2) != 0 +# define MCG_C7_OSCSEL_OSCCLK1 (2 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK1). */ +# endif +# endif +#endif + /* MCG Control 8 Register */ +#if defined(KINETIS_MCG_HAS_C8) +# if defined(KINETIS_MCG_HAS_C8_LOCS1) +# define MCG_C8_LOCS1 (1 << 0) /* Bit 0: RTC Loss of Clock Status */ +# endif + /* Bits 1-4: Reserved */ +# if defined(KINETIS_MCG_HAS_C8_CME1) +# define MCG_C8_CME1 (1 << 5) /* Bit 5: Clock Monitor Enable1 */ +# endif +# if defined(KINETIS_MCG_HAS_C8_LOLRE) +# define MCG_C8_LOLRE (1 << 6) /* Bit 6: PLL Loss of Lock Reset Enable */ +# endif +# if defined(KINETIS_MCG_HAS_C8_LOCRE1) +# define MCG_C8_LOCRE1 (1 << 7) /* Bit 7: Loss of Clock Reset Enable */ +# endif +#endif + +/* MCG Control 9 Register */ + +#if defined(KINETIS_MCG_HAS_C9) +# if defined(KINETIS_MCG_HAS_C9_EXT_PLL_LOCS) +# define MCG_C9_EXT_PLL_LOCS (1 << 0) /* Bit 0: External PLL Loss of Clock Status */ +# endif + /* Bits 1-3: Reserved */ +# if defined(KINETIS_MCG_HAS_C9_PLL_LOCRE) +# define MCG_C9_EXT_PLL_LOCRE (1 << 4) /* Bit 4: MCG External PLL Loss of Clock Reset Enable */ +# endif +# if defined(KINETIS_MCG_HAS_C9_PLL_CME) +# define MCG_C9_EXT_C9_PLL_CME (1 << 5) /* Bit 5: MCG External PLL Clock Monitor Enable */ +# endif + /* Bits 6-7: Reserved */ +#endif + +/* MCG Control 10 Register */ + +#if defined(KINETIS_MCG_HAS_C10) + /* Bits 0-[1]: Reserved */ +# if defined(KINETIS_MCG_HAS_C10_LOCS1) +# define MCG_C10_LOCS1_SHIFT (1 << 1) /* Bit 1: RTC Loss of Clock Status */ +# endif +# define MCG_C10_EREFS1 (1 << 2) /* Bit 2: External Reference Select */ +# define MCG_C10_HGO1 (1 << 3) /* Bit 3: High Gain Oscillator1 Select */ +# define MCG_C10_RANGE1_SHIFT (4) /* Bits 4-5: Frequency Range1 Select */ +# define MCG_C10_RANGE_MASK (3 << MCG_C10_RANGE_SHIFT) +# define MCG_C10_RANGE_LOW (0 << MCG_C10_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */ +# define MCG_C10_RANGE_HIGH (1 << MCG_C10_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */ +# define MCG_C10_RANGE_VHIGH (2 << MCG_C10_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */ + /* Bit 6: Reserved */ +# define MCG_C10_LOCRE2 (1 << 7) /* Bit 7: OSC1 Loss of Clock Reset Enable */ +#endif + +/* MCG Control 11 Register */ + +#if defined(KINETIS_MCG_HAS_C11) +# if defined(KINETIS_MCG_HAS_C11_PLL1OSC1) +# define MCG_C11_PRDIV1_SHIFT (0) /* Bits 0-2: PLL1 External Reference Divider */ +# define MCG_C11_PRDIV1_MASK (7 << MCG_C11_PRDIV1_SHIFT) +# define MCG_C11_PRDIV1(n) (((n)-1) << MCG_C11_PRDIV_SHIFT) /* 1..8 */ +# endif + /* Bit 3: Reserved */ +# if defined(KINETIS_MCG_HAS_C11_PLLCS) +# define MCG_C11_PLLCS (1 << 4) /* Bit 4: PLL Clock Select */ +# endif +# if defined(KINETIS_MCG_HAS_C11_PLL1OSC1) +# define MCG_C11_PLLSTEN1 (1 << 5) /* Bit 5: PLL1 Stop Enable */ +# define MCG_C11_PLLCLKEN1 (1 << 6) /* Bit 6: PLL1 Clock Enable */ +# endif +# if defined(KINETIS_MCG_HAS_C11_PLLREFSEL1) +# define MCG_C11_PLLREFSEL1 (1 << 7) /* Bit 7: PLL1 External Reference Select */ +# endif +#endif + +/* MCG Control 12 Register */ + +#if defined(KINETIS_MCG_HAS_C12) +# define MCG_C12_VDIV1_SHIFT (0) /* Bits 0-4: VCO Divider */ +# define MCG_C12_VDIV1_MASK (31 << MCG_C12_VDIV1_SHIFT) +# define MCG_C12_VDIV(n) (((n)-16) << MCG_C12_VDIV1_SHIFT) /* n=16..47 */ +# define MCG_C12_CME2 (1 << 5) /* Bit 5: Clock Monitor Enable2 */ + /* Bit 6: Reserved */ +#define MCG_C12_LOLIE1 (1 << 7) /* Bit 7: PLL1 Loss of Lock Interrupt Enable */ +#endif + +/* MCG Control S2 Register */ + +#if defined(KINETIS_MCG_HAS_S2) +# if defined(KINETIS_MCG_HAS_S2_PLL1OSC1) +# define MCG_S2_LOCS2_SHIFT (1 << 0) /* Bit 0: OSC1 Loss of Clock Status */ +# define MCG_S2_OSCINIT1 (1 << 1) /* Bit 1: OSC1 Initialization */ +# endif + /* Bits 2-3: Reserved */ +# if defined(KINETIS_MCG_HAS_S2_PLLCST) +# define MCG_S2_PLLCST (1 << 4) /* Bit 4: PLL Clock Select Status */ +# endif + /* Bit 5: Reserved */ +# if defined(KINETIS_MCG_HAS_S2_PLL1OSC1) +# define MCG_S2_LOCK1 (1 << 6) /* Bit 6: Lock1 Status */ +# define MCG_S2_LOLS1 (1 << 7) /* Bit 7: Loss of Lock1 Status */ +# endif +#endif + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index bac16f218b9..23e47a112ab 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -58,6 +58,96 @@ # error "CONFIG_ARCH_RAMFUNCS must be defined for this logic" #endif +/* A board may provide an override for BOARD_FRDIV */ + +#if !defined(BOARD_FRDIV) +# define BOARD_FRDIV MCG_C1_FRDIV_DIV256 +#endif + +/* A board may provide BOARD_MCG_C2 with all the MCG_C2 setting + * or use individual setting with 0 defaults + */ + +#if !defined(BOARD_MCG_C2) + +/* A board may provide an override for BOARD_EXTCLOCK_MCG_C2 */ + +# if defined(BOARD_EXTCLOCK) +# if defined(BOARD_EXTCLOCK_MCG_C2) +# define EXTCLOCK_MCG_C2 BOARD_EXTCLOCK_MCG_C2 +# else +# define EXTCLOCK_MCG_C2 0 +# endif +# endif + +/* A board may provide BOARD_EXTAL_LP to not choose MCG_C2_HGO */ + +# if defined(BOARD_EXTAL_LP) +# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */ +# else +# if !defined(KINETIS_MCG_HAS_C2_HGO) +# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC! +# else +# define BOARD_MGC_C2_HGO MCG_C2_HGO +# endif +# endif + +/* A board must provide BOARD_MCG_C2_FCFTRIM when SoC has the setting */ + +# if defined(KINETIS_MCG_HAS_C2_FCFTRIM) && !defined(BOARD_MCG_C2_FCFTRIM) +# error MCG_C2_FCFTRIM is supported on this SoC and BOARD_MCG_C2_FCFTRIM is not defined! +# endif + +# if !defined(KINETIS_MCG_HAS_C2_FCFTRIM) && defined(BOARD_MCG_C2_FCFTRIM) +# error BOARD_MCG_C2_FCFTRIM is defined but MCG_C2_FCFTRIM is not supported on this SoC! +# endif + +/* Provide the 0 default */ + +# if !defined(KINETIS_MCG_HAS_C2_FCFTRIM) && !defined(BOARD_MCG_C2_FCFTRIM) +# define BOARD_MCG_C2_FCFTRIM 0 +# endif + +/* A board must provide BOARD_MCG_C2_LOCRE0 when SoC has the setting */ + +# if defined(KINETIS_MCG_HAS_C2_LOCRE0) && !defined(BOARD_MCG_C2_LOCRE0) +# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined! +# endif + +# if !defined(KINETIS_MCG_HAS_C2_LOCRE0) && defined(BOARD_MCG_C2_LOCRE0) +# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC! +# endif + +/* Provide the 0 default */ + +# if !defined(KINETIS_MCG_HAS_C2_LOCRE0) && !defined(BOARD_MCG_C2_LOCRE0) +# define BOARD_MCG_C2_LOCRE0 0 +# endif +#endif /* !defined(BOARD_MCG_C2) */ + +/* Do some sanity checking */ + +#if BOARD_PRDIV > KINETIS_MCG_C5_PRDIV_MAX || \ + BOARD_PRDIV < KINETIS_MCG_C5_PRDIV_BASE +# error BOARD_PRDIV must satisfy KINETIS_MCG_C5_PRDIV_BASE >= \ + BOARD_VDIV <= KINETIS_MCG_C5_PRDIV_MAX +#endif + +#if BOARD_VDIV > KINETIS_MCG_C6_VDIV_MAX || \ + BOARD_VDIV < KINETIS_MCG_C6_VDIV_BASE +# error BOARD_VDIV must satisfy KINETIS_MCG_C6_VDIV_BASE >= \ + BOARD_VDIV <= KINETIS_MCG_C6_VDIV_MAX +#endif + +#if BOARD_PLLIN_FREQ < KINETIS_MCG_PLL_REF_MIN || \ + BOARD_PLLIN_FREQ > KINETIS_MCG_PLL_REF_MAX +# error BOARD_PLLIN_FREQ must satisfy KINETIS_MCG_PLL_REF_MIN >= \ + BOARD_PLLIN_FREQ <= KINETIS_MCG_PLL_REF_MAX +#endif + +#if ((BOARD_FRDIV & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) > KINETIS_MCG_C1_FRDIV_MAX +# error BOARD_FRDIV choice is not supported on this SoC +#endif /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -103,9 +193,16 @@ void kinetis_pllconfig(void) uint32_t regval32; uint8_t regval8; +#if defined(BOARD_MCG_C2) + + /* Use complete BOARD_MCG_C2 settings */ + + putreg8(BOARD_MCG_C2, KINETIS_MCG_C2); +#else + /* Transition to FLL Bypassed External (FBE) mode */ -#ifdef BOARD_EXTCLOCK +# if defined(BOARD_EXTCLOCK) /* IRCS = 0 (Internal Reference Clock Select) * LP = 0 (Low Power Select) * EREFS = 0 (External Reference Select) @@ -113,23 +210,22 @@ void kinetis_pllconfig(void) * RANGE = 0 (Oscillator of 32 kHz to 40 kHz) */ - putreg8(0, KINETIS_MCG_C2); -#else + putreg8(EXTCLOCK_MCG_C2, KINETIS_MCG_C2); +# else /* Enable external oscillator: * - * IRCS = 0 (Internal Reference Clock Select) - * LP = 0 (Low Power Select) - * EREFS = 1 (External Reference Select) - * HGO = 1 (High Gain Oscillator Select) - * RANGE = 2 (Oscillator of 8 MHz to 32 MHz) + * IRCS = 0 (Internal Reference Clock Select) + * LP = 0 (Low Power Select) + * EREFS = 1 (External Reference Select) + * HGO = 1 (High Gain Oscillator Select) + * RANGE = 2 (Oscillator of 8 MHz to 32 MHz) + * FCFTRIM = 0 if not supported or value provided by board + * LOCRE0 = 0 if not supported or value provided by board */ -#ifdef BOARD_EXTAL_LP - putreg8(MCG_C2_EREFS | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2); -#else - putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2); -#endif /* BOARD_EXTAL_LP */ -#endif + putreg8(BOARD_MCG_C2_LOCRE0 | BOARD_MCG_C2_FCFTRIM | BOARD_MGC_C2_HGO | MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2); +# endif +#endif /* defined(BOARD_MCG_C2) */ /* Released latched state of oscillator and GPIO */ @@ -147,15 +243,11 @@ void kinetis_pllconfig(void) * IREFSTEN = 0 (Internal Reference Stop Enable) * IRCLKEN = 0 (Internal Reference Clock Enable) * IREFS = 0 (Internal Reference Select) - * FRDIV = 3 (FLL External Reference Divider, RANGE!=0 divider=256) + * FRDIV = BOARD_FRDIV (FLL External Reference Divider) * CLKS = 2 (Clock Source Select, External reference clock) */ -#ifdef BOARD_FRDIV - putreg8((BOARD_FRDIV << MCG_C1_FRDIV_SHIFT) | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1); -#else - putreg8(MCG_C1_FRDIV_DIV256 | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1); -#endif + putreg8(BOARD_FRDIV | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1); /* If we aren't using an oscillator input we don't need to wait for the * oscillator to initialize @@ -224,7 +316,7 @@ void kinetis_pllconfig(void) /* Wait for the PLL LOCK bit to set */ - while ((getreg8(KINETIS_MCG_S) & MCG_S_LOCK) == 0); + while ((getreg8(KINETIS_MCG_S) & MCG_S_LOCK0) == 0); /* We are now running in PLL Bypassed External (PBE) mode. Transition to * PLL Engaged External (PEE) mode by setting CLKS to 0 diff --git a/configs/freedom-k64f/include/board.h b/configs/freedom-k64f/include/board.h index 4bc7ac9ffcd..a6b7a325081 100644 --- a/configs/freedom-k64f/include/board.h +++ b/configs/freedom-k64f/include/board.h @@ -65,14 +65,15 @@ /* PLL Configuration. Either the external clock or crystal frequency is used to * select the PRDIV value. Only reference clock frequencies are supported that will - * produce a 2MHz reference clock to the PLL. + * produce a KINETIS_MCG_PLL_REF_MIN >= PLLIN <= KINETIS_MCG_PLL_REF_MIN reference + * clock to the PLL. * * PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 Mhz / 20 = 2.5 MHz * PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 Mhz * 48 = 120 MHz * MCG Frequency: PLLOUT = 120 MHz * - * PRDIV register value is the divider minus one. So 20 -> 19 - * VDIV regiser value is offset by 24. So 28 -> 24 + * PRDIV register value is the divider minus KINETIS_MCG_C5_PRDIV_BASE. + * VDIV register value is offset by KINETIS_MCG_C6_VDIV_BASE. */ #define BOARD_PRDIV 20 /* PLL External Reference Divider */ @@ -82,6 +83,11 @@ #define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) #define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ +/* Define additional MCG_C2 Setting */ + +#define BOARD_MCG_C2_FCFTRIM 0 /* Do not enable FCFTRIM */ +#define BOARD_MCG_C2_LOCRE0 MCG_C2_LOCRE0 /* Enable reset on loss of clock */ + /* SIM CLKDIV1 dividers */ #define BOARD_OUTDIV1 1 /* Core = MCG, 120 MHz */ diff --git a/configs/teensy-3.x/include/board.h b/configs/teensy-3.x/include/board.h index b7099de6e8c..80dd9768293 100644 --- a/configs/teensy-3.x/include/board.h +++ b/configs/teensy-3.x/include/board.h @@ -58,13 +58,14 @@ #undef BOARD_EXTCLOCK /* Crystal */ #define BOARD_EXTAL_LP /* Low Power, as opposed to Hi Gain */ -/* BOARD_FR_DIV is MCG_C1_FRDIV_DIV512 from kinetis_mcg.h. According to the k20 +/* BOARD_FRDIV is MCG_C1_FRDIV_DIV512 from kinetis_mcg.h. According to the k20 * reference manual, when transitioning MCG clock modes to FLL Bypassed External * the C1 divider must be set so that the FLL clock is between 31.25 and 39.0625 khz. * For teensy-3.x that works out to a divider of 512. */ -#define BOARD_FR_DIV (4 << 3) +#define BOARD_FRDIV MCG_C1_FRDIV_DIV512 + #define BOARD_EXTAL_FREQ 16000000 /* 16MHz crystal frequency (REFCLK) */ #define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator (not populated) */