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arch/tricore: Regs for context switching save the memory address of the CSA.

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In the exception panic process, regs needs to use a memory address, which defaults to PCXI. Here, it is uniformly saved as the actual memory address.

Signed-off-by: liwenxiang1 <liwenxiang1@xiaomi.com>
This commit is contained in:
liwenxiang1
2024-11-22 14:53:43 +08:00
committed by Xiang Xiao
parent 68a5732d9a
commit 8da6b45939
4 changed files with 10 additions and 9 deletions
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arch/tricore/include/irq.h
+5 -4
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@@ -205,14 +205,15 @@ static inline_function bool up_interrupt_context(void)
static inline_function uintptr_t up_getusrsp(void *regs) static inline_function uintptr_t up_getusrsp(void *regs)
{ {
uintptr_t *csa = regs; uintptr_t *csa = regs;
uintptr_t pcxi = tricore_addr2csa(csa);
while (((uintptr_t)csa & PCXI_UL) == 0) while ((pcxi & PCXI_UL) == 0)
{ {
csa = tricore_csa2addr((uintptr_t)csa); csa = tricore_csa2addr(csa[REG_UPCXI]);
csa = (uintptr_t *)csa[0]; pcxi = csa[REG_UPCXI];
} }
csa = tricore_csa2addr((uintptr_t)csa); csa = tricore_csa2addr(pcxi);
return csa[REG_SP]; return csa[REG_SP];
} }
arch/tricore/src/common/tricore_csa.c
+1 -1
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@@ -82,7 +82,7 @@ uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp,
plcsa[REG_LPCXI] |= PCXI_PIE; plcsa[REG_LPCXI] |= PCXI_PIE;
} }
return (uintptr_t *)tricore_addr2csa(plcsa); return plcsa;
} }
/**************************************************************************** /****************************************************************************
arch/tricore/src/common/tricore_doirq.c
+2 -2
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@@ -56,7 +56,7 @@ IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255)
uintptr_t *regs; uintptr_t *regs;
icr.U = __mfcr(CPU_ICR); icr.U = __mfcr(CPU_ICR);
regs = (uintptr_t *)__mfcr(CPU_PCXI); regs = tricore_csa2addr(__mfcr(CPU_PCXI));
if (running_task != NULL) if (running_task != NULL)
{ {
@@ -112,7 +112,7 @@ IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255)
running_task = tcb; running_task = tcb;
g_running_tasks[this_cpu()] = running_task; g_running_tasks[this_cpu()] = running_task;
__mtcr(CPU_PCXI, (uintptr_t)up_current_regs()); __mtcr(CPU_PCXI, tricore_addr2csa(up_current_regs()));
__isync(); __isync();
} }
arch/tricore/src/common/tricore_svcall.c
+2 -2
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@@ -108,7 +108,7 @@ void tricore_svcall(volatile void *trap)
case SYS_switch_context: case SYS_switch_context:
{ {
*(uintptr_t **)regs[REG_D9] = (uintptr_t *)regs[REG_UPCXI]; *(uintptr_t **)regs[REG_D9] = tricore_csa2addr(regs[REG_UPCXI]);
up_set_current_regs((uintptr_t *)regs[REG_D10]); up_set_current_regs((uintptr_t *)regs[REG_D10]);
} }
break; break;
@@ -133,7 +133,7 @@ void tricore_svcall(volatile void *trap)
g_running_tasks[cpu] = this_task(); g_running_tasks[cpu] = this_task();
regs[REG_UPCXI] = (uintptr_t)up_current_regs(); regs[REG_UPCXI] = tricore_addr2csa(up_current_regs());
__isync(); __isync();
} }